Target/PowerPC/PPCISelLowering.cpp

3038   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3047       if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3052                    CC));
3082   if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3086     return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3145   SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3174   SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3181   OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
4684   auto isTailCallableCC  = [] (CallingConv::ID CC){
4685       return  CC == CallingConv::C || CC == CallingConv::Fast;
7594   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
7603     switch (CC) {
7627     switch (CC) {
7662   switch (CC) {
12337   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
12343     switch (CC) {
12386     ISD::CondCode CC =
12391     if (ISD::isSignedIntSetCC(CC)) {
12395     } else if (ISD::isUnsignedIntSetCC(CC)) {
12928   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
12929   if (CC == ISD::SETNE || CC == ISD::SETEQ) {
12947       return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
14339     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
14356       assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
14360       bool isBDNZ = (CC == ISD::SETEQ && Val) ||
14361                     (CC == ISD::SETNE && !Val);
14377         isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
14385         if (CC == ISD::SETEQ)      // Cond never true, remove branch.
14392       bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
15897   ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15900   switch (CC) {