Lines Matching defs:CC
523 const CallingConv::ID CC;
609 setLibcallCallingConv(LC.Op, LC.CC);
620 const CallingConv::ID CC;
632 setLibcallCallingConv(LC.Op, LC.CC);
643 const CallingConv::ID CC;
657 setLibcallCallingConv(LC.Op, LC.CC);
690 const CallingConv::ID CC;
699 setLibcallCallingConv(LC.Op, LC.CC);
1148 const CallingConv::ID CC;
1163 setLibcallCallingConv(LC.Op, LC.CC);
1169 const CallingConv::ID CC;
1184 setLibcallCallingConv(LC.Op, LC.CC);
1832 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1833 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1834 switch (CC) {
1849 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1850 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1853 switch (CC) {
1886 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1888 switch (CC) {
1895 return CC;
1924 CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1926 return CCAssignFnForNode(CC, false, isVarArg);
1929 CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1931 return CCAssignFnForNode(CC, true, isVarArg);
1936 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1939 switch (getEffectiveCallingConv(CC, isVarArg)) {
4216 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4223 switch (CC) {
4228 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4235 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4242 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4249 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4259 CC = ISD::getSetCCSwappedOperands(CC);
4287 !isSignedIntSetCC(CC)) {
4310 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4324 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4648 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4652 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4653 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4657 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4658 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4663 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4664 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4675 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4676 CC == ISD::SETUGT) {
4684 if (CC == ISD::SETO) {
4692 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4724 static bool isGTorGE(ISD::CondCode CC) {
4725 return CC == ISD::SETGT || CC == ISD::SETGE;
4728 static bool isLTorLE(ISD::CondCode CC) {
4729 return CC == ISD::SETLT || CC == ISD::SETLE;
4732 // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4740 const ISD::CondCode CC, const SDValue K) {
4741 return (isGTorGE(CC) &&
4743 (isLTorLE(CC) &&
4750 const ISD::CondCode CC, const SDValue K) {
4751 return (isGTorGE(CC) &&
4753 (isLTorLE(CC) &&
4878 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4899 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4956 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4978 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
4988 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
4997 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5006 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5014 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5020 CC = ISD::SETNE;
5038 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5041 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5048 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5056 FPCCToARMCC(CC, CondCode, CondCode2);
5069 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5162 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5176 if (CC == ISD::SETOEQ)
5177 CC = ISD::SETEQ;
5178 else if (CC == ISD::SETUNE)
5179 CC = ISD::SETNE;
5188 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5200 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5249 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5257 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5263 CC = ISD::SETNE;
5275 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5285 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5300 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5307 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5308 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5314 FPCCToARMCC(CC, CondCode, CondCode2);
6221 SDValue CC = Op.getOperand(2);
6223 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8920 CallingConv::ID CC = getLibcallCallingConv(LC);
8926 .setCallee(CC, RetTy, Callee, std::move(Args))
9250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get();
9257 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS, Chain, IsSignaling);
9260 CC = ISD::SETNE;
9263 DAG.getCondCode(CC));
9268 FPCCToARMCC(CC, CondCode, CondCode2);
10795 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
10978 // Invert is set when N is the null/all ones constant when CC is false.
10981 SDValue &CC, bool &Invert,
10987 CC = N->getOperand(0);
11010 CC = N->getOperand(0);
11011 if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC)
11066 // Slct is now know to be the desired identity constant when CC is true.
11070 // Unless SwapSelectOps says CC should be false.
12412 static bool isValidMVECond(unsigned CC, bool IsFloat) {
12413 switch (CC) {
14162 auto CC = CCNode->getAPIntValue().getLimitedValue();
14178 if (CC == ARMCC::EQ) {
14183 assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?");
14241 static SDValue SearchLoopIntrinsic(SDValue N, ISD::CondCode &CC, int &Imm,
14252 return SearchLoopIntrinsic(N.getOperand(0), CC, Imm, Negate);
14264 CC = cast<CondCodeSDNode>(N.getOperand(2))->get();
14265 return SearchLoopIntrinsic(N->getOperand(0), CC, Imm, Negate);
14293 ISD::CondCode CC;
14301 CC = ISD::SETEQ;
14306 CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
14317 SDValue Int = SearchLoopIntrinsic(Cond, CC, Imm, Negate);
14322 CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32);
14324 auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) {
14325 return (CC == ISD::SETEQ && Imm == 0) ||
14326 (CC == ISD::SETNE && Imm == 1) ||
14327 (CC == ISD::SETLT && Imm == 1) ||
14328 (CC == ISD::SETULT && Imm == 1);
14331 auto IsFalseIfZero = [](ISD::CondCode CC, int Imm) {
14332 return (CC == ISD::SETEQ && Imm == 1) ||
14333 (CC == ISD::SETNE && Imm == 0) ||
14334 (CC == ISD::SETGT && Imm == 0) ||
14335 (CC == ISD::SETUGT && Imm == 0) ||
14336 (CC == ISD::SETGE && Imm == 1) ||
14337 (CC == ISD::SETUGE && Imm == 1);
14340 assert((IsTrueIfZero(CC, Imm) || IsFalseIfZero(CC, Imm)) &&
14362 if (IsTrueIfZero(CC, Imm)) {
14384 SDValue Target = IsFalseIfZero(CC, Imm) ? Dest : OtherTarget;
14415 ARMCC::CondCodes CC =
14418 // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
14419 // -> (brcond Chain BB CC CPSR Cmp)
14420 if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
14455 ARMCC::CondCodes CC =
14483 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
14486 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
14493 // (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
14494 // -> (cmov F T CC CPSR Cmp)
14495 if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
14513 if (CC == ARMCC::EQ && isOneConstant(TrueVal)) {
14541 } else if (CC == ARMCC::NE && !isNullConstant(RHS) &&
14554 if (CC == ARMCC::EQ && !isNullConstant(RHS) &&
14584 if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&