Target/AMDGPU/SIISelLowering.cpp

796                                                     CallingConv::ID CC,
798   if (CC == CallingConv::AMDGPU_KERNEL)
799     return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
815   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
819                                                          CallingConv::ID CC,
821   if (CC == CallingConv::AMDGPU_KERNEL)
822     return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
840   return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
844   LLVMContext &Context, CallingConv::ID CC,
847   if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
877     Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
2259   // for shaders. Vector types should be explicitly handled by CC.
2580 static bool canGuaranteeTCO(CallingConv::ID CC) {
2581   return CC == CallingConv::Fast;
2585 static bool mayTailCallThisCC(CallingConv::ID CC) {
2586   switch (CC) {
2590     return canGuaranteeTCO(CC);
2720     // Note the issue is with the CC of the calling function, not of the call
9827   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
9834       CC = getSetCCSwappedOperands(CC);
9846            (CC == ISD::SETNE || CC == ISD::SETGT || CC == ISD::SETULT)) ||
9848            (CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
9852            (CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
9854            (CC == ISD::SETNE || CC == ISD::SETUGT || CC == ISD::SETLT)))
9859     if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9873       if ((CF == CRHSVal && CC == ISD::SETEQ) ||
9874           (CT == CRHSVal && CC == ISD::SETNE))
9877       if ((CF == CRHSVal && CC == ISD::SETNE) ||
9878           (CT == CRHSVal && CC == ISD::SETEQ))
9891   if ((CC == ISD::SETOEQ || CC == ISD::SETONE) && LHS.getOpcode() == ISD::FABS) {
9906       unsigned Mask = CC == ISD::SETOEQ ? IsInfMask : IsFiniteMask;