Lines Matching defs:CC
1519 /// CC
1520 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1521 switch (CC) {
1547 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1548 static void changeFPCCToAArch64CC(ISD::CondCode CC,
1552 switch (CC) {
1608 /// Convert a DAG fp condition code to an AArch64 CC.
1611 static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
1615 switch (CC) {
1617 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1638 /// CC usable with the vector instructions. Fewer operations are available
1641 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1646 switch (CC) {
1649 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1666 changeFPCCToAArch64CC(getSetCCInverse(CC, /* FP inverse */ MVT::f32),
1690 static bool isCMN(SDValue Op, ISD::CondCode CC) {
1692 (CC == ISD::SETEQ || CC == ISD::SETNE);
1706 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1728 if (isCMN(RHS, CC)) {
1732 } else if (isCMN(LHS, CC)) {
1738 !isUnsignedIntSetCC(CC)) {
1793 /// ccmp D, inv(CD), CC
1805 ISD::CondCode CC, SDValue CCOp,
1822 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1922 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1925 CC = getSetCCInverse(CC, LHS.getValueType());
1929 OutCC = changeIntCCToAArch64CC(CC);
1933 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
1939 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1941 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
1950 return emitComparison(LHS, RHS, CC, DL, DAG);
1952 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
2074 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2082 switch (CC) {
2091 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2101 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2112 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2123 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2144 SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;
2148 CC = ISD::getSetCCSwappedOperands(CC);
2154 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
2184 CC, dl, DAG);
2185 AArch64CC = changeIntCCToAArch64CC(CC);
2191 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
2198 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2199 AArch64CC = changeIntCCToAArch64CC(CC);
2206 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
2219 CC = AArch64CC::VS;
2223 CC = AArch64CC::HS;
2227 CC = AArch64CC::VS;
2231 CC = AArch64CC::LO;
2236 CC = AArch64CC::NE;
2362 AArch64CC::CondCode CC;
2364 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Sel.getValue(0), DAG);
2365 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
2382 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
2404 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
2410 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2465 AArch64CC::CondCode CC;
2468 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
2477 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
3290 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
3292 switch (CC) {
3325 AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
3326 return CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
3738 static bool canGuaranteeTCO(CallingConv::ID CC) {
3739 return CC == CallingConv::Fast;
3743 static bool mayTailCallThisCC(CallingConv::ID CC) {
3744 switch (CC) {
3750 return canGuaranteeTCO(CC);
4948 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4965 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl, LHS, RHS);
4971 CC = ISD::SETNE;
4978 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4988 if (CC == ISD::SETNE)
5004 if (CC == ISD::SETEQ) {
5020 } else if (CC == ISD::SETNE) {
5036 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
5045 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
5056 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
5064 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5066 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
5068 changeFPCCToAArch64CC(CC, CC1, CC2);
5226 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(OpNo + 2))->get();
5237 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl, LHS, RHS, Chain,
5251 LHS, RHS, ISD::getSetCCInverse(CC, LHS.getValueType()), CCVal, DAG, dl);
5270 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
5273 changeFPCCToAArch64CC(CC, CC1, CC2);
5276 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1,
5285 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
5288 // of the first as the RHS. We're effectively OR'ing the two CC's together.
5301 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
5308 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl, LHS, RHS);
5314 CC = ISD::SETNE;
5339 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5343 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5350 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5358 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5401 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5419 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5430 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5439 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
5449 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
5451 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5454 changeFPCCToAArch64CC(CC, CC1, CC2);
5464 if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETUEQ) &&
5467 else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) &&
5479 // RHS. We're effectively OR'ing the two CC's together.
5491 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5497 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
5524 ISD::CondCode CC;
5529 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
5533 CC = ISD::SETNE;
5535 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
8377 AArch64CC::CondCode CC, bool NoNans, EVT VT,
8390 switch (CC) {
8429 switch (CC) {
8473 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8481 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
8496 SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
8506 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
8510 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
10537 ISD::CondCode CC;
10543 AArch64CC::CondCode CC;
10571 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10585 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
10602 SetCCInfo.Info.AArch64.CC =
10603 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
10647 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), dl,
10653 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG,
10982 // Set condition code (CC) flags.
10985 // Convert CC to integer based on requested condition.
10987 SDValue CC = DAG.getConstant(getInvertedCondCode(Cond), DL, MVT::i32);
10988 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);
11810 // | Input | | AddConstant | | CompConstant| | CC |
11832 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
11866 static bool isEquivalentMaskless(unsigned CC, unsigned width,
11882 switch(CC) {
11946 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
11998 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
12034 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
12035 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
12067 if (CC == AArch64CC::EQ)
13282 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
13287 X, XC, CC, Y, OldShiftOpcode, NewShiftOpcode, DAG))