Searched refs:reg_name (Results 226 - 250 of 294) sorted by path

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/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c38 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.c42 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn301/
H A Ddcn301_optc.c42 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c40 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c42 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.c42 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c44 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c135 #define SR(reg_name)\
136 .reg_name = mm ## reg_name
139 #define SRI(reg_name, block, id)\
140 .reg_name = mm ## block ## id ## _ ## reg_name
491 #define SRII(reg_name, block, id)\
492 .reg_name[id] = mm ## block ## id ## _ ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c144 #define SR(reg_name)\
145 .reg_name = mm ## reg_name
148 #define SRI(reg_name, block, id)\
149 .reg_name = mm ## block ## id ## _ ## reg_name
540 #define SRII(reg_name, block, id)\
541 .reg_name[id] = mm ## block ## id ## _ ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c145 #define SR(reg_name)\
146 .reg_name = mm ## reg_name
149 #define SRI(reg_name, block, id)\
150 .reg_name = mm ## block ## id ## _ ## reg_name
521 #define SRII(reg_name, block, id)\
522 .reg_name[id] = mm ## block ## id ## _ ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c136 #define SR(reg_name)\
137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
138 mm ## reg_name
140 #define SRI(reg_name, block, id)\
141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 mm ## block ## id ## _ ## reg_name
151 #define MMHUB_SR(reg_name)\
152 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c151 #define SR(reg_name)\
152 .reg_name = mm ## reg_name
155 #define SRI(reg_name, block, id)\
156 .reg_name = mm ## block ## id ## _ ## reg_name
613 #define SRII(reg_name, block, id)\
614 .reg_name[id] = mm ## block ## id ## _ ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c111 #define SR(reg_name)\
112 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
113 mm ## reg_name
115 #define SRI(reg_name, block, id)\
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 mm ## block ## id ## _ ## reg_name
120 #define SRII(reg_name, block, id)\
121 .reg_name[i
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c128 #define SR(reg_name)\
129 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
130 mm ## reg_name
132 #define SRI(reg_name, block, id)\
133 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 mm ## block ## id ## _ ## reg_name
136 #define SRI2_DWB(reg_name, block, id)\
137 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c251 #define SR(reg_name)\
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
255 #define SRI(reg_name, block, id)\
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_ID
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c101 #define SR(reg_name)\
102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
103 mm ## reg_name
105 #define SRI(reg_name, block, id)\
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
109 #define SRIR(var_name, reg_name, block, id)\
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_ID
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c117 #define SR(reg_name)\
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
119 mm ## reg_name
121 #define SRI(reg_name, block, id)\
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 mm ## block ## id ## _ ## reg_name
125 #define SRI2(reg_name, block, id)\
126 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c116 #define SR(reg_name)\
117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
118 mm ## reg_name
120 #define SRI(reg_name, block, id)\
121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 mm ## block ## id ## _ ## reg_name
124 #define SRI2(reg_name, block, id)\
125 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c167 #define NBIO_SR(reg_name)\
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
169 mm ## reg_name
176 #define SR(reg_name)\
177 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
179 #define SF(reg_name, field_name, post_fix)\
180 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c163 #define NBIO_SR(reg_name)\
164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
165 mm ## reg_name
172 #define SR(reg_name)\
173 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
175 #define SF(reg_name, field_name, post_fix)\
176 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c128 #define SR(reg_name)\
129 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
130 reg ## reg_name
132 #define SRI(reg_name, block, id)\
133 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
136 #define SRI2(reg_name, block, id)\
137 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c145 #define SR(reg_name)\
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 reg ## reg_name
149 #define SRI(reg_name, block, id)\
150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
153 #define SRI2(reg_name, block, id)\
154 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c161 #define SR(reg_name)\
162 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
163 reg ## reg_name
165 #define SRI(reg_name, block, id)\
166 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
169 #define SRI2(reg_name, block, id)\
170 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c148 #define SR(reg_name)\
149 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 reg ## reg_name
152 #define SRI(reg_name, block, id)\
153 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
156 #define SRI2(reg_name, block, id)\
157 .reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c116 #define SR(reg_name)\
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
119 #define SR_ARR(reg_name, id) \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 #define SR_ARR_INIT(reg_name, id, value) \
123 REG_STRUCT[id].reg_name
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Completed in 345 milliseconds

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