Searched refs:wl (Results 151 - 175 of 184) sorted by relevance

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/linux-master/drivers/video/fbdev/matrox/
H A Dmatroxfb_g450.c133 int *wl)
139 *wl = min(b + c, WLMAX);
132 g450_compute_bwlevel(const struct matrox_fb_info *minfo, int *bl, int *wl) argument
/linux-master/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dchannel.c609 brcms_err(wlc->hw->d11core, "wl%d: malformed chanspec 0x%x\n",
697 struct brcms_info *wl = hw->priv; local
698 struct brcms_c_info *wlc = wl->wlc;
728 "wl%d: %s: no valid channel for \"%s\"\n",
H A Dmain.h385 * wl: pointer to specific private state.
457 struct brcms_info *wl; member in struct:brcms_c_info
/linux-master/drivers/net/wireless/realtek/rtw88/
H A Dcoex.h308 u32 wl; member in struct:coex_table_para
H A Dcoex.c717 /* update wl/bt rssi by btinfo */
994 table_wl = chip->table_sant[table_case].wl;
997 table_wl = chip->table_nsant[table_case].wl;
1050 /* If last tdma is wl slot toggle, force write table*/
1081 chip->table_sant[type].wl);
1087 chip->table_nsant[type].wl);
1310 /* set path control owner to wl at initial step */
1325 /* set path control owner to wl at initial step */
1349 /* set path control owner to wl at runtime step */
1365 /* set path control owner to wl a
[all...]
/linux-master/lib/crypto/mpi/
H A Dlonglong.h320 #define umul_ppmm(wh, wl, u, v) \
330 (wl) = __xx.__i.__l; \
613 #define umul_ppmm(wh, wl, u, v) \
620 (wl) = __x.__i.__l; \
/linux-master/drivers/net/wireless/microchip/wilc1000/
H A Dspi.c852 static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr) argument
854 struct spi_device *spi = to_spi_device(wl->dev);
855 struct wilc_spi *spi_priv = wl->bus_data;
861 wilc_spi_reset(wl);
H A Dwlan.h425 int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
/linux-master/sound/soc/codecs/
H A Dwm2200.c1693 int i, bclk, lrclk, wl, fl, sr_code; local
1697 wl = params_width(params);
1698 if (wl < 0)
1699 return wl;
1705 wl, fl);
1760 i = (wl << WM2200_AIF1TX_WL_SHIFT) | wl;
H A Dwm5100.c1405 int i, base, bclk, aif_rate, lrclk, wl, fl, sr; local
1411 wl = params_width(params);
1412 if (wl < 0)
1413 return wl;
1419 wl, fl);
1489 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
H A Darizona.c1789 int bclk, lrclk, wl, frame, bclk_target; local
1798 wl = params_width(params);
1807 tdm_width = wl;
1843 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | tdm_width;
H A Dmadera.c3114 int bclk, lrclk, wl, frame, bclk_target, num_rates; local
3126 wl = snd_pcm_format_width(params_format(params));
3135 tdm_width = wl;
3170 frame = wl << MADERA_AIF1TX_WL_SHIFT | tdm_width;
/linux-master/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1831 int wl, ch, rate; local
1862 wl = AUDIO_W_LEN_16_20MAX;
1865 wl = AUDIO_W_LEN_18_20MAX;
1868 wl = AUDIO_W_LEN_20_20MAX;
1871 wl = AUDIO_W_LEN_24_24MAX;
1880 0xf0, wl);
/linux-master/drivers/net/wireless/broadcom/b43/
H A Dtables_phy_lcn.c638 /* brcmsmac doesn't maskset, we follow newer wl here */
664 /* Not implemented in brcmsmac, noticed in wl in MMIO dump */
691 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
696 b43err(dev->wl,
706 b43err(dev->wl, "SW ctl table is unknown for this card\n");
H A Dphy_g.c228 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
1959 b43dbg(dev->wl,
2363 b43err(dev->wl, "Could not allocate memory "
2370 b43err(dev->wl, "Could not generate "
2867 b43dbg(dev->wl, "Adjusting TX power\n");
2921 b43warn(dev->wl,
2935 b43dbg(dev->wl,
2965 b43dbg(dev->wl,
H A Dtables_nphy.c3492 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
3509 b43err(dev->wl, "Unsupported antswlut: %d\n", antswlut);
3556 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
3641 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
3666 b43err(dev->wl,
3679 b43err(dev->wl,
3688 enum nl80211_band band = b43_current_band(dev->wl);
3698 } else if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) {
3710 b43err(dev->wl,
3725 b43err(dev->wl,
[all...]
H A Dtables_lpphy.c550 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
569 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) {
2369 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
2374 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
2413 else if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
2425 else if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
2436 else if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)
/linux-master/drivers/net/wireless/realtek/rtw89/
H A Dmac.h1229 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1230 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1231 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl);
H A Dfw.c4030 struct rtw89_btc_wl_info *wl = &btc->cx.wl; local
4031 struct rtw89_btc_wl_role_info *role_info = &wl->role_info;
4111 struct rtw89_btc_wl_info *wl = &btc->cx.wl; local
4112 struct rtw89_btc_wl_role_info_v1 *role_info = &wl->role_info_v1;
4201 struct rtw89_btc_wl_info *wl = &btc->cx.wl; local
4202 struct rtw89_btc_wl_role_info_v2 *role_info = &wl->role_info_v2;
4283 struct rtw89_btc_wl_role_info_v8 *role = &btc->cx.wl
4466 struct rtw89_btc_wl_info *wl = &btc->cx.wl; local
[all...]
H A Dmac_be.c1857 int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl) argument
1865 if (wl)
/linux-master/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_dfs.c8 #define RADAR_SPEC(m, len, el, eh, wl, wh, \
16 .w_low = wl, \
/linux-master/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_cmd.h122 struct hclge_waterline wl; /* Waterline for low and high */ member in struct:hclge_priv_buf
H A Dhclge_main.c2108 priv->wl.low = 0;
2109 priv->wl.high = 0;
2118 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT;
2119 priv->wl.high = roundup(priv->wl.low + aligned_mps,
2122 priv->wl.low = 0;
2123 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) :
2127 priv->buf_size = priv->wl.high + hdev->dv_buf_size;
2148 priv->wl.low = 0;
2149 priv->wl
[all...]
/linux-master/sound/soc/fsl/
H A Dfsl_ssi.c814 u32 wl = SSI_SxCCR_WL(sample_size); local
863 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl);
/linux-master/sound/pci/
H A Dintel8x0.c2769 const struct snd_pci_quirk *wl; local
2771 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
2772 if (!wl)
2775 pci->subsystem_vendor, pci->subsystem_device, wl->value);
2776 chip->ac97_bus->clock = wl->value;

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