1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7#include <linux/clk.h> 8#include <linux/spi/spi.h> 9#include <linux/crc7.h> 10#include <linux/crc-itu-t.h> 11#include <linux/gpio/consumer.h> 12 13#include "netdev.h" 14#include "cfg80211.h" 15 16#define SPI_MODALIAS "wilc1000_spi" 17 18static bool enable_crc7; /* protect SPI commands with CRC7 */ 19module_param(enable_crc7, bool, 0644); 20MODULE_PARM_DESC(enable_crc7, 21 "Enable CRC7 checksum to protect command transfers\n" 22 "\t\t\tagainst corruption during the SPI transfer.\n" 23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n" 24 "\t\t\tof enabling this is small."); 25 26static bool enable_crc16; /* protect SPI data with CRC16 */ 27module_param(enable_crc16, bool, 0644); 28MODULE_PARM_DESC(enable_crc16, 29 "Enable CRC16 checksum to protect data transfers\n" 30 "\t\t\tagainst corruption during the SPI transfer.\n" 31 "\t\t\tData transfers can be large and the CPU-cycle cost\n" 32 "\t\t\tof enabling this may be substantial."); 33 34/* 35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or 36 * more zero bytes between the command response and the DATA Start tag 37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000 38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4 39 * zero bytes when the SPI bus operates at 48MHz and none when it 40 * operates at 1MHz. 41 */ 42#define WILC_SPI_RSP_HDR_EXTRA_DATA 8 43 44struct wilc_spi { 45 bool isinit; /* true if wilc_spi_init was successful */ 46 bool probing_crc; /* true if we're probing chip's CRC config */ 47 bool crc7_enabled; /* true if crc7 is currently enabled */ 48 bool crc16_enabled; /* true if crc16 is currently enabled */ 49 struct wilc_gpios { 50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */ 51 struct gpio_desc *reset; /* RESET GPIO or NULL */ 52 } gpios; 53}; 54 55static const struct wilc_hif_func wilc_hif_spi; 56 57static int wilc_spi_reset(struct wilc *wilc); 58static int wilc_spi_configure_bus_protocol(struct wilc *wilc); 59static int wilc_validate_chipid(struct wilc *wilc); 60 61/******************************************** 62 * 63 * Spi protocol Function 64 * 65 ********************************************/ 66 67#define CMD_DMA_WRITE 0xc1 68#define CMD_DMA_READ 0xc2 69#define CMD_INTERNAL_WRITE 0xc3 70#define CMD_INTERNAL_READ 0xc4 71#define CMD_TERMINATE 0xc5 72#define CMD_REPEAT 0xc6 73#define CMD_DMA_EXT_WRITE 0xc7 74#define CMD_DMA_EXT_READ 0xc8 75#define CMD_SINGLE_WRITE 0xc9 76#define CMD_SINGLE_READ 0xca 77#define CMD_RESET 0xcf 78 79#define SPI_RETRY_MAX_LIMIT 10 80#define SPI_ENABLE_VMM_RETRY_LIMIT 2 81 82/* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */ 83#define RSP_START_FIELD GENMASK(7, 4) 84#define RSP_TYPE_FIELD GENMASK(3, 0) 85 86/* SPI response values for the response fields: */ 87#define RSP_START_TAG 0xc 88#define RSP_TYPE_FIRST_PACKET 0x1 89#define RSP_TYPE_INNER_PACKET 0x2 90#define RSP_TYPE_LAST_PACKET 0x3 91#define RSP_STATE_NO_ERROR 0x00 92 93#define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4) 94#define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3) 95#define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2) 96 97/* 98 * The SPI data packet size may be any integer power of two in the 99 * range from 256 to 8192 bytes. 100 */ 101#define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */ 102#define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */ 103 104/* 105 * Select the data packet size (log2 of number of bytes): Use the 106 * maximum data packet size. We only retransmit complete packets, so 107 * there is no benefit from using smaller data packets. 108 */ 109#define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX 110#define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ) 111 112#define WILC_SPI_COMMAND_STAT_SUCCESS 0 113#define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf) 114 115struct wilc_spi_cmd { 116 u8 cmd_type; 117 union { 118 struct { 119 u8 addr[3]; 120 u8 crc[]; 121 } __packed simple_cmd; 122 struct { 123 u8 addr[3]; 124 u8 size[2]; 125 u8 crc[]; 126 } __packed dma_cmd; 127 struct { 128 u8 addr[3]; 129 u8 size[3]; 130 u8 crc[]; 131 } __packed dma_cmd_ext; 132 struct { 133 u8 addr[2]; 134 __be32 data; 135 u8 crc[]; 136 } __packed internal_w_cmd; 137 struct { 138 u8 addr[3]; 139 __be32 data; 140 u8 crc[]; 141 } __packed w_cmd; 142 } u; 143} __packed; 144 145struct wilc_spi_read_rsp_data { 146 u8 header; 147 u8 data[4]; 148 u8 crc[]; 149} __packed; 150 151struct wilc_spi_rsp_data { 152 u8 rsp_cmd_type; 153 u8 status; 154 u8 data[]; 155} __packed; 156 157struct wilc_spi_special_cmd_rsp { 158 u8 skip_byte; 159 u8 rsp_cmd_type; 160 u8 status; 161} __packed; 162 163static int wilc_parse_gpios(struct wilc *wilc) 164{ 165 struct spi_device *spi = to_spi_device(wilc->dev); 166 struct wilc_spi *spi_priv = wilc->bus_data; 167 struct wilc_gpios *gpios = &spi_priv->gpios; 168 169 /* get ENABLE pin and deassert it (if it is defined): */ 170 gpios->enable = devm_gpiod_get_optional(&spi->dev, 171 "enable", GPIOD_OUT_LOW); 172 /* get RESET pin and assert it (if it is defined): */ 173 if (gpios->enable) { 174 /* if enable pin exists, reset must exist as well */ 175 gpios->reset = devm_gpiod_get(&spi->dev, 176 "reset", GPIOD_OUT_HIGH); 177 if (IS_ERR(gpios->reset)) { 178 dev_err(&spi->dev, "missing reset gpio.\n"); 179 return PTR_ERR(gpios->reset); 180 } 181 } else { 182 gpios->reset = devm_gpiod_get_optional(&spi->dev, 183 "reset", GPIOD_OUT_HIGH); 184 } 185 return 0; 186} 187 188static void wilc_wlan_power(struct wilc *wilc, bool on) 189{ 190 struct wilc_spi *spi_priv = wilc->bus_data; 191 struct wilc_gpios *gpios = &spi_priv->gpios; 192 193 if (on) { 194 /* assert ENABLE: */ 195 gpiod_set_value(gpios->enable, 1); 196 mdelay(5); 197 /* deassert RESET: */ 198 gpiod_set_value(gpios->reset, 0); 199 } else { 200 /* assert RESET: */ 201 gpiod_set_value(gpios->reset, 1); 202 /* deassert ENABLE: */ 203 gpiod_set_value(gpios->enable, 0); 204 } 205} 206 207static int wilc_bus_probe(struct spi_device *spi) 208{ 209 int ret; 210 struct wilc *wilc; 211 struct wilc_spi *spi_priv; 212 213 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL); 214 if (!spi_priv) 215 return -ENOMEM; 216 217 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); 218 if (ret) 219 goto free; 220 221 spi_set_drvdata(spi, wilc); 222 wilc->dev = &spi->dev; 223 wilc->bus_data = spi_priv; 224 wilc->dev_irq_num = spi->irq; 225 226 ret = wilc_parse_gpios(wilc); 227 if (ret < 0) 228 goto netdev_cleanup; 229 230 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc"); 231 if (IS_ERR(wilc->rtc_clk)) { 232 ret = PTR_ERR(wilc->rtc_clk); 233 goto netdev_cleanup; 234 } 235 clk_prepare_enable(wilc->rtc_clk); 236 237 dev_info(&spi->dev, "Selected CRC config: crc7=%s, crc16=%s\n", 238 enable_crc7 ? "on" : "off", enable_crc16 ? "on" : "off"); 239 240 /* we need power to configure the bus protocol and to read the chip id: */ 241 242 wilc_wlan_power(wilc, true); 243 244 ret = wilc_spi_configure_bus_protocol(wilc); 245 if (ret) 246 goto power_down; 247 248 ret = wilc_validate_chipid(wilc); 249 if (ret) 250 goto power_down; 251 252 wilc_wlan_power(wilc, false); 253 return 0; 254 255power_down: 256 clk_disable_unprepare(wilc->rtc_clk); 257 wilc_wlan_power(wilc, false); 258netdev_cleanup: 259 wilc_netdev_cleanup(wilc); 260free: 261 kfree(spi_priv); 262 return ret; 263} 264 265static void wilc_bus_remove(struct spi_device *spi) 266{ 267 struct wilc *wilc = spi_get_drvdata(spi); 268 struct wilc_spi *spi_priv = wilc->bus_data; 269 270 clk_disable_unprepare(wilc->rtc_clk); 271 wilc_netdev_cleanup(wilc); 272 kfree(spi_priv); 273} 274 275static const struct of_device_id wilc_of_match[] = { 276 { .compatible = "microchip,wilc1000", }, 277 { /* sentinel */ } 278}; 279MODULE_DEVICE_TABLE(of, wilc_of_match); 280 281static const struct spi_device_id wilc_spi_id[] = { 282 { "wilc1000", 0 }, 283 { /* sentinel */ } 284}; 285MODULE_DEVICE_TABLE(spi, wilc_spi_id); 286 287static struct spi_driver wilc_spi_driver = { 288 .driver = { 289 .name = SPI_MODALIAS, 290 .of_match_table = wilc_of_match, 291 }, 292 .id_table = wilc_spi_id, 293 .probe = wilc_bus_probe, 294 .remove = wilc_bus_remove, 295}; 296module_spi_driver(wilc_spi_driver); 297MODULE_DESCRIPTION("Atmel WILC1000 SPI wireless driver"); 298MODULE_LICENSE("GPL"); 299 300static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len) 301{ 302 struct spi_device *spi = to_spi_device(wilc->dev); 303 int ret; 304 struct spi_message msg; 305 306 if (len > 0 && b) { 307 struct spi_transfer tr = { 308 .tx_buf = b, 309 .len = len, 310 .delay = { 311 .value = 0, 312 .unit = SPI_DELAY_UNIT_USECS 313 }, 314 }; 315 char *r_buffer = kzalloc(len, GFP_KERNEL); 316 317 if (!r_buffer) 318 return -ENOMEM; 319 320 tr.rx_buf = r_buffer; 321 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); 322 323 memset(&msg, 0, sizeof(msg)); 324 spi_message_init(&msg); 325 spi_message_add_tail(&tr, &msg); 326 327 ret = spi_sync(spi, &msg); 328 if (ret < 0) 329 dev_err(&spi->dev, "SPI transaction failed\n"); 330 331 kfree(r_buffer); 332 } else { 333 dev_err(&spi->dev, 334 "can't write data with the following length: %d\n", 335 len); 336 ret = -EINVAL; 337 } 338 339 return ret; 340} 341 342static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen) 343{ 344 struct spi_device *spi = to_spi_device(wilc->dev); 345 int ret; 346 347 if (rlen > 0) { 348 struct spi_message msg; 349 struct spi_transfer tr = { 350 .rx_buf = rb, 351 .len = rlen, 352 .delay = { 353 .value = 0, 354 .unit = SPI_DELAY_UNIT_USECS 355 }, 356 357 }; 358 char *t_buffer = kzalloc(rlen, GFP_KERNEL); 359 360 if (!t_buffer) 361 return -ENOMEM; 362 363 tr.tx_buf = t_buffer; 364 365 memset(&msg, 0, sizeof(msg)); 366 spi_message_init(&msg); 367 spi_message_add_tail(&tr, &msg); 368 369 ret = spi_sync(spi, &msg); 370 if (ret < 0) 371 dev_err(&spi->dev, "SPI transaction failed\n"); 372 kfree(t_buffer); 373 } else { 374 dev_err(&spi->dev, 375 "can't read data with the following length: %u\n", 376 rlen); 377 ret = -EINVAL; 378 } 379 380 return ret; 381} 382 383static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen) 384{ 385 struct spi_device *spi = to_spi_device(wilc->dev); 386 int ret; 387 388 if (rlen > 0) { 389 struct spi_message msg; 390 struct spi_transfer tr = { 391 .rx_buf = rb, 392 .tx_buf = wb, 393 .len = rlen, 394 .bits_per_word = 8, 395 .delay = { 396 .value = 0, 397 .unit = SPI_DELAY_UNIT_USECS 398 }, 399 400 }; 401 402 memset(&msg, 0, sizeof(msg)); 403 spi_message_init(&msg); 404 spi_message_add_tail(&tr, &msg); 405 ret = spi_sync(spi, &msg); 406 if (ret < 0) 407 dev_err(&spi->dev, "SPI transaction failed\n"); 408 } else { 409 dev_err(&spi->dev, 410 "can't read data with the following length: %u\n", 411 rlen); 412 ret = -EINVAL; 413 } 414 415 return ret; 416} 417 418static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz) 419{ 420 struct spi_device *spi = to_spi_device(wilc->dev); 421 struct wilc_spi *spi_priv = wilc->bus_data; 422 int ix, nbytes; 423 int result = 0; 424 u8 cmd, order, crc[2]; 425 u16 crc_calc; 426 427 /* 428 * Data 429 */ 430 ix = 0; 431 do { 432 if (sz <= DATA_PKT_SZ) { 433 nbytes = sz; 434 order = 0x3; 435 } else { 436 nbytes = DATA_PKT_SZ; 437 if (ix == 0) 438 order = 0x1; 439 else 440 order = 0x02; 441 } 442 443 /* 444 * Write command 445 */ 446 cmd = 0xf0; 447 cmd |= order; 448 449 if (wilc_spi_tx(wilc, &cmd, 1)) { 450 dev_err(&spi->dev, 451 "Failed data block cmd write, bus error...\n"); 452 result = -EINVAL; 453 break; 454 } 455 456 /* 457 * Write data 458 */ 459 if (wilc_spi_tx(wilc, &b[ix], nbytes)) { 460 dev_err(&spi->dev, 461 "Failed data block write, bus error...\n"); 462 result = -EINVAL; 463 break; 464 } 465 466 /* 467 * Write CRC 468 */ 469 if (spi_priv->crc16_enabled) { 470 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 471 crc[0] = crc_calc >> 8; 472 crc[1] = crc_calc; 473 if (wilc_spi_tx(wilc, crc, 2)) { 474 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); 475 result = -EINVAL; 476 break; 477 } 478 } 479 480 /* 481 * No need to wait for response 482 */ 483 ix += nbytes; 484 sz -= nbytes; 485 } while (sz); 486 487 return result; 488} 489 490/******************************************** 491 * 492 * Spi Internal Read/Write Function 493 * 494 ********************************************/ 495static u8 wilc_get_crc7(u8 *buffer, u32 len) 496{ 497 return crc7_be(0xfe, buffer, len) | 0x01; 498} 499 500static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, 501 u8 clockless) 502{ 503 struct spi_device *spi = to_spi_device(wilc->dev); 504 struct wilc_spi *spi_priv = wilc->bus_data; 505 u8 wb[32], rb[32]; 506 int cmd_len, resp_len, i; 507 u16 crc_calc, crc_recv; 508 struct wilc_spi_cmd *c; 509 struct wilc_spi_rsp_data *r; 510 struct wilc_spi_read_rsp_data *r_data; 511 512 memset(wb, 0x0, sizeof(wb)); 513 memset(rb, 0x0, sizeof(rb)); 514 c = (struct wilc_spi_cmd *)wb; 515 c->cmd_type = cmd; 516 if (cmd == CMD_SINGLE_READ) { 517 c->u.simple_cmd.addr[0] = adr >> 16; 518 c->u.simple_cmd.addr[1] = adr >> 8; 519 c->u.simple_cmd.addr[2] = adr; 520 } else if (cmd == CMD_INTERNAL_READ) { 521 c->u.simple_cmd.addr[0] = adr >> 8; 522 if (clockless == 1) 523 c->u.simple_cmd.addr[0] |= BIT(7); 524 c->u.simple_cmd.addr[1] = adr; 525 c->u.simple_cmd.addr[2] = 0x0; 526 } else { 527 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); 528 return -EINVAL; 529 } 530 531 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 532 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA; 533 534 if (spi_priv->crc7_enabled) { 535 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 536 cmd_len += 1; 537 resp_len += 2; 538 } 539 540 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 541 dev_err(&spi->dev, 542 "spi buffer size too small (%d) (%d) (%zu)\n", 543 cmd_len, resp_len, ARRAY_SIZE(wb)); 544 return -EINVAL; 545 } 546 547 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 548 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 549 return -EINVAL; 550 } 551 552 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 553 if (r->rsp_cmd_type != cmd && !clockless) { 554 if (!spi_priv->probing_crc) 555 dev_err(&spi->dev, 556 "Failed cmd, cmd (%02x), resp (%02x)\n", 557 cmd, r->rsp_cmd_type); 558 return -EINVAL; 559 } 560 561 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 562 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 563 r->status); 564 return -EINVAL; 565 } 566 567 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i) 568 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) 569 break; 570 571 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) { 572 dev_err(&spi->dev, "Error, data start missing\n"); 573 return -EINVAL; 574 } 575 576 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; 577 578 if (b) 579 memcpy(b, r_data->data, 4); 580 581 if (!clockless && spi_priv->crc16_enabled) { 582 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; 583 crc_calc = crc_itu_t(0xffff, r_data->data, 4); 584 if (crc_recv != crc_calc) { 585 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 586 "(calculated 0x%04x)\n", __func__, 587 crc_recv, crc_calc); 588 return -EINVAL; 589 } 590 } 591 592 return 0; 593} 594 595static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, 596 u8 clockless) 597{ 598 struct spi_device *spi = to_spi_device(wilc->dev); 599 struct wilc_spi *spi_priv = wilc->bus_data; 600 u8 wb[32], rb[32]; 601 int cmd_len, resp_len; 602 struct wilc_spi_cmd *c; 603 struct wilc_spi_rsp_data *r; 604 605 memset(wb, 0x0, sizeof(wb)); 606 memset(rb, 0x0, sizeof(rb)); 607 c = (struct wilc_spi_cmd *)wb; 608 c->cmd_type = cmd; 609 if (cmd == CMD_INTERNAL_WRITE) { 610 c->u.internal_w_cmd.addr[0] = adr >> 8; 611 if (clockless == 1) 612 c->u.internal_w_cmd.addr[0] |= BIT(7); 613 614 c->u.internal_w_cmd.addr[1] = adr; 615 c->u.internal_w_cmd.data = cpu_to_be32(data); 616 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc); 617 if (spi_priv->crc7_enabled) 618 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 619 } else if (cmd == CMD_SINGLE_WRITE) { 620 c->u.w_cmd.addr[0] = adr >> 16; 621 c->u.w_cmd.addr[1] = adr >> 8; 622 c->u.w_cmd.addr[2] = adr; 623 c->u.w_cmd.data = cpu_to_be32(data); 624 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc); 625 if (spi_priv->crc7_enabled) 626 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 627 } else { 628 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); 629 return -EINVAL; 630 } 631 632 if (spi_priv->crc7_enabled) 633 cmd_len += 1; 634 635 resp_len = sizeof(*r); 636 637 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 638 dev_err(&spi->dev, 639 "spi buffer size too small (%d) (%d) (%zu)\n", 640 cmd_len, resp_len, ARRAY_SIZE(wb)); 641 return -EINVAL; 642 } 643 644 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 645 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 646 return -EINVAL; 647 } 648 649 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 650 /* 651 * Clockless registers operations might return unexptected responses, 652 * even if successful. 653 */ 654 if (r->rsp_cmd_type != cmd && !clockless) { 655 dev_err(&spi->dev, 656 "Failed cmd response, cmd (%02x), resp (%02x)\n", 657 cmd, r->rsp_cmd_type); 658 return -EINVAL; 659 } 660 661 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { 662 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 663 r->status); 664 return -EINVAL; 665 } 666 667 return 0; 668} 669 670static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) 671{ 672 struct spi_device *spi = to_spi_device(wilc->dev); 673 struct wilc_spi *spi_priv = wilc->bus_data; 674 u16 crc_recv, crc_calc; 675 u8 wb[32], rb[32]; 676 int cmd_len, resp_len; 677 int retry, ix = 0; 678 u8 crc[2]; 679 struct wilc_spi_cmd *c; 680 struct wilc_spi_rsp_data *r; 681 682 memset(wb, 0x0, sizeof(wb)); 683 memset(rb, 0x0, sizeof(rb)); 684 c = (struct wilc_spi_cmd *)wb; 685 c->cmd_type = cmd; 686 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { 687 c->u.dma_cmd.addr[0] = adr >> 16; 688 c->u.dma_cmd.addr[1] = adr >> 8; 689 c->u.dma_cmd.addr[2] = adr; 690 c->u.dma_cmd.size[0] = sz >> 8; 691 c->u.dma_cmd.size[1] = sz; 692 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc); 693 if (spi_priv->crc7_enabled) 694 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 695 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { 696 c->u.dma_cmd_ext.addr[0] = adr >> 16; 697 c->u.dma_cmd_ext.addr[1] = adr >> 8; 698 c->u.dma_cmd_ext.addr[2] = adr; 699 c->u.dma_cmd_ext.size[0] = sz >> 16; 700 c->u.dma_cmd_ext.size[1] = sz >> 8; 701 c->u.dma_cmd_ext.size[2] = sz; 702 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc); 703 if (spi_priv->crc7_enabled) 704 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); 705 } else { 706 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", 707 cmd); 708 return -EINVAL; 709 } 710 if (spi_priv->crc7_enabled) 711 cmd_len += 1; 712 713 resp_len = sizeof(*r); 714 715 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 716 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", 717 cmd_len, resp_len, ARRAY_SIZE(wb)); 718 return -EINVAL; 719 } 720 721 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 722 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 723 return -EINVAL; 724 } 725 726 r = (struct wilc_spi_rsp_data *)&rb[cmd_len]; 727 if (r->rsp_cmd_type != cmd) { 728 dev_err(&spi->dev, 729 "Failed cmd response, cmd (%02x), resp (%02x)\n", 730 cmd, r->rsp_cmd_type); 731 return -EINVAL; 732 } 733 734 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 735 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 736 r->status); 737 return -EINVAL; 738 } 739 740 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) 741 return 0; 742 743 while (sz > 0) { 744 int nbytes; 745 u8 rsp; 746 747 nbytes = min_t(u32, sz, DATA_PKT_SZ); 748 749 /* 750 * Data Response header 751 */ 752 retry = 100; 753 do { 754 if (wilc_spi_rx(wilc, &rsp, 1)) { 755 dev_err(&spi->dev, 756 "Failed resp read, bus err\n"); 757 return -EINVAL; 758 } 759 if (WILC_GET_RESP_HDR_START(rsp) == 0xf) 760 break; 761 } while (retry--); 762 763 /* 764 * Read bytes 765 */ 766 if (wilc_spi_rx(wilc, &b[ix], nbytes)) { 767 dev_err(&spi->dev, 768 "Failed block read, bus err\n"); 769 return -EINVAL; 770 } 771 772 /* 773 * Read CRC 774 */ 775 if (spi_priv->crc16_enabled) { 776 if (wilc_spi_rx(wilc, crc, 2)) { 777 dev_err(&spi->dev, 778 "Failed block CRC read, bus err\n"); 779 return -EINVAL; 780 } 781 crc_recv = (crc[0] << 8) | crc[1]; 782 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes); 783 if (crc_recv != crc_calc) { 784 dev_err(&spi->dev, "%s: bad CRC 0x%04x " 785 "(calculated 0x%04x)\n", __func__, 786 crc_recv, crc_calc); 787 return -EINVAL; 788 } 789 } 790 791 ix += nbytes; 792 sz -= nbytes; 793 } 794 return 0; 795} 796 797static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) 798{ 799 struct spi_device *spi = to_spi_device(wilc->dev); 800 struct wilc_spi *spi_priv = wilc->bus_data; 801 u8 wb[32], rb[32]; 802 int cmd_len, resp_len = 0; 803 struct wilc_spi_cmd *c; 804 struct wilc_spi_special_cmd_rsp *r; 805 806 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) 807 return -EINVAL; 808 809 memset(wb, 0x0, sizeof(wb)); 810 memset(rb, 0x0, sizeof(rb)); 811 c = (struct wilc_spi_cmd *)wb; 812 c->cmd_type = cmd; 813 814 if (cmd == CMD_RESET) 815 memset(c->u.simple_cmd.addr, 0xFF, 3); 816 817 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc); 818 resp_len = sizeof(*r); 819 820 if (spi_priv->crc7_enabled) { 821 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); 822 cmd_len += 1; 823 } 824 if (cmd_len + resp_len > ARRAY_SIZE(wb)) { 825 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", 826 cmd_len, resp_len, ARRAY_SIZE(wb)); 827 return -EINVAL; 828 } 829 830 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) { 831 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); 832 return -EINVAL; 833 } 834 835 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len]; 836 if (r->rsp_cmd_type != cmd) { 837 if (!spi_priv->probing_crc) 838 dev_err(&spi->dev, 839 "Failed cmd response, cmd (%02x), resp (%02x)\n", 840 cmd, r->rsp_cmd_type); 841 return -EINVAL; 842 } 843 844 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { 845 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", 846 r->status); 847 return -EINVAL; 848 } 849 return 0; 850} 851 852static void wilc_spi_reset_cmd_sequence(struct wilc *wl, u8 attempt, u32 addr) 853{ 854 struct spi_device *spi = to_spi_device(wl->dev); 855 struct wilc_spi *spi_priv = wl->bus_data; 856 857 if (!spi_priv->probing_crc) 858 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); 859 860 usleep_range(1000, 1100); 861 wilc_spi_reset(wl); 862 usleep_range(1000, 1100); 863} 864 865static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) 866{ 867 struct spi_device *spi = to_spi_device(wilc->dev); 868 int result; 869 u8 cmd = CMD_SINGLE_READ; 870 u8 clockless = 0; 871 u8 i; 872 873 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 874 /* Clockless register */ 875 cmd = CMD_INTERNAL_READ; 876 clockless = 1; 877 } 878 879 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 880 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); 881 if (!result) { 882 le32_to_cpus(data); 883 return 0; 884 } 885 886 /* retry is not applicable for clockless registers */ 887 if (clockless) 888 break; 889 890 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); 891 wilc_spi_reset_cmd_sequence(wilc, i, addr); 892 } 893 894 return result; 895} 896 897static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 898{ 899 struct spi_device *spi = to_spi_device(wilc->dev); 900 int result; 901 u8 i; 902 903 if (size <= 4) 904 return -EINVAL; 905 906 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 907 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, 908 buf, size); 909 if (!result) 910 return 0; 911 912 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); 913 914 wilc_spi_reset_cmd_sequence(wilc, i, addr); 915 } 916 917 return result; 918} 919 920static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) 921{ 922 struct spi_device *spi = to_spi_device(wilc->dev); 923 int result; 924 u8 i; 925 926 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 927 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, 928 dat, 0); 929 if (!result) 930 return 0; 931 dev_err(&spi->dev, "Failed internal write cmd...\n"); 932 933 wilc_spi_reset_cmd_sequence(wilc, i, adr); 934 } 935 936 return result; 937} 938 939static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data) 940{ 941 struct spi_device *spi = to_spi_device(wilc->dev); 942 struct wilc_spi *spi_priv = wilc->bus_data; 943 int result; 944 u8 i; 945 946 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 947 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, 948 data, 0); 949 if (!result) { 950 le32_to_cpus(data); 951 return 0; 952 } 953 if (!spi_priv->probing_crc) 954 dev_err(&spi->dev, "Failed internal read cmd...\n"); 955 956 wilc_spi_reset_cmd_sequence(wilc, i, adr); 957 } 958 959 return result; 960} 961 962/******************************************** 963 * 964 * Spi interfaces 965 * 966 ********************************************/ 967 968static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) 969{ 970 struct spi_device *spi = to_spi_device(wilc->dev); 971 int result; 972 u8 cmd = CMD_SINGLE_WRITE; 973 u8 clockless = 0; 974 u8 i; 975 976 if (addr <= WILC_SPI_CLOCKLESS_ADDR_LIMIT) { 977 /* Clockless register */ 978 cmd = CMD_INTERNAL_WRITE; 979 clockless = 1; 980 } 981 982 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 983 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); 984 if (!result) 985 return 0; 986 987 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); 988 989 if (clockless) 990 break; 991 992 wilc_spi_reset_cmd_sequence(wilc, i, addr); 993 } 994 return result; 995} 996 997static int spi_data_rsp(struct wilc *wilc, u8 cmd) 998{ 999 struct spi_device *spi = to_spi_device(wilc->dev); 1000 int result, i; 1001 u8 rsp[4]; 1002 1003 /* 1004 * The response to data packets is two bytes long. For 1005 * efficiency's sake, wilc_spi_write() wisely ignores the 1006 * responses for all packets but the final one. The downside 1007 * of that optimization is that when the final data packet is 1008 * short, we may receive (part of) the response to the 1009 * second-to-last packet before the one for the final packet. 1010 * To handle this, we always read 4 bytes and then search for 1011 * the last byte that contains the "Response Start" code (0xc 1012 * in the top 4 bits). We then know that this byte is the 1013 * first response byte of the final data packet. 1014 */ 1015 result = wilc_spi_rx(wilc, rsp, sizeof(rsp)); 1016 if (result) { 1017 dev_err(&spi->dev, "Failed bus error...\n"); 1018 return result; 1019 } 1020 1021 for (i = sizeof(rsp) - 2; i >= 0; --i) 1022 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG) 1023 break; 1024 1025 if (i < 0) { 1026 dev_err(&spi->dev, 1027 "Data packet response missing (%02x %02x %02x %02x)\n", 1028 rsp[0], rsp[1], rsp[2], rsp[3]); 1029 return -1; 1030 } 1031 1032 /* rsp[i] is the last response start byte */ 1033 1034 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET 1035 || rsp[i + 1] != RSP_STATE_NO_ERROR) { 1036 dev_err(&spi->dev, "Data response error (%02x %02x)\n", 1037 rsp[i], rsp[i + 1]); 1038 return -1; 1039 } 1040 return 0; 1041} 1042 1043static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size) 1044{ 1045 struct spi_device *spi = to_spi_device(wilc->dev); 1046 int result; 1047 u8 i; 1048 1049 /* 1050 * has to be greated than 4 1051 */ 1052 if (size <= 4) 1053 return -EINVAL; 1054 1055 for (i = 0; i < SPI_RETRY_MAX_LIMIT; i++) { 1056 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, 1057 NULL, size); 1058 if (result) { 1059 dev_err(&spi->dev, 1060 "Failed cmd, write block (%08x)...\n", addr); 1061 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1062 continue; 1063 } 1064 1065 /* 1066 * Data 1067 */ 1068 result = spi_data_write(wilc, buf, size); 1069 if (result) { 1070 dev_err(&spi->dev, "Failed block data write...\n"); 1071 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1072 continue; 1073 } 1074 1075 /* 1076 * Data response 1077 */ 1078 result = spi_data_rsp(wilc, CMD_DMA_EXT_WRITE); 1079 if (result) { 1080 dev_err(&spi->dev, "Failed block data rsp...\n"); 1081 wilc_spi_reset_cmd_sequence(wilc, i, addr); 1082 continue; 1083 } 1084 break; 1085 } 1086 return result; 1087} 1088 1089/******************************************** 1090 * 1091 * Bus interfaces 1092 * 1093 ********************************************/ 1094 1095static int wilc_spi_reset(struct wilc *wilc) 1096{ 1097 struct spi_device *spi = to_spi_device(wilc->dev); 1098 struct wilc_spi *spi_priv = wilc->bus_data; 1099 int result; 1100 1101 result = wilc_spi_special_cmd(wilc, CMD_RESET); 1102 if (result && !spi_priv->probing_crc) 1103 dev_err(&spi->dev, "Failed cmd reset\n"); 1104 1105 return result; 1106} 1107 1108static bool wilc_spi_is_init(struct wilc *wilc) 1109{ 1110 struct wilc_spi *spi_priv = wilc->bus_data; 1111 1112 return spi_priv->isinit; 1113} 1114 1115static int wilc_spi_deinit(struct wilc *wilc) 1116{ 1117 struct wilc_spi *spi_priv = wilc->bus_data; 1118 1119 spi_priv->isinit = false; 1120 wilc_wlan_power(wilc, false); 1121 return 0; 1122} 1123 1124static int wilc_spi_init(struct wilc *wilc, bool resume) 1125{ 1126 struct wilc_spi *spi_priv = wilc->bus_data; 1127 int ret; 1128 1129 if (spi_priv->isinit) { 1130 /* Confirm we can read chipid register without error: */ 1131 if (wilc_validate_chipid(wilc) == 0) 1132 return 0; 1133 } 1134 1135 wilc_wlan_power(wilc, true); 1136 1137 ret = wilc_spi_configure_bus_protocol(wilc); 1138 if (ret) { 1139 wilc_wlan_power(wilc, false); 1140 return ret; 1141 } 1142 1143 spi_priv->isinit = true; 1144 1145 return 0; 1146} 1147 1148static int wilc_spi_configure_bus_protocol(struct wilc *wilc) 1149{ 1150 struct spi_device *spi = to_spi_device(wilc->dev); 1151 struct wilc_spi *spi_priv = wilc->bus_data; 1152 u32 reg; 1153 int ret, i; 1154 1155 /* 1156 * Infer the CRC settings that are currently in effect. This 1157 * is necessary because we can't be sure that the chip has 1158 * been RESET (e.g, after module unload and reload). 1159 */ 1160 spi_priv->probing_crc = true; 1161 spi_priv->crc7_enabled = enable_crc7; 1162 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ 1163 for (i = 0; i < 2; ++i) { 1164 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1165 if (ret == 0) 1166 break; 1167 spi_priv->crc7_enabled = !enable_crc7; 1168 } 1169 if (ret) { 1170 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); 1171 return ret; 1172 } 1173 1174 /* set up the desired CRC configuration: */ 1175 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK); 1176 if (enable_crc7) 1177 reg |= PROTOCOL_REG_CRC7_MASK; 1178 if (enable_crc16) 1179 reg |= PROTOCOL_REG_CRC16_MASK; 1180 1181 /* set up the data packet size: */ 1182 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN 1183 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX); 1184 reg &= ~PROTOCOL_REG_PKT_SZ_MASK; 1185 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK, 1186 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); 1187 1188 /* establish the new setup: */ 1189 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg); 1190 if (ret) { 1191 dev_err(&spi->dev, 1192 "[wilc spi %d]: Failed internal write reg\n", 1193 __LINE__); 1194 return ret; 1195 } 1196 /* update our state to match new protocol settings: */ 1197 spi_priv->crc7_enabled = enable_crc7; 1198 spi_priv->crc16_enabled = enable_crc16; 1199 1200 /* re-read to make sure new settings are in effect: */ 1201 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®); 1202 1203 spi_priv->probing_crc = false; 1204 1205 return 0; 1206} 1207 1208static int wilc_validate_chipid(struct wilc *wilc) 1209{ 1210 struct spi_device *spi = to_spi_device(wilc->dev); 1211 u32 chipid; 1212 int ret; 1213 1214 /* 1215 * make sure can read chip id without protocol error 1216 */ 1217 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); 1218 if (ret) { 1219 dev_err(&spi->dev, "Fail cmd read chip id...\n"); 1220 return ret; 1221 } 1222 if (!is_wilc1000(chipid)) { 1223 dev_err(&spi->dev, "Unknown chip id 0x%x\n", chipid); 1224 return -ENODEV; 1225 } 1226 return 0; 1227} 1228 1229static int wilc_spi_read_size(struct wilc *wilc, u32 *size) 1230{ 1231 int ret; 1232 1233 ret = spi_internal_read(wilc, 1234 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); 1235 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); 1236 1237 return ret; 1238} 1239 1240static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) 1241{ 1242 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, 1243 int_status); 1244} 1245 1246static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) 1247{ 1248 int ret; 1249 int retry = SPI_ENABLE_VMM_RETRY_LIMIT; 1250 u32 check; 1251 1252 while (retry) { 1253 ret = spi_internal_write(wilc, 1254 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1255 val); 1256 if (ret) 1257 break; 1258 1259 ret = spi_internal_read(wilc, 1260 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, 1261 &check); 1262 if (ret || ((check & EN_VMM) == (val & EN_VMM))) 1263 break; 1264 1265 retry--; 1266 } 1267 return ret; 1268} 1269 1270static int wilc_spi_sync_ext(struct wilc *wilc, int nint) 1271{ 1272 struct spi_device *spi = to_spi_device(wilc->dev); 1273 u32 reg; 1274 int ret, i; 1275 1276 if (nint > MAX_NUM_INT) { 1277 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); 1278 return -EINVAL; 1279 } 1280 1281 /* 1282 * interrupt pin mux select 1283 */ 1284 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®); 1285 if (ret) { 1286 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1287 WILC_PIN_MUX_0); 1288 return ret; 1289 } 1290 reg |= BIT(8); 1291 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg); 1292 if (ret) { 1293 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1294 WILC_PIN_MUX_0); 1295 return ret; 1296 } 1297 1298 /* 1299 * interrupt enable 1300 */ 1301 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®); 1302 if (ret) { 1303 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1304 WILC_INTR_ENABLE); 1305 return ret; 1306 } 1307 1308 for (i = 0; (i < 5) && (nint > 0); i++, nint--) 1309 reg |= (BIT((27 + i))); 1310 1311 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg); 1312 if (ret) { 1313 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1314 WILC_INTR_ENABLE); 1315 return ret; 1316 } 1317 if (nint) { 1318 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®); 1319 if (ret) { 1320 dev_err(&spi->dev, "Failed read reg (%08x)...\n", 1321 WILC_INTR2_ENABLE); 1322 return ret; 1323 } 1324 1325 for (i = 0; (i < 3) && (nint > 0); i++, nint--) 1326 reg |= BIT(i); 1327 1328 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg); 1329 if (ret) { 1330 dev_err(&spi->dev, "Failed write reg (%08x)...\n", 1331 WILC_INTR2_ENABLE); 1332 return ret; 1333 } 1334 } 1335 1336 return 0; 1337} 1338 1339/* Global spi HIF function table */ 1340static const struct wilc_hif_func wilc_hif_spi = { 1341 .hif_init = wilc_spi_init, 1342 .hif_deinit = wilc_spi_deinit, 1343 .hif_read_reg = wilc_spi_read_reg, 1344 .hif_write_reg = wilc_spi_write_reg, 1345 .hif_block_rx = wilc_spi_read, 1346 .hif_block_tx = wilc_spi_write, 1347 .hif_read_int = wilc_spi_read_int, 1348 .hif_clear_int_ext = wilc_spi_clear_int_ext, 1349 .hif_read_size = wilc_spi_read_size, 1350 .hif_block_tx_ext = wilc_spi_write, 1351 .hif_block_rx_ext = wilc_spi_read, 1352 .hif_sync_ext = wilc_spi_sync_ext, 1353 .hif_reset = wilc_spi_reset, 1354 .hif_is_init = wilc_spi_is_init, 1355}; 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