/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 1232 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1246 stream->timing.display_color_depth; 1248 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1250 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1255 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1262 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1270 stream->clamping.c_depth = stream->timing.display_color_depth; 1271 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1288 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1430 if (result == DC_OK && dc_stream->timing 1879 struct dc_crtc_timing timing; local [all...] |
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
H A D | ramcfg.h | 115 unsigned timing[11]; member in struct:nvbios_ramcfg
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/linux-master/drivers/media/test-drivers/vidtv/ |
H A D | vidtv_mux.h | 92 * @timing: Keeps track of timing related information. 117 struct vidtv_mux_timing timing; member in struct:vidtv_mux
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/linux-master/drivers/ata/ |
H A D | pata_artop.c | 34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we 103 static const u16 timing[2][5] = { local 108 /* Load the PIO timing active/recovery bits */ 109 pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]); 147 * ARTOP6260 and relatives store the timing data differently. 157 static const u8 timing[2][5] = { local 162 /* Load the PIO timing active/recovery bits */ 163 pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]); 216 /* Load the PIO timing active/recovery bits */ 238 * ARTOP6260 and relatives store the timing dat [all...] |
H A D | pata_octeon_cf.c | 73 * boot bus timing register, based on timing multiple 121 * timing requirements of the PIO mode. 131 struct ata_timing timing; local 137 /* These names are timing parameters from the ATA spec */ 141 * A divisor value of four will overflow the timing fields at 150 BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); 152 t2 = timing.active; 160 pause = (int)timing.cycle - (int)timing 225 const struct ata_timing *timing; local [all...] |
H A D | pata_hpt3x2n.c | 36 u32 timing; member in struct:hpt_clock 101 return clocks->timing; 191 u32 reg, timing, mask; local 193 /* Determine timing mask and find matching mode entry */ 201 timing = hpt3x2n_find_mode(ap, mode); 204 reg = (reg & ~mask) | (timing & mask); 222 * hpt3x2n_set_dmamode - DMA timing setup 596 * the MISC. register to stretch the UltraDMA Tss timing.
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H A D | pata_via.c | 238 * Program the VIA registers for DMA and PIO modes. Uses the ata timing 266 /* Calculate the timing values we require */ 269 /* We share 8bit timing so we must merge the constraints */ 502 u32 timing; local 509 pci_read_config_dword(pdev, 0x50, &timing); 510 timing |= 0x80008; 511 pci_write_config_dword(pdev, 0x50, timing); 515 pci_read_config_dword(pdev, 0x50, &timing); 516 timing &= ~0x80008; 517 pci_write_config_dword(pdev, 0x50, timing); [all...] |
/linux-master/drivers/mmc/core/ |
H A D | mmc_ops.h | 50 unsigned int timeout_ms, unsigned char timing,
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/linux-master/include/drm/bridge/ |
H A D | dw_mipi_dsi.h | 42 struct dw_mipi_dsi_dphy_timing *timing);
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/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
H A D | dcn201_optc.h | 72 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
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/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
H A D | dcn30_optc.c | 219 struct dc_crtc_timing *timing) 222 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 285 * Options: any time, start of frame, dp start of frame (range timing) 218 optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, struct dc_crtc_timing *timing) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_clk_mgr.c | 539 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; 540 cfg->v_refresh /= stream->timing.h_total; 541 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 542 / stream->timing.v_total; 558 vertical_blank_in_pixels = stream->timing.h_total * 559 (stream->timing.v_total 560 - stream->timing.v_addressable); 563 * 10000 / stream->timing.pix_clk_100hz; 660 const struct dc_crtc_timing *timing = local 661 &context->streams[0]->timing; [all...] |
/linux-master/drivers/media/pci/zoran/ |
H A D | zoran.h | 51 #define BUZ_MAX_WIDTH (zr->timing->wa) 52 #define BUZ_MAX_HEIGHT (zr->timing->ha) 219 const struct tvnorm *timing; member in struct:zoran
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/linux-master/drivers/video/fbdev/omap2/omapfb/displays/ |
H A D | panel-dpi.c | 144 struct display_timing timing; local 154 r = of_get_display_timing(node, "panel-timing", &timing); 156 dev_err(&pdev->dev, "failed to get video timing\n"); 160 videomode_from_timing(&timing, &vm);
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/linux-master/drivers/staging/media/omap4iss/ |
H A D | iss_csi2.c | 359 * csi2_timing_config - CSI2 timing configuration. 360 * @timing: csi2_timing_cfg structure 363 struct iss_csi2_timing_cfg *timing) 369 if (timing->force_rx_mode) 374 if (timing->stop_state_16x) 379 if (timing->stop_state_4x) 385 reg |= timing->stop_state_counter << 528 struct iss_csi2_timing_cfg *timing = &csi2->timing[0]; local 552 timing 362 csi2_timing_config(struct iss_csi2_device *csi2, struct iss_csi2_timing_cfg *timing) argument [all...] |
/linux-master/drivers/gpu/drm/stm/ |
H A D | dw_mipi_dsi-stm.c | 308 struct dw_mipi_dsi_dphy_timing *timing) 317 timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps); 318 timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps); 319 timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps); 320 timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps); 307 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, struct dw_mipi_dsi_dphy_timing *timing) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_dmub_srv.c | 459 uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000; 461 config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz; 540 * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe 551 struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; 552 struct dc_crtc_timing *phantom_timing = &phantom_stream->timing; 553 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; 634 // the pipe for timing info (stream should be same for any pipe splits) 645 pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; 646 pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - 647 vblank_pipe->stream->timing [all...] |
/linux-master/include/linux/mmc/ |
H A D | host.h | 51 unsigned char timing; /* timing specification used */ member in struct:mmc_ios 359 #define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ 360 #define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ 630 return card->host->ios.timing == MMC_TIMING_SD_HS || 631 card->host->ios.timing == MMC_TIMING_MMC_HS; 637 return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 && 638 card->host->ios.timing <= MMC_TIMING_UHS_DDR50;
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
H A D | dcn32_hwseq.c | 734 * correct timing so we cannot set DISPCLK to min freq or it could cause 736 * freq to ensure that the timing is valid and unchanged. 983 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 987 stream->timing.pix_clk_100hz > 480000; 999 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1000 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | display_mode_util.c | 527 void dml_print_dml_display_cfg_timing(const struct dml_timing_cfg_st *timing, dml_uint_t num_plane) argument 530 dml_print("DML: timing_cfg: plane=%d, HTotal = %d\n", i, timing->HTotal[i]); 531 dml_print("DML: timing_cfg: plane=%d, VTotal = %d\n", i, timing->VTotal[i]); 532 dml_print("DML: timing_cfg: plane=%d, HActive = %d\n", i, timing->HActive[i]); 533 dml_print("DML: timing_cfg: plane=%d, VActive = %d\n", i, timing->VActive[i]); 534 dml_print("DML: timing_cfg: plane=%d, VFrontPorch = %d\n", i, timing->VFrontPorch[i]); 535 dml_print("DML: timing_cfg: plane=%d, VBlankNom = %d\n", i, timing->VBlankNom[i]); 536 dml_print("DML: timing_cfg: plane=%d, RefreshRate = %d\n", i, timing->RefreshRate[i]); 537 dml_print("DML: timing_cfg: plane=%d, PixelClock = %f\n", i, timing->PixelClock[i]); 538 dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing [all...] |
H A D | dml2_wrapper.c | 139 refresh_rate_hz = (int)div_u64((unsigned long long) p->cur_display_config->timing.PixelClock[i] * 1000 * 1000, 140 (p->cur_display_config->timing.HTotal[i] * p->cur_display_config->timing.VTotal[i])); 165 // Add a phantom pipe reflecting the main pipe's timing 166 dml2_util_copy_dml_timing(&p->new_display_config->timing, new_timing_index, subvp_timing_to_add); 170 (p->new_display_config->timing.PixelClock[subvp_timing_to_add] * 1000 * 1000) / 171 (double)p->new_display_config->timing.HTotal[subvp_timing_to_add]); 175 p->new_display_config->timing.VActive[new_timing_index] = subvp_height; 176 p->new_display_config->timing.VTotal[new_timing_index] = subvp_height + 177 p->new_display_config->timing [all...] |
/linux-master/drivers/mmc/host/ |
H A D | sdhci-of-arasan.c | 202 * Some of the Arasan variations might not have timing requirements 400 * Some of the Arasan variations might not have timing 745 switch (host->timing) { 814 switch (host->timing) { 874 switch (host->timing) { 941 switch (host->timing) { 998 switch (host->timing) { 1044 switch (host->timing) { 1112 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 1212 clk_data->clk_phase_in[host->timing]); 1217 arasan_dt_read_clk_phase(struct device *dev, struct sdhci_arasan_clk_data *clk_data, unsigned int timing, const char *prop) argument [all...] |
H A D | sdhci-omap.c | 116 u8 timing; member in struct:sdhci_omap_host 340 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50)) 601 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing) argument 610 if (omap_host->timing == timing) 615 pinctrl_state = omap_host->pinctrl_state[timing]; 623 omap_host->timing = timing; 662 sdhci_omap_set_timing(omap_host, ios->timing); 821 unsigned int timing) 820 sdhci_omap_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/modules/power/ |
H A D | power_helpers.c | 859 * fields which are based on DPCD caps or timing information. To setup PSR in DMUB FW, 886 /* timing parameters */ 887 num_vblank_lines = stream->timing.v_total - 888 stream->timing.v_addressable - 889 stream->timing.v_border_top - 890 stream->timing.v_border_bottom; 892 vblank_time_in_us = (stream->timing.h_total * num_vblank_lines * 1000) / (stream->timing.pix_clk_100hz / 10); 894 line_time_in_us = ((stream->timing.h_total * 1000) / (stream->timing [all...] |
/linux-master/drivers/gpu/drm/tegra/ |
H A D | dsi.c | 36 struct mipi_dphy_timing timing; member in struct:tegra_dsi_state 360 const struct mipi_dphy_timing *timing) 364 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 365 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 366 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 367 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 370 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 371 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 372 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 373 DSI_TIMING_FIELD(timing 358 tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, unsigned long period, const struct mipi_dphy_timing *timing) argument [all...] |