#
ef1c3a7e |
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11-Aug-2023 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci-of-arasan: Use sdhci_pltfm_remove() Use sdhci_pltfm_remove() instead of sdhci_pltfm_unregister() because sdhci_pltfm_unregister() is going to be removed. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230811130351.7038-9-adrian.hunter@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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3de205a0 |
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27-Jul-2023 |
Yangtao Li <frank.li@vivo.com> |
mmc: sdhci-of-arasan: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Yangtao Li <frank.li@vivo.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230727070051.17778-25-frank.li@vivo.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c62da8a8 |
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18-Jul-2023 |
Rob Herring <robh@kernel.org> |
mmc: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230718143054.1065288-1-robh@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
9fab9389 |
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03-Apr-2023 |
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> |
mmc: sdhci-of-arasan: Skip setting clock delay for 400KHz Clock delay settings are not defined for 400KHz, so add frequency check to skip calling the clock delay settings when frequency is <=400KHz. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230403102551.3763054-4-sai.krishna.potthuri@amd.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b095f4f5 |
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03-Apr-2023 |
Swati Agarwal <swati.agarwal@amd.com> |
mmc: sdhci-of-arasan: Add support for eMMC5.1 on Xilinx Versal Net platform Add support for eMMC5.1 on Xilinx Versal Net platform - Add new compatible string(xlnx,versal-net-emmc). - Add support for PHY which is part of Host Controller register space. - Add DLL and Delay Chain mode support and corresponding tap delays for all eMMC modes. - Add Strobe select tap for HS400 mode. Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230403102551.3763054-3-sai.krishna.potthuri@amd.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
189f7370 |
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16-Mar-2023 |
A, Rashmi <rashmi.a@intel.com> |
mmc: sdhci-of-arasan: Remove Intel Thunder Bay SOC support Remove Thunder Bay specific code as the product got cancelled and there are no end customers or users. Signed-off-by: A, Rashmi <rashmi.a@intel.com> Reviewed-by: Hunter, Adrian <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230316120549.21486-2-rashmi.a@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
66756ca3 |
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10-Mar-2023 |
Rob Herring <robh@kernel.org> |
mmc: arasan: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230310144714.1543767-1-robh@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
4453d51e |
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23-Feb-2023 |
Swati Agarwal <swati.agarwal@amd.com> |
mmc: sdhci-of-arasan: Add support to request the "gate" clock Add support to read the optional "gate" clock property and request the clock which will be used to ungate the DLL clock. For Xilinx platforms which has DLL module, dll clock must be ungated/enabled when SD controller operates at higher frequencies like 50 MHz, 100 MHz and 200 MHz. This will be done by explicitly requesting gate clock from the driver. Signed-off-by: Swati Agarwal <swati.agarwal@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20230223141402.23979-1-swati.agarwal@amd.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
0614b0ae |
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18-Oct-2022 |
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> |
mmc: sdhci-of-arasan: Add support for dynamic configuration Add dynamic configuration support for Xilinx ZynqMP which takes care of configuring the SD secure space configuration registers using EEMI APIs, performing SD reset assert and deassert. High level sequence: - Check for the PM dynamic configuration support, if no error proceed with SD dynamic configurations(next steps) otherwise skip the dynamic configuration. - Put the SD Controller in reset. - Configure SD Fixed configurations. - Configure the SD Slot Type. - Configure the BASE_CLOCK. - Configure the 8-bit support. - Bring the SD Controller out of reset. - Wait for 1msec delay. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20221019054857.8286-1-sai.krishna.potthuri@amd.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5d249ac3 |
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26-Oct-2022 |
Brian Norris <briannorris@chromium.org> |
mmc: sdhci-of-arasan: Fix SDHCI_RESET_ALL for CQHCI SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c ("mmc: sdhci-msm: Deactivate CQE during SDHC reset") df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers") The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Do this via the new sdhci_and_cqhci_reset() helper. This patch depends on (and should not compile without) the patch entitled "mmc: cqhci: Provide helper for resetting both SDHCI and CQHCI". Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20221026124150.v4.2.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
869f9875 |
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10-Jun-2022 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
mmc: sdhci-of-arasan: Obviously always return success in remove callback sdhci_pltfm_unregister() returns 0 unconditionally and returning an error in a platform remove callback isn't very sensible. (The only effect of the latter is that the device core emits a generic warning and then removes the device anyhow.) So return 0 unconditionally to make it obvious there is no error forwarded to the upper layers. This is a preparation for making platform remove callbacks return void. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20220610211257.102071-4-u.kleine-koenig@pengutronix.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ded2c4c3 |
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11-May-2022 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
mmc: sdhci-of-arasan: Add NULL check for data field Add NULL check for data field retrieved from of_device_get_match_data() before dereferencing the data. Addresses-coverity: CID 305057:Dereference null return value (NULL_RETURNS) Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1652339993-27280-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
39013f09 |
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29-Aug-2021 |
Rashmi A <rashmi.a@intel.com> |
mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver Intel Thunder Bay SoC eMMC controller is based on Arasan eMMC 5.1 host controller IP Signed-off-by: Rashmi A <rashmi.a@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20210829182443.30802-2-rashmi.a@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5c7e468a |
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15-Jun-2021 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
mmc: arasan: Fix the issue in reading tap values from DT 'of_property_read_variable_u32_array' function returns number of elements read on success. This patch updates the condition check in the driver to overwrite the tap values from DT if exist. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-8-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
4dd7080a |
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15-Jun-2021 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Modify data type of the clk_phase array Modify the data type of the clk_phase array to u32 to make it compatible with the argument requirement of "of_property_read_variable_u32_array". Addresses-coverity: ("incompatible_param") Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-7-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
462f58fd |
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15-Jun-2021 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Use appropriate type of division macro The division macro DIV_ROUND_CLOSEST takes int values as the argument. However the code here uses unsigned int values for this, which is causing the values comparison with 0 as always true. We can use DIV_ROUND_CLOSEST_ULL instead for the same. Addresses-coverity: ("result_independent_of_operands") Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-6-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
66bad6ed |
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15-Jun-2021 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Check return value of non-void funtions At a couple of places, the return values of the non-void functions were not getting checked. This was reported by the coverity tool. Modify the code to check the return values of the same. Addresses-Coverity: ("check_return") Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-5-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
256e4e4e |
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15-Jun-2021 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Skip Auto tuning for DDR50 mode in ZynqMP platform ZynqMP platform does not perform auto tuning in DDR50 mode. Skip the same while the card is operating in DDR50 mode. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-4-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
25a91664 |
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15-Jun-2021 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Add "SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12" quirk. Arasan controller supports AUTO CMD12, this patch adds "SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12" quirk to enable auto cmd12 feature. By using auto cmd12 we can also avoid following error message "Got data interrupt even though no data operation in progress" Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-3-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c0b4e411 |
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15-Jun-2021 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Modified SD default speed to 19MHz for ZynqMP SD standard speed timing was met only at 19MHz and not 25 MHz, that's why changing driver to 19MHz. The reason for this is when a level shifter is used on the board, timing was met for standard speed only at 19MHz. Since this level shifter is commonly required for high speed modes, the driver is modified to use standard speed of 19Mhz. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1623753837-21035-2-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b2af3227 |
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03-Jun-2021 |
Rashmi A <rashmi.a@intel.com> |
mmc: sdhci-of-arasan: Use clock-frequency property to update clk_xin If clock-frequency property is set and it is not the same as the current clock rate of clk_xin(base clock frequency), set clk_xin to use the provided clock rate. Signed-off-by: Rashmi A <rashmi.a@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/20210603182242.25733-2-rashmi.a@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ffd68f35 |
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14-Jan-2021 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: Use dev_err_probe() to avoid spamming logs Using dev_err_probe() can avoid spamming logs when probe is deferred. This function can also help to reduce code the size, uniform error handling and simplify the code. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-5-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2ff0b85d |
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14-Jan-2021 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: Add structure device pointer in probe function Add struct device *dev in probe func() so that it can widely use in probe to make code more readable. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-4-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
80d41efe |
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14-Jan-2021 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: Convert to use np instead of pdev->dev.of_node Use np pointer to simplify code and improve readability. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-3-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
eb085875 |
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14-Jan-2021 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: use of_device_get_match_data() Use of_device_get_match_data() helper to get the match-data. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-2-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
db845093 |
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11-Jan-2021 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: Change code style of mapping the syscon field Change code style of mapping the syscon in sdhci_arasan_update_support64b() for readability and consistency. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20210111155001.12307-3-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
973c7c99 |
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11-Jan-2021 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: Fixed kernel-doc format warning Commit 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay") introduces syscon map sdhci_arasan_update_support64b(). Unfortunately, kernel-doc format script tool has not been run before and causing warning on the documentation style. Below is the output when running the kernel-doc script tool: drivers/mmc/host/sdhci-of-arasan.c:1388: warning: contents before sections Let's fix this by using standard conventions kernel-doc format. Fixes: 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay") Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20210111155001.12307-2-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
a3096ec6 |
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19-Nov-2020 |
Gustavo A. R. Silva <gustavoars@kernel.org> |
mmc: sdhci-of-arasan: Fix fall-through warnings for Clang In preparation to enable -Wimplicit-fallthrough for Clang, fix multiple warnings by explicitly adding multiple break statements instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/387cab3a466038aa5d1fc34b8b6a7c4f693826ea.1605896060.git.gustavoars@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
a42a7ec9 |
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18-Nov-2020 |
Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> |
mmc: sdhci-of-arasan: Fix clock registration error for Keem Bay SOC The commit 16ada730a759 ("mmc: sdhci-of-arasan: Modify clock operations handling") introduced support for platform specific clock operations. Around the same point in time the commit 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay") was also merged. Unfortunate it was not really tested on top of the previously mentioned commit, which causes clock registration failures for Keem Bay SOC devices. Let's fix this, by properly declaring the clock operation for Keem Bay SOC devices. Fixes: 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay") Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20201118120120.24908-2-muhammad.husaini.zulkifli@intel.com Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d06d60d5 |
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16-Nov-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Issue DLL reset explicitly In the current implementation DLL reset will be issued for each ITAP and OTAP setting inside ATF, this is creating issues in some scenarios and this sequence is not inline with the TRM. To fix the issue, DLL reset should be removed from the ATF and host driver will request it explicitly. This patch update host driver to explicitly request for DLL reset before ITAP (assert DLL) and after OTAP (release DLL) settings. Fixes: a5c8b2ae2e51 ("mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup") Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1605515565-117562-4-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d338c6d0 |
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16-Nov-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Use Mask writes for Tap delays Mask the ITAP and OTAP delay bits before updating with the new tap value for Versal platform. Fixes: 1a470721c8f5 ("sdhci: arasan: Add support for Versal Tap Delays") Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1605515565-117562-3-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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9e953432 |
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16-Nov-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Allow configuring zero tap values Allow configuring the Output and Input tap values with zero to avoid failures in some cases (one of them is SD boot mode) where the output and input tap values may be already set to non-zero. Fixes: a5c8b2ae2e51 ("mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup") Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1605515565-117562-2-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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21b2cec6 |
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03-Sep-2020 |
Douglas Anderson <dianders@chromium.org> |
mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.4 This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v4.4 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # SH_MMCIF Tested-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200903162412.1.Id501e96fa63224f77bb86b2135a5e8324ffb9c43@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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72ea817d |
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02-Sep-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
mmc: sdhci-of-arasan: Simplify with dev_err_probe() Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200902193658.20539-8-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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88e1d0b1 |
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14-Jul-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: fix timings allocation code The initial code that was adding delays was doing a cast over undefined memory. This meant that the delays would be all gibberish. This change, allocates all delays on the stack, and assigns them from the ZynqMP & Versal macros/phase-list. And then finally copies them over the common iclk_phase & oclk_phase variables. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://lore.kernel.org/r/1594753953-62980-1-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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654e8750 |
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01-Jul-2020 |
Lee Jones <lee.jones@linaro.org> |
mmc: sdhci-of-arasan: Correct formatting and provide missing function arg(s) Kerneldoc expects arg descriptions to be in the format '@.*: '. If either the '@' or the ':' is omitted then kerneldoc complains that the description is missing. Add the missing ':' here and provide a new description for 'value'. Fixes the following kernel build W=1 warnings: drivers/mmc/host/sdhci-of-arasan.c:1394: warning: Function parameter or member 'host' not described in 'sdhci_arasan_update_support64b' drivers/mmc/host/sdhci-of-arasan.c:1394: warning: Function parameter or member 'value' not described in 'sdhci_arasan_update_support64b' drivers/mmc/host/sdhci-msm.c:1887:6: warning: no previous prototype for ‘sdhci_msm_dump_vendor_regs’ [-Wmissing-prototypes] Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Xiaobo Xie <X.Xie@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com> Cc: Soeren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20200701124702.908713-12-lee.jones@linaro.org Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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c99e1d0c |
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08-Jun-2020 |
Chuhong Yuan <hslester96@gmail.com> |
mmc: sdhci-of-arasan: Add missed checks for devm_clk_register() These functions do not check the return value of devm_clk_register(): - sdhci_arasan_register_sdcardclk() - sdhci_arasan_register_sampleclk() Therefore, add the missed checks to fix them. Fixes: c390f2110adf1 ("mmc: sdhci-of-arasan: Add ability to export card clock") Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200608162226.3259186-1-hslester96@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
36c6aada |
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26-May-2020 |
Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> |
mmc: sdhci-of-arasan: Add support for Intel Keem Bay Intel Keem Bay SoC eMMC/SD/SDIO controller is based on Arasan SD 3.0 / eMMC 5.1 host controller IP. However, it does not support 64-bit access as its AXI interface has 32-bit address ports. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200526062758.17642-3-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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098c408b |
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16-Apr-2020 |
Nathan Chancellor <nathan@kernel.org> |
mmc: sdhci-of-arasan: Remove uninitialized ret variables Clang warns: drivers/mmc/host/sdhci-of-arasan.c:784:9: warning: variable 'ret' is uninitialized when used here [-Wuninitialized] return ret; ^~~ drivers/mmc/host/sdhci-of-arasan.c:738:9: note: initialize the variable 'ret' to silence this warning int ret; ^ = 0 drivers/mmc/host/sdhci-of-arasan.c:860:9: warning: variable 'ret' is uninitialized when used here [-Wuninitialized] return ret; ^~~ drivers/mmc/host/sdhci-of-arasan.c:810:9: note: initialize the variable 'ret' to silence this warning int ret; ^ = 0 2 warnings generated. This looks like a copy paste error. Neither function has handling that needs ret so just remove it and return 0 directly. Link: https://github.com/ClangBuiltLinux/linux/issues/996 Reported-by: kernelci.org bot <bot@kernelci.org> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://lore.kernel.org/r/20200416182402.16858-1-natechancellor@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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4908460e |
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06-Apr-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Fix kernel-doc warnings Modify code to fix the warnings reported by kernel-doc for better documentation. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://lore.kernel.org/r/1586195015-128992-7-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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16ada730 |
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06-Apr-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Modify clock operations handling The SDHCI clock operations are platform specific. So it better to define them separately for particular platform. This will prevent multiple if..else conditions and will make it easy for user to add their own clock operations handlers. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://lore.kernel.org/r/1586195015-128992-6-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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37d3ee7c |
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06-Apr-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Rearrange the platform data structs for modularity Existing driver code has the platform specific structures scattered throughout the driver code. Rearrange the platform specific data structures for more modularity and readability. This will help in adding new static functions with more ease. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://lore.kernel.org/r/1586195015-128992-5-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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19ee441f |
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06-Apr-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Rename sdhci_arasan_data to avoid confusion There is 'struct sdhci_arasan_data' but also 'struct sdhci_arasan_of_data sdhci_arasan_data'. Rename the latter to avoid confusion with the name of the struct. Reported-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://lore.kernel.org/r/1586195015-128992-4-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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1a470721 |
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06-Apr-2020 |
Manish Narani <manish.narani@xilinx.com> |
sdhci: arasan: Add support for Versal Tap Delays Add support to set tap delays for Xilinx Versal SD controller. The tap delay registers have moved to SD controller space in Versal. Make the changes accordingly. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1586195015-128992-3-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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426c8d85 |
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24-Apr-2020 |
Rajan Vaja <rajan.vaja@xilinx.com> |
firmware: xilinx: Use APIs instead of IOCTLs Remove IOCTL API and use individual APIs for better readability. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-12-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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c2c5252c |
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06-Mar-2020 |
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> |
mmc: sdhci: arasan: Use sdhci_set_power_and_voltage() The sdhci core provides a helper function with the same functionality as this controller's set_power() callback. Use it instead. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200306174413.20634-3-nsaenzjulienne@suse.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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2a2b8216 |
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21-Jan-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Remove quirk for broken base clock This patch removes quirk which indicates a broken base clock. This was making the kernel report wrong base clock of ~187MHz instead of 200MHz even as the measurement on the hardware was showing 200MHz. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1579602095-30060-5-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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8d2e3343 |
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21-Jan-2020 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms The DLL resets are required while executing the auto tuning procedure in ZynqMP. This patch adds code to support the same. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1579602095-30060-4-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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a5c8b2ae |
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19-Nov-2019 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup Apart from taps set by auto tuning, ZynqMP platform has feature to set the tap values manually. Add support to set tap delay values in HW via ZynqMP SoC framework. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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f3dafc37 |
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19-Nov-2019 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Add support to set clock phase delays for SD Add support to read Clock Phase Delays from the DT and set it via clk_set_phase() API from clock framework. Some of the controllers might have their own handling of setting clock delays, for this keep the set_clk_delays as function pointer which can be assigned controller specific handling of the same. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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07a14d1d |
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19-Nov-2019 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Add sampling clock for a phy to use There are some operations like setting the clock delays may need to have two clocks, one for output path and one for input path. Adding input path clock for some phys to use. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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e1463618 |
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19-Nov-2019 |
Manish Narani <manish.narani@xilinx.com> |
mmc: sdhci-of-arasan: Separate out clk related data to another structure To improve the code readability, use two different structs, one for clock provider data and one for mmc platform data. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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d1807ad6 |
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08-Oct-2019 |
Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> |
mmc: sdhci-of-arasan: Add Support for Intel LGM SDXC The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM SDXC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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5c1a4f40 |
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26-Aug-2019 |
Ramuthevar Vadivel Muruganx <vadivel.muruganx.ramuthevar@linux.intel.com> |
mmc: sdhci-of-arasan: Add Support for Intel LGM eMMC The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM eMMC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Muruganx <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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7bda9482 |
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21-Mar-2019 |
Christoph Muellner <christoph.muellner@theobroma-systems.com> |
mmc: sdhci-of-arasan: Add DTS property to disable DCMDs. Direct commands (DCMDs) are an optional feature of eMMC 5.1's command queue engine (CQE). The Arasan eMMC 5.1 controller uses the CQHCI, which exposes a control register bit to enable the feature. The current implementation sets this bit unconditionally. This patch allows to suppress the feature activation, by specifying the property disable-cqe-dcmd. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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41fd4cae |
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10-Dec-2018 |
Faiz Abbas <faiz_abbas@ti.com> |
mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driver The host controllers on TI's AM654 SOCs are not compatible with the phy and consumer model of the sdhci-of-arasan driver. It turns out that for optimal operation at higher speeds, a special tuning procedure needs to be implemented which involves configuration of platform specific phy registers. Therefore, branch out to a new sdhci_am654 driver and add the phy register space with all phy configurations to it. Populate AM654 specific callbacks to sdhci_ops and add SDHCI_QUIRKS wherever applicable. Only add support for upto High Speed for SD card and upto DDR52 speed mode for eMMC. Higher speeds will be added in subsequent patches. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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f0061fed |
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04-Oct-2018 |
Faiz Abbas <faiz_abbas@ti.com> |
mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY The current arasan sdhci PHY configuration isn't compatible with the PHY on TI's AM654 devices. Therefore, add a new compatible, AM654 specific quirks and a new AM654 specific set_clock function which configures the PHY in a sane way. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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06b23ca0 |
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04-Oct-2018 |
Faiz Abbas <faiz_abbas@ti.com> |
mmc: sdhci-of-arasan: Add a single data structure to incorporate pdata and soc_ctl_map Currently, the driver passes platform data as a global structure and uses the .data of of_device_id to pass the soc_ctl_map. To make the implementation more flexible add a single data structure that incorporates both of the above and pass it in the .data of of_device_id. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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60208a26 |
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06-Aug-2018 |
Michal Simek <michal.simek@xilinx.com> |
mmc: sdhci-of-arasan: Do now show error message in case of deffered probe When mmc-pwrseq property is passed mmc_pwrseq_alloc() can return -EPROBE_DEFER because driver for power sequence provider is not probed yet. Do not show error message when this situation happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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3f2c7d5d |
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20-Jun-2018 |
Helmut Grohne <h.grohne@intenta.de> |
mmc: sdhci-of-arasan: Add quirk for unstable clocks Some controllers immediately report SDHCI_CLOCK_INT_STABLE after enabling the clock even when the clock is not stable. When used in conjunction with older/slower cards, this can result in: mmc0: error -84 whilst initialising SD card When the stable reporting is known to be broken, we simply wait for the maximum stabilization period. Signed-off-by: Helmut Grohne <h.grohne@intenta.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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970f2d90 |
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19-Apr-2018 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
mmc: host: simplify getting .drvdata We should get drvdata from struct device directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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57aac337 |
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13-Mar-2018 |
Phil Edworthy <Phil.Edworthy@renesas.com> |
mmc: sdhci-of-arasan: Add quirk to avoid unexpected interrupt msgs On SD 2.00 cards we get lots of these messages: "mmc0: Got data interrupt 0x00000002 even though no data operation was in progress" By applying the SDHCI_QUIRK2_STOP_WITH_TC quirk, the messages no longer happen. A single card claiming to be SD 3.00 compliant also generates the interrupts, but since the card's manfacturing date is 2002 mar, it's unlikely to really be SD 3.00. This card is a 8GB SanDisk 'SU08G' 8.0 (SDHC class 4). This has been reported on Xilinx devices that also use the Arasan IP. See https://patchwork.kernel.org/patch/8062871/ This has been tested on the Renesas RZ/ND-DB board with the RZ/N1 SoC. The Arasan IP in this device is version 1.39a and uses a max SD clock of 50MHz and does not support DDR modes. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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84362d79 |
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15-Jan-2018 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1 Add CQHCI initialization and implement CQHCI operations for Arasan SDHCI variant host, namely arasan,sdhci-5.1, which is used by Rockchip RK3399 platform. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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043f2dca |
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27-Nov-2017 |
Milan Stevanovic <milan.o.stevanovic@gmail.com> |
mmc: sdhci-of-arasan: Add sdhci_arasan_set_power The power register needs to have a valid voltage set even when the power supply is managed by an external regulator. Signed-off-by: Milan Stevanovic <milan.o.stevanovic@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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a81dae3a |
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07-Aug-2017 |
Julia Lawall <Julia.Lawall@lip6.fr> |
mmc: sdhci-of-arasan: constify sdhci_pltfm_data and sdhci_ops structures The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, while the sdhci_ops structure is only stored in the ops field of a sdhci_pltfm_data structure, which is also const. Thus both kinds of structures can be const as well. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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0daf72fe |
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16-Jul-2017 |
Jean-Francois Dagenais <jeff.dagenais@gmail.com> |
mmc: sdhci-of-arasan: use io functions from sdhci.h This increases consistency of the code across the sdhci family. Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
940e698c |
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02-May-2017 |
Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
mmc: sdhci-of-arasan: Trivial print fix ret is signed however is printed as unsigned fix the same. If printed as a negative number the result is easier to read. No functional change. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
8cc35289 |
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24-Mar-2017 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci: clarify the get_timeout_clock callback Currently the get_timeout_clock callback doesn't clearly have a statement that it needs the variant drivers to return the timeout clock rate in kHz if the SDHCI_TIMEOUT_CLK_UNIT isn't present, otherwise the variant drivers should return it in MHz. It's also very likely that further variant drivers which are going to use this callback will be confused by this situation. Given the fact that moderm sdhci variant hosts are very prone to get the timeout clock from common clock framework (actually the only three users did that), it's more natural to return the value in Hz and we make an explicit comment there. Then we put the unit conversion inside the sdhci core. Thus will improve the code and prevent further misuses. Reported-by: Anssi Hannula <anssi.hannula@bitwise.fi> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
d1e4f74f |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Do not use spin lock in set_ios paths The spin lock is not necessary in set_ios. Anything that is racing with changes to the I/O state is already broken. The mmc core already provides synchronization via "claiming" the host. So remove spin_lock and friends from sdhci_set_ios and related callbacks. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
d38dcad4 |
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20-Mar-2017 |
Adrian Hunter <adrian.hunter@intel.com> |
mmc: sdhci: Let drivers decide whether to use mmc_retune_needed() with pm Devices might save and restore tuning values so that re-tuning might not be needed after a pm transition. Let drivers decide by pushing the mmc_retune_needed() logic down to them. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
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#
16681037 |
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13-Feb-2017 |
Anssi Hannula <anssi.hannula@bitwise.fi> |
mmc: sdhci-of-arasan: fix incorrect timeout clock sdhci_arasan_get_timeout_clock() divides the frequency it has with (1 << (13 + divisor)). However, the divisor is not some Arasan-specific value, but instead is just the Data Timeout Counter Value from the SDHCI Timeout Control Register. Applying it here like this is wrong as the sdhci driver already takes that value into account when calculating timeouts, and in fact it *sets* that register value based on how long a timeout is wanted. Additionally, sdhci core interprets the .get_timeout_clock callback return value as if it were read from hardware registers, i.e. the unit should be kHz or MHz depending on SDHCI_TIMEOUT_CLK_UNIT capability bit. This bit is set at least on the tested Zynq-7000 SoC. With the tested hardware (SDHCI_TIMEOUT_CLK_UNIT set) this results in too high a timeout clock rate being reported, causing the core to use longer-than-needed timeouts. Additionally, on a partitioned MMC (therefore having erase_group_def bit set) mmc_calc_max_discard() disables discard support as it looks like controller does not support the long timeouts needed for that. Do not apply the extra divisor and return the timeout clock in the expected unit. Tested with a Zynq-7000 SoC and a partitioned Toshiba THGBMAG5A1JBAWR eMMC card. Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi> Fixes: e3ec3a3d11ad ("mmc: arasan: Add driver for Arasan SDHCI") Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
8a3bee9b |
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30-Sep-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: add sdhci_arasan_voltage_switch for arasan, 5.1 Per the vendor's requirement, we shouldn't do any setting for 1.8V Signaling Enable, otherwise the interaction/behaviour between phy and controller will be undefined. Mostly it works fine if we do that, but we still see failures. Anyway, let's fix it to meet the vendor's requirement. The error log looks like: [ 93.405085] mmc1: unexpected status 0x800900 after switch [ 93.408474] mmc1: switch to bus width 1 failed [ 93.408482] mmc1: mmc_select_hs200 failed, error -110 [ 93.408492] mmc1: error -110 during resume (card was removed?) [ 93.408705] PM: resume of devices complete after 213.453 msecs Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
13d62fd2 |
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25-Sep-2016 |
Wei Yongjun <weiyongjun1@huawei.com> |
mmc: sdhci-of-arasan: Fix non static symbol warning Fixes the following sparse warning: drivers/mmc/host/sdhci-of-arasan.c:253:6: warning: symbol 'sdhci_arasan_reset' was not declared. Should it be static? Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3794c542 |
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16-Sep-2016 |
Zach Brown <zach.brown@ni.com> |
mmc: sdhci-of-arasan: Set controller to test mode when no CD bit The sdhci controller on xilinx zynq devices will not function unless the CD bit is provided. http://www.xilinx.com/support/answers/61064.html In cases where it is impossible to provide the CD bit in hardware, setting the controller to test mode and then setting inserted to true will get the controller to function without the CD bit. When the device has the property xlnx,fails-without-test-cd the driver changes the controller to test mode and sets test inserted to true to make the controller function. Signed-off-by: Zach Brown <zach.brown@ni.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b2ca77c9 |
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26-Aug-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: Properly set corecfg_clockmultiplier on rk3399 corecfg_clockmultiplier indicates clock multiplier value of programmable clock generator which should be the same value of SDHCI_CAPABILITIES_1. The default value of the register, corecfg_clockmultiplier, is 0x10. But actually it is a mistake by designer as our intention was to set it to be zero which means we don't support programmable clock generator. So we have to make it to be zero on bootloader which seems work fine until now. But now we find an issue that when deploying genpd support for it, the remove callback will trigger the genpd to poweroff the power domain for sdhci-of-arasan which manage the controller, phy and corecfg_* stuff. So when we do bind/unbind the driver, we have already reinit the controller and phy, but without doing that for corecfg_*. Regarding to only the corecfg_clockmultipler is wrong, let's fix it by explicitly marking it to be zero when probing. With this change, we could do bind/unbind successfully. Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Cc: Douglas Anderson <dianders@chromium.org> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Ziyuan Xu <xzy.xu@rock-chips.com> Tested-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b2db9c67 |
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18-Aug-2016 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-of-arasan: Don't power PHY w/ slow/no clock PHY intended to be used with the Arasan SDHCI 5.1 controller has trouble turning on when the card clock is slow or off. Strangely these problems appear to show up consistently on some boards while other boards work fine, but on the boards where it shows up the problem reproduces 100% of the time and is quite consistent in its behavior. These problems can be fixed by always making sure that we power on the PHY (and turn on its DLL) when the card clock is faster than about 50 MHz. Once on, we need to make sure that we never power down the PHY / turn off its DLL until the clock is faster again. We'll add logic for handling this into the sdhci-of-arasan driver. Note that right now the only user of a PHY in the sdhci-of-arasan driver is arasan,sdhci-5.1. It's presumed that all arasan,sdhci-5.1 PHY implementations need this workaround, so the logic is only contingent on having a PHY to control. If future Arasan controllers don't have this problem we can add code to decide if we want this flow or not. Also note that we check for slow clocks by checking for <= 400 kHz rather than checking for 50 MHz. This keeps things the most consistent and also means we can power the PHY on at max speed (where the DLL will lock fastest). Presumably anyone who intends to run with a card clock of < 50 MHz and > 400 kHz will be running on a device where this problem is fixed anyway. I believe this brings some resolution to the problems reported before. See the commit 6fc09244d74d ("mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes"). Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
6fc09244 |
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27-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes This reverts commit 4ac0d5f245e1 ("mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes"), resolving conflicts with other patches that have come after. It appears that on some boards / with some eMMC devices that the patch is causing problems. Presumably turning the phy off and on again at the wrong time while initially setting up the card is confusing the card, the host, or the PHY. We have lots of power cycles while initially setting up the card because the main sdhci driver often turns off the clock by clearing SDHCI_CLOCK_CARD_EN and then calls host->ops->set_clock() to set the clock again. With all of those, we ended up with lots of power cycles. Presumably the arguments made in the original patch still hold. That is, whenever the card clock is turned off and on again (or changed) we really should wait for the DLL to lock again. However, perhaps it's really not that critical for the lower speeds. It's possible that the right answer here is: * Whenever set_clock() is called we should double-check that the DLL is locked. * Whenever set_clock() is called and we're actually changing clocks we should do a power cycle around that. * When we're doing a power cycle just because the clock changed, we probably shouldn't do quite as many things (maybe don't need to recalibarate, etc). Unfortunately the interaction between SDHCI and the PHY is extremely limited because of the limited PHY API. The PHY does have a reference to the card clock and could theoretically register for notifications, except that our clock is query only (it uses CLK_GET_RATE_NOCACHE) and so can't really be notified about updates. I believe we would need a major redesign of clock handling in SDHCI core to do better than that, or we would need to make our one fake notifications. :( Let's hope that we can eventually get more information from Arasan on how all this should be handled before doing tons more work. Until then, let's get back to a known working state. Note that the rest of the patches in the 150 MHz series should still work fine even without this one. Signed-off-by: Douglas Anderson <dianders@chromium.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
c390f211 |
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20-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-of-arasan: Add ability to export card clock Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock in order to function properly. Let's add the ability to expose this clock. Any PHY that needs to know the clock rate can add a reference and query the clock rate. At the moment we register a CLK_GET_RATE_NOCACHE clock that simply allows querying the clock. This allows us to be less intrusive with regards to the main SDHCI driver, which has complex logic for adjusting the SD clock. Right now we always fully power cycle the PHY when the clock changes and that gives the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3ea4666e |
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20-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 In the the earlier change in this series ("Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs") we can see the mechansim for specifying a syscon to properly set corecfg registers in sdhci-of-arasan. Now let's use this mechanism to properly set corecfg_baseclkfreq on rk3399. >From [1] the corecfg_baseclkfreq is supposed to be set to: Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. This is a relatively easy thing to do. Note that we assume that xin_clk is not dynamic and we can check the clock at probe time. If any real devices have a dynamic xin_clk future patches could register for notifiers for the clock. At the moment, setting corecfg_baseclkfreq is only supported for rk3399 since we need a specific map for each implementation. The code is written in a generic way that should make this easy to extend to other SoCs. Note that a specific compatible string for rk3399 is already in use and so we add that to the table to match rk3399. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
ca572f46 |
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20-Jun-2016 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes In commit 802ac39a5566 ("mmc: sdhci-of-arasan: fix set_clock when a phy is supported") we added code to power the PHY off and on whenever the clock was changed but we avoided doing the power cycle code when the clock was low speed. Let's now do it always. Although there may be other reasons for power cycling the PHY when the clock changes, one of the main reasons is that we need to give the DLL a chance to re-lock with the new clock. One of the things that the DLL is for is tuning the Receive Clock in HS200 mode and STRB in HS400 mode. Thus it is clear that we should make sure we power cycle the PHY (and wait for the DLL to lock) when we know we'll be in one of these two speed modes. That's what the original code did, though it used the clock rate rather than the speed mode. However, even in speed modes other than HS200,/HS400 the DLL is used for something since it can be clearly observed that the PHY doesn't function properly if you leave the DLL off. Although it appears less important to power cycle the PHY and wait for the DLL to lock when not in HS200/HS400 modes (no bugs were reported), it still seems wise to let the locking always happen nevertheless. Note: as part of this, we make sure that we never try to turn the PHY on when the clock is off (when the clock rate is 0). The PHY cannot work when the clock is off since its DLL can't lock. This change requires ("phy: rockchip-emmc: Increase lock time allowance") and will cause problems if picked without that change. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
a05c8465 |
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25-May-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: implement enhanced strobe callback Currently sdhci-arasan 5.1 can support enhanced strobe function, and we now limit it just for "arasan,sdhci-5.1". Add mmc-hs400-enhanced-strobe in DT to enable the function if we're sure our controller can support it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
802ac39a |
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03-May-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: fix set_clock when a phy is supported commit 61b914eb81f8 ("mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan") introduce phy support for arasan. According to the vendor's databook, we should make sure the phy is in poweroff status before we configure the clk stuff. Otherwise it may cause some IO sample timing issues from the test. And we don't need this extra operation while running in low performance mode since phy doesn't trigger sampling block. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
91aa3661 |
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07-Mar-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan This patch adds Generic PHY access for sdhci-of-arasan. Driver can get PHY handler from dt-binding, and power-on/init the PHY. Currently, it's just mandatory for arasan,sdhci-5.1. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
278d0962 |
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07-Mar-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: fix missing sdhci_pltfm_free for err handling Currently, some err handling of sdhci_arasan_probe return directly without calling sdhci_pltfm_free. This patch fixes them. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
84275048 |
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07-Mar-2016 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: remove disable clk_ahb from sdhci_arasan_resume We don't really need disable clk_ahb when failing to resume. Otherwise we may take risk of bus error for accessing register without clk_ahb. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
89211418 |
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16-Feb-2016 |
Jisheng Zhang <jszhang@marvell.com> |
mmc: sdhci-of-arasan: use sdhci_pltfm_init for private allocation Commit 0e748234293f ("mmc: sdhci: Add size for caller in init+register") allows users of sdhci_pltfm to allocate private space in calls to sdhci_pltfm_init+sdhci_pltfm_register. This patch migrates the sdhci-of-arasan driver to this allocation. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
0c7fe32e |
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16-Feb-2016 |
Jisheng Zhang <jszhang@marvell.com> |
mmc: sdhci-of-arasan: fix clk issue in sdhci_arasan_remove() sdhci_pltfm_unregister() could operate host's registers, it will cause problems if the clk is already disabled and unprepared. Fix this issue by moving the clk_disable_unprepare() call to the end of remove function. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
e99369dc |
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23-Dec-2015 |
Rameshwar Prasad Sahu <rsahu@apm.com> |
mmc: sdhci-of-arasan: Remove no-hispd and no-cmd23 quirks for sdhci-arasan4.9a The Arason SD host controller supports set block count command (cmd23) and high speed mode. This patch re-enable both of these features that was disabled. For device that doesn't support high speed, it should configure its capability register accordingly instead disables it explicitly. Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
da795ec2 |
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11-Aug-2015 |
Shawn Lin <shawn.lin@rock-chips.com> |
mmc: sdhci-of-arasan: Add the support for sdhci-5.1 This patch adds the compatible string in sdhci-of-arasan.c to support sdhci-arasan5.1 version of controller. No documented controller IP version is found in the TRM, so we use ths version of command queueing engine integrated into this controller by arasan to specify our controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2d532d45 |
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09-Jun-2015 |
Suneel Garapati <suneel.garapati@xilinx.com> |
mmc: sdhci-of-arasan: add quirks for broken clock base adding SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,SDHCI_QUIRK2_PRESET_VALUE_BROKEN flags for arasan sdhc. Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
308f3f8d |
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04-May-2015 |
Suman Tripathi <stripathi@apm.com> |
mmc: sdhci-of-arasan: Add the support for sdhci-arasan4.9a This patch adds the quirks and compatible string in sdhci-of-arasan.c to support sdhci-arasan4.9a version of controller. Signed-off-by: Suman Tripathi <stripathi@apm.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
16b23787 |
|
06-Apr-2015 |
Michal Simek <michal.simek@xilinx.com> |
mmc: sdhci-of-arasan: Call OF parsing for MMC Also check MMC OF properties. The controller supports MMC too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
83eacdfa |
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27-Feb-2015 |
Kevin Hao <haokexin@gmail.com> |
mmc: sdhci: disable the clock in sdhci_pltfm_unregister() So we can avoid to sprinkle the clk_disable_unprepare() in many drivers. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
b1df9de7 |
|
28-Oct-2014 |
Mike Looijmans <mike.looijmans@topic.nl> |
mmc: sdhci-of-arasan: Omit superfluous error messages sdhci_add_host and sdhci_platfm_init already report failure, so don't emit error messages when a failure occurs. This prevents occurences of "deferred" messages when required power supplies are not ready for operation yet. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5d0e1194 |
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23-Oct-2014 |
Mike Looijmans <mike.looijmans@topic.nl> |
mmc: sdhci-of-arasan: Use signed formatting in error messages "ret" is a signed int, so use "%d" in format strings instead of "%u". This prevents cryptic codes in error messages like this: sdhci-arasan e0101000.sdhci: platform register failed (4294966779) Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
2137f5d3 |
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12-Aug-2014 |
Peter Griffin <peter.griffin@linaro.org> |
mmc: remove .owner field for drivers using module_platform_driver This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
96d7b78c |
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24-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
mmc: sdhci: convert sdhci_set_uhs_signaling() into a library function Add sdhci_set_uhs_signaling() and always call the set_uhs_signaling method. This avoids quirks being added into sdhci_set_uhs_signaling(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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1771059c |
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24-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
mmc: sdhci: convert sdhci_set_clock() into a library function Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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03231f9b |
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24-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
mmc: sdhci: convert reset into a library function Rather than having platform_reset_enter/platform_reset_exit methods, turn the core of the reset handling into a library function which platforms can call at the appropriate moment in their (new) reset method. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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2317f56c |
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24-Apr-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
mmc: sdhci: convert generic bus width setup to library function Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-by: Markus Pargmann <mpa@pengutronix.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
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e3ec3a3d |
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02-Dec-2013 |
Soren Brinkmann <soren.brinkmann@xilinx.com> |
mmc: arasan: Add driver for Arasan SDHCI Add a driver for Arasan's SDHCI controller core. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Rob Herring <rob.herring@calxeda.com> [binding] Acked-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Chris Ball <chris@printf.net>
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