1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
4 *
5 * This driver is heavily based upon:
6 *
7 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
8 *
9 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
10 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
11 * Portions Copyright (C) 2003		Red Hat Inc
12 * Portions Copyright (C) 2005-2010	MontaVista Software, Inc.
13 *
14 *
15 * TODO
16 *	Work out best PLL policy
17 */
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME	"pata_hpt3x2n"
27#define DRV_VERSION	"0.3.19"
28
29enum {
30	PCI66		=	(1 << 1),
31	USE_DPLL	=	(1 << 0)
32};
33
34struct hpt_clock {
35	u8	xfer_speed;
36	u32	timing;
37};
38
39/* key for bus clock timings
40 * bit
41 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
42 *        cycles = value + 1
43 * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
44 *        cycles = value + 1
45 * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
46 *        register access.
47 * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
48 *        register access.
49 * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
50 * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
51 * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
52 * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
53 *        register access.
54 * 28     UDMA enable.
55 * 29     DMA  enable.
56 * 30     PIO_MST enable. If set, the chip is in bus master mode during
57 *        PIO xfer.
58 * 31     FIFO enable. Only for PIO.
59 */
60
61/* 66MHz DPLL clocks */
62
63static struct hpt_clock hpt3x2n_clocks[] = {
64	{	XFER_UDMA_7,	0x1c869c62	},
65	{	XFER_UDMA_6,	0x1c869c62	},
66	{	XFER_UDMA_5,	0x1c8a9c62	},
67	{	XFER_UDMA_4,	0x1c8a9c62	},
68	{	XFER_UDMA_3,	0x1c8e9c62	},
69	{	XFER_UDMA_2,	0x1c929c62	},
70	{	XFER_UDMA_1,	0x1c9a9c62	},
71	{	XFER_UDMA_0,	0x1c829c62	},
72
73	{	XFER_MW_DMA_2,	0x2c829c62	},
74	{	XFER_MW_DMA_1,	0x2c829c66	},
75	{	XFER_MW_DMA_0,	0x2c829d2e	},
76
77	{	XFER_PIO_4,	0x0c829c62	},
78	{	XFER_PIO_3,	0x0c829c84	},
79	{	XFER_PIO_2,	0x0c829ca6	},
80	{	XFER_PIO_1,	0x0d029d26	},
81	{	XFER_PIO_0,	0x0d029d5e	},
82};
83
84/**
85 *	hpt3x2n_find_mode	-	reset the hpt3x2n bus
86 *	@ap: ATA port
87 *	@speed: transfer mode
88 *
89 *	Return the 32bit register programming information for this channel
90 *	that matches the speed provided. For the moment the clocks table
91 *	is hard coded but easy to change. This will be needed if we use
92 *	different DPLLs
93 */
94
95static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
96{
97	struct hpt_clock *clocks = hpt3x2n_clocks;
98
99	while (clocks->xfer_speed) {
100		if (clocks->xfer_speed == speed)
101			return clocks->timing;
102		clocks++;
103	}
104	BUG();
105	return 0xffffffffU;	/* silence compiler warning */
106}
107
108/**
109 *	hpt372n_filter	-	mode selection filter
110 *	@adev: ATA device
111 *	@mask: mode mask
112 *
113 *	The Marvell bridge chips used on the HighPoint SATA cards do not seem
114 *	to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
115 */
116static unsigned int hpt372n_filter(struct ata_device *adev, unsigned int mask)
117{
118	if (ata_id_is_sata(adev->id))
119		mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
120
121	return mask;
122}
123
124/**
125 *	hpt3x2n_cable_detect	-	Detect the cable type
126 *	@ap: ATA port to detect on
127 *
128 *	Return the cable type attached to this port
129 */
130
131static int hpt3x2n_cable_detect(struct ata_port *ap)
132{
133	u8 scr2, ata66;
134	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
135
136	pci_read_config_byte(pdev, 0x5B, &scr2);
137	pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
138
139	udelay(10); /* debounce */
140
141	/* Cable register now active */
142	pci_read_config_byte(pdev, 0x5A, &ata66);
143	/* Restore state */
144	pci_write_config_byte(pdev, 0x5B, scr2);
145
146	if (ata66 & (2 >> ap->port_no))
147		return ATA_CBL_PATA40;
148	else
149		return ATA_CBL_PATA80;
150}
151
152/**
153 *	hpt3x2n_pre_reset	-	reset the hpt3x2n bus
154 *	@link: ATA link to reset
155 *	@deadline: deadline jiffies for the operation
156 *
157 *	Perform the initial reset handling for the 3x2n series controllers.
158 *	Reset the hardware and state machine,
159 */
160
161static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
162{
163	struct ata_port *ap = link->ap;
164	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
165	static const struct pci_bits hpt3x2n_enable_bits[] = {
166		{ 0x50, 1, 0x04, 0x04 },
167		{ 0x54, 1, 0x04, 0x04 }
168	};
169	u8 mcr2;
170
171	if (!pci_test_config_bits(pdev, &hpt3x2n_enable_bits[ap->port_no]))
172		return -ENOENT;
173
174	/* Reset the state machine */
175	pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
176	udelay(100);
177
178	/* Fast interrupt prediction disable, hold off interrupt disable */
179	pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);
180	mcr2 &= ~0x07;
181	pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);
182
183	return ata_sff_prereset(link, deadline);
184}
185
186static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
187			     u8 mode)
188{
189	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
190	int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
191	u32 reg, timing, mask;
192
193	/* Determine timing mask and find matching mode entry */
194	if (mode < XFER_MW_DMA_0)
195		mask = 0xcfc3ffff;
196	else if (mode < XFER_UDMA_0)
197		mask = 0x31c001ff;
198	else
199		mask = 0x303c0000;
200
201	timing = hpt3x2n_find_mode(ap, mode);
202
203	pci_read_config_dword(pdev, addr, &reg);
204	reg = (reg & ~mask) | (timing & mask);
205	pci_write_config_dword(pdev, addr, reg);
206}
207
208/**
209 *	hpt3x2n_set_piomode		-	PIO setup
210 *	@ap: ATA interface
211 *	@adev: device on the interface
212 *
213 *	Perform PIO mode setup.
214 */
215
216static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
217{
218	hpt3x2n_set_mode(ap, adev, adev->pio_mode);
219}
220
221/**
222 *	hpt3x2n_set_dmamode		-	DMA timing setup
223 *	@ap: ATA interface
224 *	@adev: Device being configured
225 *
226 *	Set up the channel for MWDMA or UDMA modes.
227 */
228
229static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
230{
231	hpt3x2n_set_mode(ap, adev, adev->dma_mode);
232}
233
234/**
235 *	hpt3x2n_bmdma_stop		-	DMA engine stop
236 *	@qc: ATA command
237 *
238 *	Clean up after the HPT3x2n and later DMA engine
239 */
240
241static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
242{
243	struct ata_port *ap = qc->ap;
244	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
245	int mscreg = 0x50 + 4 * ap->port_no;
246	u8 bwsr_stat, msc_stat;
247
248	pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
249	pci_read_config_byte(pdev, mscreg, &msc_stat);
250	if (bwsr_stat & (1 << ap->port_no))
251		pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
252	ata_bmdma_stop(qc);
253}
254
255/**
256 *	hpt3x2n_set_clock	-	clock control
257 *	@ap: ATA port
258 *	@source: 0x21 or 0x23 for PLL or PCI sourced clock
259 *
260 *	Switch the ATA bus clock between the PLL and PCI clock sources
261 *	while correctly isolating the bus and resetting internal logic
262 *
263 *	We must use the DPLL for
264 *	-	writing
265 *	-	second channel UDMA7 (SATA ports) or higher
266 *	-	66MHz PCI
267 *
268 *	or we will underclock the device and get reduced performance.
269 */
270
271static void hpt3x2n_set_clock(struct ata_port *ap, int source)
272{
273	void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
274
275	/* Tristate the bus */
276	iowrite8(0x80, bmdma+0x73);
277	iowrite8(0x80, bmdma+0x77);
278
279	/* Switch clock and reset channels */
280	iowrite8(source, bmdma+0x7B);
281	iowrite8(0xC0, bmdma+0x79);
282
283	/* Reset state machines, avoid enabling the disabled channels */
284	iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
285	iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
286
287	/* Complete reset */
288	iowrite8(0x00, bmdma+0x79);
289
290	/* Reconnect channels to bus */
291	iowrite8(0x00, bmdma+0x73);
292	iowrite8(0x00, bmdma+0x77);
293}
294
295static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
296{
297	long flags = (long)ap->host->private_data;
298
299	/* See if we should use the DPLL */
300	if (writing)
301		return USE_DPLL;	/* Needed for write */
302	if (flags & PCI66)
303		return USE_DPLL;	/* Needed at 66Mhz */
304	return 0;
305}
306
307static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
308{
309	struct ata_port *ap = qc->ap;
310	struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
311	int rc, flags = (long)ap->host->private_data;
312	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
313
314	/* First apply the usual rules */
315	rc = ata_std_qc_defer(qc);
316	if (rc != 0)
317		return rc;
318
319	if ((flags & USE_DPLL) != dpll && alt->qc_active)
320		return ATA_DEFER_PORT;
321	return 0;
322}
323
324static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
325{
326	struct ata_port *ap = qc->ap;
327	int flags = (long)ap->host->private_data;
328	int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
329
330	if ((flags & USE_DPLL) != dpll) {
331		flags &= ~USE_DPLL;
332		flags |= dpll;
333		ap->host->private_data = (void *)(long)flags;
334
335		hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
336	}
337	return ata_bmdma_qc_issue(qc);
338}
339
340static const struct scsi_host_template hpt3x2n_sht = {
341	ATA_BMDMA_SHT(DRV_NAME),
342};
343
344/*
345 *	Configuration for HPT302N/371N.
346 */
347
348static struct ata_port_operations hpt3xxn_port_ops = {
349	.inherits	= &ata_bmdma_port_ops,
350
351	.bmdma_stop	= hpt3x2n_bmdma_stop,
352
353	.qc_defer	= hpt3x2n_qc_defer,
354	.qc_issue	= hpt3x2n_qc_issue,
355
356	.cable_detect	= hpt3x2n_cable_detect,
357	.set_piomode	= hpt3x2n_set_piomode,
358	.set_dmamode	= hpt3x2n_set_dmamode,
359	.prereset	= hpt3x2n_pre_reset,
360};
361
362/*
363 *	Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
364 */
365
366static struct ata_port_operations hpt372n_port_ops = {
367	.inherits	= &hpt3xxn_port_ops,
368	.mode_filter	= &hpt372n_filter,
369};
370
371/**
372 *	hpt3xn_calibrate_dpll		-	Calibrate the DPLL loop
373 *	@dev: PCI device
374 *
375 *	Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
376 *	succeeds
377 */
378
379static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
380{
381	u8 reg5b;
382	u32 reg5c;
383	int tries;
384
385	for (tries = 0; tries < 0x5000; tries++) {
386		udelay(50);
387		pci_read_config_byte(dev, 0x5b, &reg5b);
388		if (reg5b & 0x80) {
389			/* See if it stays set */
390			for (tries = 0; tries < 0x1000; tries++) {
391				pci_read_config_byte(dev, 0x5b, &reg5b);
392				/* Failed ? */
393				if ((reg5b & 0x80) == 0)
394					return 0;
395			}
396			/* Turn off tuning, we have the DPLL set */
397			pci_read_config_dword(dev, 0x5c, &reg5c);
398			pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
399			return 1;
400		}
401	}
402	/* Never went stable */
403	return 0;
404}
405
406static int hpt3x2n_pci_clock(struct pci_dev *pdev, unsigned int base)
407{
408	unsigned int freq;
409	u32 fcnt;
410
411	/*
412	 * Some devices do not let this value be accessed via PCI space
413	 * according to the old driver.
414	 */
415	fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
416	if ((fcnt >> 12) != 0xABCDE) {
417		u32 total = 0;
418		int i;
419		u16 sr;
420
421		dev_warn(&pdev->dev, "BIOS clock data not set\n");
422
423		/* This is the process the HPT371 BIOS is reported to use */
424		for (i = 0; i < 128; i++) {
425			pci_read_config_word(pdev, 0x78, &sr);
426			total += sr & 0x1FF;
427			udelay(15);
428		}
429		fcnt = total / 128;
430	}
431	fcnt &= 0x1FF;
432
433	freq = (fcnt * base) / 192;	/* in MHz */
434
435	/* Clamp to bands */
436	if (freq < 40)
437		return 33;
438	if (freq < 45)
439		return 40;
440	if (freq < 55)
441		return 50;
442	return 66;
443}
444
445/**
446 *	hpt3x2n_init_one		-	Initialise an HPT37X/302
447 *	@dev: PCI device
448 *	@id: Entry in match table
449 *
450 *	Initialise an HPT3x2n device. There are some interesting complications
451 *	here. Firstly the chip may report 366 and be one of several variants.
452 *	Secondly all the timings depend on the clock for the chip which we must
453 *	detect and look up
454 *
455 *	This is the known chip mappings. It may be missing a couple of later
456 *	releases.
457 *
458 *	Chip version		PCI		Rev	Notes
459 *	HPT372			4 (HPT366)	5	Other driver
460 *	HPT372N			4 (HPT366)	6	UDMA133
461 *	HPT372			5 (HPT372)	1	Other driver
462 *	HPT372N			5 (HPT372)	2	UDMA133
463 *	HPT302			6 (HPT302)	*	Other driver
464 *	HPT302N			6 (HPT302)	> 1	UDMA133
465 *	HPT371			7 (HPT371)	*	Other driver
466 *	HPT371N			7 (HPT371)	> 1	UDMA133
467 *	HPT374			8 (HPT374)	*	Other driver
468 *	HPT372N			9 (HPT372N)	*	UDMA133
469 *
470 *	(1) UDMA133 support depends on the bus clock
471 */
472
473static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
474{
475	/* HPT372N - UDMA133 */
476	static const struct ata_port_info info_hpt372n = {
477		.flags = ATA_FLAG_SLAVE_POSS,
478		.pio_mask = ATA_PIO4,
479		.mwdma_mask = ATA_MWDMA2,
480		.udma_mask = ATA_UDMA6,
481		.port_ops = &hpt372n_port_ops
482	};
483	/* HPT302N and HPT371N - UDMA133 */
484	static const struct ata_port_info info_hpt3xxn = {
485		.flags = ATA_FLAG_SLAVE_POSS,
486		.pio_mask = ATA_PIO4,
487		.mwdma_mask = ATA_MWDMA2,
488		.udma_mask = ATA_UDMA6,
489		.port_ops = &hpt3xxn_port_ops
490	};
491	const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
492	u8 rev = dev->revision;
493	u8 irqmask;
494	unsigned int pci_mhz;
495	unsigned int f_low, f_high;
496	int adjust;
497	unsigned long iobase = pci_resource_start(dev, 4);
498	void *hpriv = (void *)USE_DPLL;
499	int rc;
500
501	rc = pcim_enable_device(dev);
502	if (rc)
503		return rc;
504
505	switch (dev->device) {
506	case PCI_DEVICE_ID_TTI_HPT366:
507		/* 372N if rev >= 6 */
508		if (rev < 6)
509			return -ENODEV;
510		goto hpt372n;
511	case PCI_DEVICE_ID_TTI_HPT371:
512		/* 371N if rev >= 2 */
513		if (rev < 2)
514			return -ENODEV;
515		break;
516	case PCI_DEVICE_ID_TTI_HPT372:
517		/* 372N if rev >= 2 */
518		if (rev < 2)
519			return -ENODEV;
520		goto hpt372n;
521	case PCI_DEVICE_ID_TTI_HPT302:
522		/* 302N if rev >= 2 */
523		if (rev < 2)
524			return -ENODEV;
525		break;
526	case PCI_DEVICE_ID_TTI_HPT372N:
527hpt372n:
528		ppi[0] = &info_hpt372n;
529		break;
530	default:
531		dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n",
532			dev->device);
533		return -ENODEV;
534	}
535
536	/* Ok so this is a chip we support */
537
538	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
539	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
540	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
541	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
542
543	pci_read_config_byte(dev, 0x5A, &irqmask);
544	irqmask &= ~0x10;
545	pci_write_config_byte(dev, 0x5a, irqmask);
546
547	/*
548	 * HPT371 chips physically have only one channel, the secondary one,
549	 * but the primary channel registers do exist!  Go figure...
550	 * So,  we manually disable the non-existing channel here
551	 * (if the BIOS hasn't done this already).
552	 */
553	if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
554		u8 mcr1;
555		pci_read_config_byte(dev, 0x50, &mcr1);
556		mcr1 &= ~0x04;
557		pci_write_config_byte(dev, 0x50, mcr1);
558	}
559
560	/*
561	 * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
562	 * 50 for UDMA100. Right now we always use 66
563	 */
564
565	pci_mhz = hpt3x2n_pci_clock(dev, 77);
566
567	f_low = (pci_mhz * 48) / 66;	/* PCI Mhz for 66Mhz DPLL */
568	f_high = f_low + 2;		/* Tolerance */
569
570	pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
571	/* PLL clock */
572	pci_write_config_byte(dev, 0x5B, 0x21);
573
574	/* Unlike the 37x we don't try jiggling the frequency */
575	for (adjust = 0; adjust < 8; adjust++) {
576		if (hpt3xn_calibrate_dpll(dev))
577			break;
578		pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
579	}
580	if (adjust == 8) {
581		dev_err(&dev->dev, "DPLL did not stabilize!\n");
582		return -ENODEV;
583	}
584
585	dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
586
587	/*
588	 * Set our private data up. We only need a few flags
589	 * so we use it directly.
590	 */
591	if (pci_mhz > 60)
592		hpriv = (void *)(PCI66 | USE_DPLL);
593
594	/*
595	 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
596	 * the MISC. register to stretch the UltraDMA Tss timing.
597	 * NOTE: This register is only writeable via I/O space.
598	 */
599	if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
600		outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
601
602	/* Now kick off ATA set up */
603	return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
604}
605
606static const struct pci_device_id hpt3x2n[] = {
607	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
608	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
609	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
610	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
611	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
612
613	{ },
614};
615
616static struct pci_driver hpt3x2n_pci_driver = {
617	.name		= DRV_NAME,
618	.id_table	= hpt3x2n,
619	.probe		= hpt3x2n_init_one,
620	.remove		= ata_pci_remove_one
621};
622
623module_pci_driver(hpt3x2n_pci_driver);
624
625MODULE_AUTHOR("Alan Cox");
626MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
627MODULE_LICENSE("GPL");
628MODULE_DEVICE_TABLE(pci, hpt3x2n);
629MODULE_VERSION(DRV_VERSION);
630