Searched refs:bank (Results 126 - 150 of 369) sorted by path

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/linux-master/drivers/gpio/
H A Dgpio-sprd.c28 /* We have 16 banks GPIOs and each bank contain 16 GPIOs */
43 unsigned int bank)
45 return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
194 u32 bank, n; local
198 for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
199 void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
205 bank * SPRD_GPIO_BANK_NR + n);
42 sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio, unsigned int bank) argument
H A Dgpio-stmpe.c260 u8 bank = offset / 8; local
261 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
312 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
319 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
320 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
333 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
407 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : local
409 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
418 int line = bank * 8 + bit;
H A Dgpio-tegra.c63 unsigned int bank; member in struct:tegra_gpio_bank
113 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, argument
116 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
229 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; local
246 spin_lock_irqsave(&bank->dbc_lock[port], flags);
247 if (bank->dbc_cnt[port] < debounce_ms) {
249 bank->dbc_cnt[port] = debounce_ms;
251 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
304 struct tegra_gpio_bank *bank; local
309 bank
383 struct tegra_gpio_bank *bank = NULL; local
466 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; local
501 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; local
537 struct tegra_gpio_bank *bank; local
689 struct tegra_gpio_bank *bank; local
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H A Dgpio-tegra186.c72 unsigned int bank; member in struct:tegra_gpio_port
139 offset = port->bank * 0x1000 + port->port * 0x200;
154 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
642 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
644 /* skip ports that are not associated with this bank */
646 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
759 base = gpio->secure + port->bank * 0x1000 + 0x800;
838 if (gpio->soc->ports[i].bank > gpio->num_banks)
839 gpio->num_banks = gpio->soc->ports[i].bank;
943 * To simplify things, use a single interrupt per bank fo
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H A Dgpio-thunderx.c122 int bank = line / 64; local
126 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
184 int bank = line / 64; local
188 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;
260 int bank = line / 64; local
262 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
275 int bank; local
279 for (bank = 0; bank <= chip->ngpio / 64; bank
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H A Dgpio-uniphier.c35 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) argument
39 reg = (bank + 1) * 8;
52 unsigned int *bank, u32 *mask)
54 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
72 static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, argument
80 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
88 unsigned int bank; local
91 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
93 uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
100 unsigned int bank, reg_offse local
51 uniphier_gpio_get_bank_and_mask(unsigned int offset, unsigned int *bank, u32 *mask) argument
149 unsigned long i, bank, bank_mask, bank_bits; local
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H A Dgpio-xgene.c135 unsigned int bank; local
137 for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
138 bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
139 gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
148 unsigned int bank; local
150 for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank
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H A Dgpio-zynq.c93 /* Mid pin number of a bank */
142 * @bank_min: this array represents bank's min pin
143 * @bank_max: this array represents bank's max pin
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
183 * @bank_num: an output parameter used to return the bank number of the gpio
185 * @bank_pin_num: an output parameter used to return pin number within a bank
189 * Returns the bank number and pin offset within the bank.
196 int bank; local
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_aca.c31 typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);
58 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank) argument
62 if (!bank)
69 memcpy(&node->bank, bank, sizeof(*bank));
119 static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank, argument
129 idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]);
138 struct aca_bank bank; local
163 memset(&bank,
180 aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type) argument
201 aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type) argument
302 aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type) argument
316 handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data) argument
328 aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank, enum aca_smu_type type, bank_handler_t handler, void *data) argument
353 struct aca_bank *bank; local
730 aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info) argument
754 aca_bank_get_error_code(struct amdgpu_device *adev, struct aca_bank *bank) argument
765 aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size) argument
810 aca_dump_entry(struct seq_file *m, struct aca_bank *bank, enum aca_smu_type type, int idx) argument
832 handler_aca_bank_dump(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data) argument
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H A Damdgpu_aca.h117 struct aca_bank bank; member in struct:aca_bank_node
165 int (*aca_bank_parser)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data);
166 bool (*aca_bank_is_valid)(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type,
175 int (*get_valid_aca_bank)(struct amdgpu_device *adev, enum aca_smu_type type, int idx, struct aca_bank *bank);
176 int (*parse_error_code)(struct amdgpu_device *adev, struct aca_bank *bank);
198 int aca_bank_info_decode(struct aca_bank *bank, struct aca_bank_info *info);
199 int aca_bank_check_error_codes(struct amdgpu_device *adev, struct aca_bank *bank, int *err_codes, int size);
H A Damdgpu_debugfs.c57 * Bit 62: Indicates a GRBM bank switch is needed
58 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
1144 * The return data comes from the SGPR or VGPR register bank for
1153 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; local
1166 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
1184 if (bank == 0) {
H A Damdgpu_ras.c3837 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
H A Damdgpu_ras_eeprom.c497 buf[i++] = record->bank;
525 record->bank = buf[i++];
1175 record.bank,
H A Damdgpu_ras_eeprom.h124 unsigned char bank; member in union:eeprom_table_record::__anon473
H A Damdgpu_xgmi.c1038 static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, argument
1047 ret = aca_bank_info_decode(bank, &info);
1051 status = bank->regs[ACA_REG_IDX_STATUS];
1059 count = ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]);
H A Dgfx_v9_4_2.c1548 uint32_t bank, way, mem; local
1554 bank = instance / (blk->num_mem_blocks * blk->num_ways);
1561 bank, vml2_way_str[way], mem, sec_cnt, ded_cnt);
1565 vml2_walker_mems[bank], sec_cnt, ded_cnt);
1571 bank, utcl2_rounter_str[mem], sec_cnt, ded_cnt);
1577 bank, way, sec_cnt, ded_cnt);
1583 bank, way, mem, sec_cnt, ded_cnt);
1589 bank, way, mem, sec_cnt, ded_cnt);
H A Dgfx_v9_4_3.c684 struct aca_bank *bank, enum aca_smu_type type,
692 ret = aca_bank_info_decode(bank, &info);
697 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
701 misc0 = bank->regs[ACA_REG_IDX_MISC0];
719 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, argument
724 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
683 gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data) argument
H A Dmmhub_v1_8.c724 static int mmhub_v1_8_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, argument
731 ret = aca_bank_info_decode(bank, &info);
735 misc0 = bank->regs[ACA_REG_IDX_MISC0];
762 static bool mmhub_v1_8_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, argument
767 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
773 if (aca_bank_check_error_codes(handle->adev, bank,
H A Dsdma_v4_4_2.c2183 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, argument
2190 ret = aca_bank_info_decode(bank, &info);
2194 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2214 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, argument
2219 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2225 if (aca_bank_check_error_codes(handle->adev, bank,
H A Dta_ras_if.h154 uint32_t bank; member in struct:ta_ras_phy_addr
H A Dumc_v12_0.c179 uint32_t col, row, row_xor, bank, channel_index; local
193 bank = addr_out.pa.bank;
213 retired_page, row, col, bank, channel_index);
221 retired_page, row_xor, col, bank, channel_index);
231 uint32_t col, row, row_xor, bank, channel_index; local
245 bank = addr_out.pa.bank;
270 retired_page, row, col, bank, channel_index);
281 retired_page, row_xor, col, bank, channel_inde
489 umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data) argument
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c3661 u32 tmp, width, row, column, bank, density; local
3675 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3677 density = (1 << (row + column - 20 + bank)) * width;
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c2650 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
2942 /* if valid mca bank count is 0, the driver can return 0 directly */
3130 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3137 enum aca_smu_type type, int idx, struct aca_bank *bank)
3141 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3143 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3151 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank) argument
3156 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3158 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3136 aca_smu_get_valid_aca_bank(struct amdgpu_device *adev, enum aca_smu_type type, int idx, struct aca_bank *bank) argument
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_gt_irq.c32 const unsigned int bank, const unsigned int bit)
40 raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
48 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
54 bank, bit, ident);
58 raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
149 gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank) argument
157 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
160 const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
166 raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
171 unsigned int bank; local
31 gen11_gt_engine_identity(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) argument
183 gen11_gt_reset_one_iir(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) argument
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H A Dintel_gt_irq.h28 const unsigned int bank,

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