1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6 */ 7 8#include <linux/cleanup.h> 9#include <linux/init.h> 10#include <linux/platform_device.h> 11#include <linux/slab.h> 12#include <linux/gpio/driver.h> 13#include <linux/interrupt.h> 14#include <linux/of.h> 15#include <linux/mfd/stmpe.h> 16#include <linux/seq_file.h> 17#include <linux/bitops.h> 18 19/* 20 * These registers are modified under the irq bus lock and cached to avoid 21 * unnecessary writes in bus_sync_unlock. 22 */ 23enum { REG_RE, REG_FE, REG_IE }; 24 25enum { LSB, CSB, MSB }; 26 27#define CACHE_NR_REGS 3 28/* No variant has more than 24 GPIOs */ 29#define CACHE_NR_BANKS (24 / 8) 30 31struct stmpe_gpio { 32 struct gpio_chip chip; 33 struct stmpe *stmpe; 34 struct device *dev; 35 struct mutex irq_lock; 36 u32 norequest_mask; 37 /* Caches of interrupt control registers for bus_lock */ 38 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 39 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 40}; 41 42static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 43{ 44 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 45 struct stmpe *stmpe = stmpe_gpio->stmpe; 46 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; 47 u8 mask = BIT(offset % 8); 48 int ret; 49 50 ret = stmpe_reg_read(stmpe, reg); 51 if (ret < 0) 52 return ret; 53 54 return !!(ret & mask); 55} 56 57static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 58{ 59 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 60 struct stmpe *stmpe = stmpe_gpio->stmpe; 61 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 62 u8 reg = stmpe->regs[which + (offset / 8)]; 63 u8 mask = BIT(offset % 8); 64 65 /* 66 * Some variants have single register for gpio set/clear functionality. 67 * For them we need to write 0 to clear and 1 to set. 68 */ 69 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) 70 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); 71 else 72 stmpe_reg_write(stmpe, reg, mask); 73} 74 75static int stmpe_gpio_get_direction(struct gpio_chip *chip, 76 unsigned offset) 77{ 78 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 79 struct stmpe *stmpe = stmpe_gpio->stmpe; 80 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 81 u8 mask = BIT(offset % 8); 82 int ret; 83 84 ret = stmpe_reg_read(stmpe, reg); 85 if (ret < 0) 86 return ret; 87 88 if (ret & mask) 89 return GPIO_LINE_DIRECTION_OUT; 90 91 return GPIO_LINE_DIRECTION_IN; 92} 93 94static int stmpe_gpio_direction_output(struct gpio_chip *chip, 95 unsigned offset, int val) 96{ 97 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 98 struct stmpe *stmpe = stmpe_gpio->stmpe; 99 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 100 u8 mask = BIT(offset % 8); 101 102 stmpe_gpio_set(chip, offset, val); 103 104 return stmpe_set_bits(stmpe, reg, mask, mask); 105} 106 107static int stmpe_gpio_direction_input(struct gpio_chip *chip, 108 unsigned offset) 109{ 110 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 111 struct stmpe *stmpe = stmpe_gpio->stmpe; 112 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 113 u8 mask = BIT(offset % 8); 114 115 return stmpe_set_bits(stmpe, reg, mask, 0); 116} 117 118static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 119{ 120 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 121 struct stmpe *stmpe = stmpe_gpio->stmpe; 122 123 if (stmpe_gpio->norequest_mask & BIT(offset)) 124 return -EINVAL; 125 126 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); 127} 128 129static const struct gpio_chip template_chip = { 130 .label = "stmpe", 131 .owner = THIS_MODULE, 132 .get_direction = stmpe_gpio_get_direction, 133 .direction_input = stmpe_gpio_direction_input, 134 .get = stmpe_gpio_get, 135 .direction_output = stmpe_gpio_direction_output, 136 .set = stmpe_gpio_set, 137 .request = stmpe_gpio_request, 138 .can_sleep = true, 139}; 140 141static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 142{ 143 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 144 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 145 int offset = d->hwirq; 146 int regoffset = offset / 8; 147 int mask = BIT(offset % 8); 148 149 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) 150 return -EINVAL; 151 152 /* STMPE801 and STMPE 1600 don't have RE and FE registers */ 153 if (stmpe_gpio->stmpe->partnum == STMPE801 || 154 stmpe_gpio->stmpe->partnum == STMPE1600) 155 return 0; 156 157 if (type & IRQ_TYPE_EDGE_RISING) 158 stmpe_gpio->regs[REG_RE][regoffset] |= mask; 159 else 160 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 161 162 if (type & IRQ_TYPE_EDGE_FALLING) 163 stmpe_gpio->regs[REG_FE][regoffset] |= mask; 164 else 165 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 166 167 return 0; 168} 169 170static void stmpe_gpio_irq_lock(struct irq_data *d) 171{ 172 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 173 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 174 175 mutex_lock(&stmpe_gpio->irq_lock); 176} 177 178static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 179{ 180 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 181 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 182 struct stmpe *stmpe = stmpe_gpio->stmpe; 183 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 184 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { 185 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB, 186 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, 187 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB, 188 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB, 189 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, 190 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB, 191 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, 192 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, 193 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, 194 }; 195 int i, j; 196 197 /* 198 * STMPE1600: to be able to get IRQ from pins, 199 * a read must be done on GPMR register, or a write in 200 * GPSR or GPCR registers 201 */ 202 if (stmpe->partnum == STMPE1600) { 203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]); 204 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]); 205 } 206 207 for (i = 0; i < CACHE_NR_REGS; i++) { 208 /* STMPE801 and STMPE1600 don't have RE and FE registers */ 209 if ((stmpe->partnum == STMPE801 || 210 stmpe->partnum == STMPE1600) && 211 (i != REG_IE)) 212 continue; 213 214 for (j = 0; j < num_banks; j++) { 215 u8 old = stmpe_gpio->oldregs[i][j]; 216 u8 new = stmpe_gpio->regs[i][j]; 217 218 if (new == old) 219 continue; 220 221 stmpe_gpio->oldregs[i][j] = new; 222 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); 223 } 224 } 225 226 mutex_unlock(&stmpe_gpio->irq_lock); 227} 228 229static void stmpe_gpio_irq_mask(struct irq_data *d) 230{ 231 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 232 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 233 int offset = d->hwirq; 234 int regoffset = offset / 8; 235 int mask = BIT(offset % 8); 236 237 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 238 gpiochip_disable_irq(gc, offset); 239} 240 241static void stmpe_gpio_irq_unmask(struct irq_data *d) 242{ 243 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 244 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 245 int offset = d->hwirq; 246 int regoffset = offset / 8; 247 int mask = BIT(offset % 8); 248 249 gpiochip_enable_irq(gc, offset); 250 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 251} 252 253static void stmpe_dbg_show_one(struct seq_file *s, 254 struct gpio_chip *gc, 255 unsigned offset, unsigned gpio) 256{ 257 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 258 struct stmpe *stmpe = stmpe_gpio->stmpe; 259 bool val = !!stmpe_gpio_get(gc, offset); 260 u8 bank = offset / 8; 261 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; 262 u8 mask = BIT(offset % 8); 263 int ret; 264 u8 dir; 265 266 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset); 267 if (IS_ERR(label)) 268 return; 269 270 ret = stmpe_reg_read(stmpe, dir_reg); 271 if (ret < 0) 272 return; 273 dir = !!(ret & mask); 274 275 if (dir) { 276 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", 277 gpio, label ?: "(none)", 278 val ? "hi" : "lo"); 279 } else { 280 u8 edge_det_reg; 281 u8 rise_reg; 282 u8 fall_reg; 283 u8 irqen_reg; 284 285 static const char * const edge_det_values[] = { 286 "edge-inactive", 287 "edge-asserted", 288 "not-supported" 289 }; 290 static const char * const rise_values[] = { 291 "no-rising-edge-detection", 292 "rising-edge-detection", 293 "not-supported" 294 }; 295 static const char * const fall_values[] = { 296 "no-falling-edge-detection", 297 "falling-edge-detection", 298 "not-supported" 299 }; 300 #define NOT_SUPPORTED_IDX 2 301 u8 edge_det = NOT_SUPPORTED_IDX; 302 u8 rise = NOT_SUPPORTED_IDX; 303 u8 fall = NOT_SUPPORTED_IDX; 304 bool irqen; 305 306 switch (stmpe->partnum) { 307 case STMPE610: 308 case STMPE811: 309 case STMPE1601: 310 case STMPE2401: 311 case STMPE2403: 312 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; 313 ret = stmpe_reg_read(stmpe, edge_det_reg); 314 if (ret < 0) 315 return; 316 edge_det = !!(ret & mask); 317 fallthrough; 318 case STMPE1801: 319 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; 320 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; 321 322 ret = stmpe_reg_read(stmpe, rise_reg); 323 if (ret < 0) 324 return; 325 rise = !!(ret & mask); 326 ret = stmpe_reg_read(stmpe, fall_reg); 327 if (ret < 0) 328 return; 329 fall = !!(ret & mask); 330 fallthrough; 331 case STMPE801: 332 case STMPE1600: 333 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; 334 break; 335 336 default: 337 return; 338 } 339 340 ret = stmpe_reg_read(stmpe, irqen_reg); 341 if (ret < 0) 342 return; 343 irqen = !!(ret & mask); 344 345 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", 346 gpio, label ?: "(none)", 347 val ? "hi" : "lo", 348 edge_det_values[edge_det], 349 irqen ? "IRQ-enabled" : "IRQ-disabled", 350 rise_values[rise], 351 fall_values[fall]); 352 } 353} 354 355static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) 356{ 357 unsigned i; 358 unsigned gpio = gc->base; 359 360 for (i = 0; i < gc->ngpio; i++, gpio++) { 361 stmpe_dbg_show_one(s, gc, i, gpio); 362 seq_putc(s, '\n'); 363 } 364} 365 366static const struct irq_chip stmpe_gpio_irq_chip = { 367 .name = "stmpe-gpio", 368 .irq_bus_lock = stmpe_gpio_irq_lock, 369 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 370 .irq_mask = stmpe_gpio_irq_mask, 371 .irq_unmask = stmpe_gpio_irq_unmask, 372 .irq_set_type = stmpe_gpio_irq_set_type, 373 .flags = IRQCHIP_IMMUTABLE, 374 GPIOCHIP_IRQ_RESOURCE_HELPERS, 375}; 376 377#define MAX_GPIOS 24 378 379static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 380{ 381 struct stmpe_gpio *stmpe_gpio = dev; 382 struct stmpe *stmpe = stmpe_gpio->stmpe; 383 u8 statmsbreg; 384 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 385 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)]; 386 int ret; 387 int i; 388 389 /* 390 * the stmpe_block_read() call below, imposes to set statmsbreg 391 * with the register located at the lowest address. As STMPE1600 392 * variant is the only one which respect registers address's order 393 * (LSB regs located at lowest address than MSB ones) whereas all 394 * the others have a registers layout with MSB located before the 395 * LSB regs. 396 */ 397 if (stmpe->partnum == STMPE1600) 398 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; 399 else 400 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 401 402 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 403 if (ret < 0) 404 return IRQ_NONE; 405 406 for (i = 0; i < num_banks; i++) { 407 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : 408 num_banks - i - 1; 409 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 410 unsigned int stat = status[i]; 411 412 stat &= enabled; 413 if (!stat) 414 continue; 415 416 while (stat) { 417 int bit = __ffs(stat); 418 int line = bank * 8 + bit; 419 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain, 420 line); 421 422 handle_nested_irq(child_irq); 423 stat &= ~BIT(bit); 424 } 425 426 /* 427 * interrupt status register write has no effect on 428 * 801/1801/1600, bits are cleared when read. 429 * Edge detect register is not present on 801/1600/1801 430 */ 431 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 && 432 stmpe->partnum != STMPE1801) { 433 stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 434 stmpe_reg_write(stmpe, 435 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, 436 status[i]); 437 } 438 } 439 440 return IRQ_HANDLED; 441} 442 443static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, 444 unsigned long *valid_mask, 445 unsigned int ngpios) 446{ 447 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 448 int i; 449 450 if (!stmpe_gpio->norequest_mask) 451 return; 452 453 /* Forbid unused lines to be mapped as IRQs */ 454 for (i = 0; i < sizeof(u32); i++) { 455 if (stmpe_gpio->norequest_mask & BIT(i)) 456 clear_bit(i, valid_mask); 457 } 458} 459 460static void stmpe_gpio_disable(void *stmpe) 461{ 462 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 463} 464 465static int stmpe_gpio_probe(struct platform_device *pdev) 466{ 467 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 468 struct device_node *np = pdev->dev.of_node; 469 struct stmpe_gpio *stmpe_gpio; 470 int ret, irq; 471 472 if (stmpe->num_gpios > MAX_GPIOS) { 473 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n"); 474 return -EINVAL; 475 } 476 477 stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL); 478 if (!stmpe_gpio) 479 return -ENOMEM; 480 481 mutex_init(&stmpe_gpio->irq_lock); 482 483 stmpe_gpio->dev = &pdev->dev; 484 stmpe_gpio->stmpe = stmpe; 485 stmpe_gpio->chip = template_chip; 486 stmpe_gpio->chip.ngpio = stmpe->num_gpios; 487 stmpe_gpio->chip.parent = &pdev->dev; 488 stmpe_gpio->chip.base = -1; 489 490 if (IS_ENABLED(CONFIG_DEBUG_FS)) 491 stmpe_gpio->chip.dbg_show = stmpe_dbg_show; 492 493 of_property_read_u32(np, "st,norequest-mask", 494 &stmpe_gpio->norequest_mask); 495 496 irq = platform_get_irq(pdev, 0); 497 if (irq < 0) 498 dev_info(&pdev->dev, 499 "device configured in no-irq mode: " 500 "irqs are not available\n"); 501 502 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 503 if (ret) 504 return ret; 505 506 ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe); 507 if (ret) 508 return ret; 509 510 if (irq > 0) { 511 struct gpio_irq_chip *girq; 512 513 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 514 stmpe_gpio_irq, IRQF_ONESHOT, 515 "stmpe-gpio", stmpe_gpio); 516 if (ret) { 517 dev_err(&pdev->dev, "unable to get irq: %d\n", ret); 518 return ret; 519 } 520 521 girq = &stmpe_gpio->chip.irq; 522 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip); 523 /* This will let us handle the parent IRQ in the driver */ 524 girq->parent_handler = NULL; 525 girq->num_parents = 0; 526 girq->parents = NULL; 527 girq->default_type = IRQ_TYPE_NONE; 528 girq->handler = handle_simple_irq; 529 girq->threaded = true; 530 girq->init_valid_mask = stmpe_init_irq_valid_mask; 531 } 532 533 return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio); 534} 535 536static struct platform_driver stmpe_gpio_driver = { 537 .driver = { 538 .suppress_bind_attrs = true, 539 .name = "stmpe-gpio", 540 }, 541 .probe = stmpe_gpio_probe, 542}; 543 544static int __init stmpe_gpio_init(void) 545{ 546 return platform_driver_register(&stmpe_gpio_driver); 547} 548subsys_initcall(stmpe_gpio_init); 549