Searched refs:cache (Results 151 - 175 of 359) sorted by relevance

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/u-boot/board/hisilicon/poplar/
H A Dpoplar.c11 #include <asm/cache.h>
/u-boot/board/freescale/t4rdb/
H A Dt4240rdb.c19 #include <asm/cache.h>
74 /* Flush d-cache and invalidate i-cache of any FLASH data */
H A Deth.c15 #include <asm/cache.h>
/u-boot/lib/
H A Dbch.c773 rep = bch->cache;
860 gf_poly_logrep(bch, f, bch->cache);
875 gf_poly_mod(bch, z, f, bch->cache);
971 gf_poly_logrep(bch, p, bch->cache);
972 bch->cache[p->deg] = 0;
978 m = bch->cache[j];
1354 bch->cache = bch_alloc(2*t*sizeof(*bch->cache), &err);
1402 kfree(bch->cache);
/u-boot/arch/arm/mach-omap2/omap5/
H A Dsec_entry_cpu1.S86 blx flush_dcache_range @ flush the cache on args buffer
/u-boot/arch/xtensa/include/asm/
H A Dcacheasm.h10 #include <asm/cache.h>
21 * Define cache functions as macros here so that they can be used
/u-boot/arch/x86/cpu/intel_common/
H A Dcar2.S191 /* Disable cache eviction (setup stage) */
199 /* Clear the cache memory region. This will also fill up the cache */
209 /* Disable cache eviction (run stage) */
242 * prefetchers slow down filling cache with rep stos in CQOS mode.
254 #error "CQOS CAR may not use whole L2 cache area"
267 /* Set this mask for initial cache fill */
282 /* Invert bits that are to be used for cache */
296 /* Clear the cache memory region. This will also fill up the cache */
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/u-boot/include/
H A Ddwmmc.h10 #include <asm/cache.h>
H A Dfat.h14 #include <asm/cache.h>
/u-boot/arch/arm/mach-npcm/npcm7xx/
H A Dl2_cache_pl310_init.S31 ORR r1, r1, #(1 << 22) @ cache replacement policy
/u-boot/fs/btrfs/
H A Dextent-io.h11 * As we don't cache eb in U-Boot.
25 #include "extent-cache.h"
68 struct cache_tree cache; member in struct:extent_io_tree
/u-boot/arch/mips/lib/
H A Dcache.c9 #include <asm/cache.h>
122 /* flush I-cache & D-cache simultaneously */
128 /* flush D-cache */
131 /* flush L2 cache */
134 /* flush I-cache */
138 /* ensure cache ops complete before any further memory accesses */
156 /* flush L2 cache */
159 /* ensure cache ops complete before any further memory accesses */
172 /* invalidate L2 cache */
[all...]
/u-boot/drivers/net/
H A Ddesignware.h10 #include <asm/cache.h>
/u-boot/arch/arm/mach-keystone/
H A Dinit.c12 #include <asm/cache.h>
211 /* Enable D-cache. I-cache is already enabled in start.S */
/u-boot/arch/arm/cpu/armv7/
H A Dstart.S133 * If I-cache is enabled invalidate it
197 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
206 * "any cache or TLB maintenance operations are performed".
232 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
234 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
317 @ lines allocate in the L1 or L2 cache.
319 @ lines allocate in the L1 cache.
/u-boot/drivers/crypto/fsl/
H A Dfsl_blob.c13 #include <asm/cache.h>
27 * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
99 * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
H A Ddcp_rng.c14 #include <asm/cache.h>
/u-boot/drivers/firmware/scmi/
H A Dsmt.c15 #include <asm/cache.h>
/u-boot/arch/arm/mach-kirkwood/
H A Dcpu.c16 #include <asm/cache.h>
192 /* Enable and invalidate L2 cache in write through mode */
/u-boot/arch/arm/mach-socfpga/
H A Dmisc.c10 #include <asm/cache.h>
76 pr_err("cache controller driver NOT found!\n");
81 /* Disable the L2 cache */
91 /* Disable the L2 cache */
103 /* Enable the L2 cache */
108 * Invalidate the PL310 L2 cache. Keep the invalidation code
109 * entirely in L1 I-cache to avoid any bus traffic through
135 /* Disable the L2 cache */
/u-boot/drivers/usb/eth/
H A Dusb_ether.c13 #include <asm/cache.h>
/u-boot/arch/xtensa/lib/
H A Dbootm.c18 #include <asm/cache.h>
/u-boot/arch/arm/mach-tegra/
H A Dboard.c14 #include <asm/cache.h>
273 /* Enable D-cache. I-cache is already enabled in start.S */
/u-boot/board/freescale/p2041rdb/
H A Dp2041rdb.c18 #include <asm/cache.h>
130 /* Flush d-cache and invalidate i-cache of any FLASH data */
/u-boot/board/hisilicon/hikey960/
H A Dhikey960.c11 #include <asm/cache.h>

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