1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2021 Nuvoton Technology Corp.
4 */
5
6.align 5
7
8#include <linux/linkage.h>
9
10#ifndef CONFIG_SYS_L2CACHE_OFF
11
12ENTRY(l2_pl310_init)
13
14@------------------------------------------------------------------
15@ L2CC (PL310) Initialization
16@------------------------------------------------------------------
17	@ In this example PL310 PA = VA. The memory was marked as Device memory
18	@ in previous stages when defining CORE0 private address space
19	LDR     r0, =0xF03FC000        @ A9_BASE_ADDR
20
21	@ Disable L2 Cache controller just in case it is already on
22	LDR     r1, =0x0
23	STR     r1, [r0,#0x100]
24
25	@ Set aux cntrl
26	@ Way size = 32KB
27	@ Way = 16
28	LDR     r1, =0x02050000
29	ORR	r1, r1, #(1 << 29)	@ Instruction prefetch enable
30	ORR	r1, r1, #(1 << 28)	@ Data prefetch enable
31	ORR	r1, r1, #(1 << 22)	@ cache replacement policy
32	STR     r1, [r0,#0x104]		@ auxilary control reg at offset 0x104
33
34	@ Set tag RAM latency
35	@ 1 cycle RAM write access latency
36	@ 1 cycle RAM read access latency
37	@ 1 cycle RAM setup latency
38	LDR     r1, =0x00000000
39	STR     r1, [r0,#0x108]		@ tag ram control reg at offset 0x108
40
41	@ Set Data RAM latency
42	@ 1 cycle RAM write access latency
43	@ 2 cycles RAM read access latency
44	@ 1 cycle RAM setup latency
45	LDR     r1, =0x00000000
46	STR     r1, [r0,#0x10C]		@ data ram control reg at offset 0x108
47
48	@Cache maintenance - invalidate 16 ways (0xffff) - base offset 0x77C
49	LDR     r1, =0xFFFF
50	STR     r1, [r0,#0x77C]		@ invalidate by way register at offset 0x77C
51poll_invalidate:
52	LDR     r1, [r0,#0x77C]		@ invalidate by way register at offset 0x77C
53	TST     r1, #1
54	BNE     poll_invalidate
55
56	@ Ensure L2 remains disabled for the time being
57	LDR     r1, =0x0
58	STR     r1, [r0,#0x100]
59
60	MRC     p15, 4, r0, c15, c0, 0     @ Read periph base address
61	@ SCU offset from base of private peripheral space = 0x000
62
63	LDR     r1, [r0, #0x0]             @ Read the SCU Control Register
64	ORR     r1, r1, #0x1               @ Set bit 0 (The Enable bit)
65	STR     r1, [r0, #0x0]             @ Write back modifed value
66
67	BX	lr
68
69ENDPROC(l2_pl310_init)
70
71#endif
72