1// SPDX-License-Identifier: GPL-2.0+
2/*
3 *  (C) Copyright 2010-2015
4 *  NVIDIA Corporation <www.nvidia.com>
5 */
6
7#include <common.h>
8#include <cpu_func.h>
9#include <dm.h>
10#include <init.h>
11#include <log.h>
12#include <ns16550.h>
13#include <spl.h>
14#include <asm/cache.h>
15#include <asm/global_data.h>
16#include <asm/io.h>
17#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
18#include <asm/arch/clock.h>
19#endif
20#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
21#include <asm/arch/funcmux.h>
22#endif
23#if IS_ENABLED(CONFIG_TEGRA_MC)
24#include <asm/arch/mc.h>
25#endif
26#include <asm/arch/tegra.h>
27#include <asm/arch-tegra/ap.h>
28#include <asm/arch-tegra/board.h>
29#include <asm/arch-tegra/cboot.h>
30#include <asm/arch-tegra/pmc.h>
31#include <asm/arch-tegra/sys_proto.h>
32#include <asm/arch-tegra/warmboot.h>
33
34void save_boot_params_ret(void);
35
36DECLARE_GLOBAL_DATA_PTR;
37
38enum {
39	/* UARTs which we can enable */
40	UARTA	= 1 << 0,
41	UARTB	= 1 << 1,
42	UARTC	= 1 << 2,
43	UARTD	= 1 << 3,
44	UARTE	= 1 << 4,
45	UART_COUNT = 5,
46};
47
48static bool from_spl __section(".data");
49
50#ifndef CONFIG_SPL_BUILD
51void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
52		      unsigned long r3)
53{
54	from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
55
56	/*
57	 * The logic for this is somewhat indirect. The purpose of the marker
58	 * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
59	 * was loaded from a read-only instance of itself, which is something
60	 * that can happen in secure boot setups. So basically the presence
61	 * of the marker is an indication that U-Boot was loaded by one such
62	 * special variant of U-Boot. Conversely, the absence of the marker
63	 * indicates that this instance of U-Boot was loaded by something
64	 * other than a special U-Boot. This could be SPL, but it could just
65	 * as well be one of any number of other first stage bootloaders.
66	 */
67	if (from_spl)
68		cboot_save_boot_params(r0, r1, r2, r3);
69
70	save_boot_params_ret();
71}
72#endif
73
74bool spl_was_boot_source(void)
75{
76	return from_spl;
77}
78
79#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
80bool tegra_cpu_is_non_secure(void)
81{
82	/*
83	 * This register reads 0xffffffff in non-secure mode. This register
84	 * only implements bits 31:20, so the lower bits will always read 0 in
85	 * secure mode. Thus, the lower bits are an indicator for secure vs.
86	 * non-secure mode.
87	 */
88	struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
89	uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
90	return (mc_s_cfg0 & 1) == 1;
91}
92#endif
93
94#if IS_ENABLED(CONFIG_TEGRA_MC)
95/* Read the RAM size directly from the memory controller */
96static phys_size_t query_sdram_size(void)
97{
98	struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
99	u32 emem_cfg;
100	phys_size_t size_bytes;
101
102	emem_cfg = readl(&mc->mc_emem_cfg);
103#if defined(CONFIG_TEGRA20)
104	debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
105	size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
106#else
107	debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
108#ifndef CONFIG_PHYS_64BIT
109	/*
110	 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
111	 * and will wrap. Clip the reported size to the maximum that a 32-bit
112	 * variable can represent (rounded to a page).
113	 */
114	if (emem_cfg >= 4096) {
115		size_bytes = U32_MAX & ~(0x1000 - 1);
116	} else
117#endif
118	{
119		/* RAM size EMC is programmed to. */
120		size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
121#ifndef CONFIG_ARM64
122		/*
123		 * If all RAM fits within 32-bits, it can be accessed without
124		 * LPAE, so go test the RAM size. Otherwise, we can't access
125		 * all the RAM, and get_ram_size() would get confused, so
126		 * avoid using it. There's no reason we should need this
127		 * validation step anyway.
128		 */
129		if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
130			size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
131						  size_bytes);
132#endif
133	}
134#endif
135
136#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
137	/* External memory limited to 2047 MB due to IROM/HI-VEC */
138	if (size_bytes == SZ_2G)
139		size_bytes -= SZ_1M;
140#endif
141
142	return size_bytes;
143}
144#endif
145
146int dram_init(void)
147{
148	int err;
149
150	/* try to initialize DRAM from cboot DTB first */
151	err = cboot_dram_init();
152	if (err == 0)
153		return 0;
154
155#if IS_ENABLED(CONFIG_TEGRA_MC)
156	/* We do not initialise DRAM here. We just query the size */
157	gd->ram_size = query_sdram_size();
158#endif
159
160	return 0;
161}
162
163#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
164static int uart_configs[] = {
165#if defined(CONFIG_TEGRA20)
166 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
167	FUNCMUX_UART1_UAA_UAB,
168 #elif defined(CONFIG_TEGRA_UARTA_GPU)
169	FUNCMUX_UART1_GPU,
170 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
171	FUNCMUX_UART1_SDIO1,
172 #else
173	FUNCMUX_UART1_IRRX_IRTX,
174#endif
175	FUNCMUX_UART2_UAD,
176	-1,
177	FUNCMUX_UART4_GMC,
178	-1,
179#elif defined(CONFIG_TEGRA30)
180	FUNCMUX_UART1_ULPI,	/* UARTA */
181	-1,
182	-1,
183	-1,
184	-1,
185#elif defined(CONFIG_TEGRA114)
186	-1,
187	-1,
188	-1,
189	FUNCMUX_UART4_GMI,	/* UARTD */
190	-1,
191#elif defined(CONFIG_TEGRA124)
192	FUNCMUX_UART1_KBC,	/* UARTA */
193	-1,
194	-1,
195	FUNCMUX_UART4_GPIO,	/* UARTD */
196	-1,
197#else	/* Tegra210 */
198	FUNCMUX_UART1_UART1,	/* UARTA */
199	-1,
200	-1,
201	FUNCMUX_UART4_UART4,	/* UARTD */
202	-1,
203#endif
204};
205
206/**
207 * Set up the specified uarts
208 *
209 * @param uarts_ids	Mask containing UARTs to init (UARTx)
210 */
211static void setup_uarts(int uart_ids)
212{
213	static enum periph_id id_for_uart[] = {
214		PERIPH_ID_UART1,
215		PERIPH_ID_UART2,
216		PERIPH_ID_UART3,
217		PERIPH_ID_UART4,
218		PERIPH_ID_UART5,
219	};
220	size_t i;
221
222	for (i = 0; i < UART_COUNT; i++) {
223		if (uart_ids & (1 << i)) {
224			enum periph_id id = id_for_uart[i];
225
226			funcmux_select(id, uart_configs[i]);
227			clock_ll_start_uart(id);
228		}
229	}
230}
231#endif
232
233void board_init_uart_f(void)
234{
235#if CONFIG_IS_ENABLED(PINCTRL_TEGRA)
236	int uart_ids = 0;	/* bit mask of which UART ids to enable */
237
238#ifdef CONFIG_TEGRA_ENABLE_UARTA
239	uart_ids |= UARTA;
240#endif
241#ifdef CONFIG_TEGRA_ENABLE_UARTB
242	uart_ids |= UARTB;
243#endif
244#ifdef CONFIG_TEGRA_ENABLE_UARTC
245	uart_ids |= UARTC;
246#endif
247#ifdef CONFIG_TEGRA_ENABLE_UARTD
248	uart_ids |= UARTD;
249#endif
250#ifdef CONFIG_TEGRA_ENABLE_UARTE
251	uart_ids |= UARTE;
252#endif
253	setup_uarts(uart_ids);
254#endif
255}
256
257#if !CONFIG_IS_ENABLED(OF_CONTROL)
258static struct ns16550_plat ns16550_com1_pdata = {
259	.base = CFG_SYS_NS16550_COM1,
260	.reg_shift = 2,
261	.clock = CFG_SYS_NS16550_CLK,
262	.fcr = UART_FCR_DEFVAL,
263};
264
265U_BOOT_DRVINFO(ns16550_com1) = {
266	"ns16550_serial", &ns16550_com1_pdata
267};
268#endif
269
270#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
271void enable_caches(void)
272{
273	/* Enable D-cache. I-cache is already enabled in start.S */
274	dcache_enable();
275}
276#endif
277