1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2011,2012 Freescale Semiconductor, Inc. 4 */ 5 6#include <common.h> 7#include <clock_legacy.h> 8#include <command.h> 9#include <env.h> 10#include <fdt_support.h> 11#include <image.h> 12#include <init.h> 13#include <netdev.h> 14#include <asm/global_data.h> 15#include <linux/compiler.h> 16#include <asm/mmu.h> 17#include <asm/processor.h> 18#include <asm/cache.h> 19#include <asm/immap_85xx.h> 20#include <asm/fsl_law.h> 21#include <asm/fsl_serdes.h> 22#include <asm/fsl_liodn.h> 23#include <fm_eth.h> 24 25extern void pci_of_setup(void *blob, struct bd_info *bd); 26 27#include "cpld.h" 28 29DECLARE_GLOBAL_DATA_PTR; 30 31int checkboard(void) 32{ 33 u8 sw; 34 struct cpu_type *cpu = gd->arch.cpu; 35 unsigned int i; 36 37 printf("Board: %sRDB, ", cpu->name); 38 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), 39 CPLD_READ(cpld_ver_sub)); 40 41 sw = CPLD_READ(fbank_sel); 42 printf("vBank: %d\n", sw & 0x1); 43 44 /* 45 * Display the actual SERDES reference clocks as configured by the 46 * dip switches on the board. Note that the SWx registers could 47 * technically be set to force the reference clocks to match the 48 * values that the SERDES expects (or vice versa). For now, however, 49 * we just display both values and hope the user notices when they 50 * don't match. 51 */ 52 puts("SERDES Reference Clocks: "); 53 sw = in_8(&CPLD_SW(2)) >> 2; 54 for (i = 0; i < 2; i++) { 55 static const char * const freq[][3] = {{"0", "100", "125"}, 56 {"100", "156.25", "125"} 57 }; 58 unsigned int clock = (sw >> (2 * i)) & 3; 59 60 printf("Bank%u=%sMhz ", i+1, freq[i][clock]); 61 } 62 puts("\n"); 63 64 return 0; 65} 66 67int board_early_init_f(void) 68{ 69 ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); 70 71 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ 72 setbits_be32(&gur->ddrclkdr, 0x000f000f); 73 74 return 0; 75} 76 77#define CPLD_LANE_A_SEL 0x1 78#define CPLD_LANE_G_SEL 0x2 79#define CPLD_LANE_C_SEL 0x4 80#define CPLD_LANE_D_SEL 0x8 81 82void board_config_lanes_mux(void) 83{ 84 ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; 85 int srds_prtcl = (in_be32(&gur->rcwsr[4]) & 86 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; 87 88 u8 mux = 0; 89 switch (srds_prtcl) { 90 case 0x2: 91 case 0x5: 92 case 0x9: 93 case 0xa: 94 case 0xf: 95 break; 96 case 0x8: 97 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; 98 break; 99 case 0x14: 100 mux |= CPLD_LANE_A_SEL; 101 break; 102 case 0x17: 103 mux |= CPLD_LANE_G_SEL; 104 break; 105 case 0x16: 106 case 0x19: 107 case 0x1a: 108 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; 109 break; 110 case 0x1c: 111 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL; 112 break; 113 default: 114 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl); 115 break; 116 } 117 CPLD_WRITE(serdes_mux, mux); 118} 119 120int board_early_init_r(void) 121{ 122 const unsigned int flashbase = CFG_SYS_FLASH_BASE; 123 int flash_esel = find_tlb_idx((void *)flashbase, 1); 124 125 /* 126 * Remap Boot flash + PROMJET region to caching-inhibited 127 * so that flash can be erased properly. 128 */ 129 130 /* Flush d-cache and invalidate i-cache of any FLASH data */ 131 flush_dcache(); 132 invalidate_icache(); 133 134 if (flash_esel == -1) { 135 /* very unlikely unless something is messed up */ 136 puts("Error: Could not find TLB for FLASH BASE\n"); 137 flash_esel = 2; /* give our best effort to continue */ 138 } else { 139 /* invalidate existing TLB entry for flash + promjet */ 140 disable_tlb(flash_esel); 141 } 142 143 set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, 144 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 145 0, flash_esel, BOOKE_PAGESZ_256M, 1); 146 147 board_config_lanes_mux(); 148 149 return 0; 150} 151 152unsigned long get_board_sys_clk(void) 153{ 154 u8 sysclk_conf = CPLD_READ(sysclk_sw1); 155 156 switch (sysclk_conf & 0x7) { 157 case CPLD_SYSCLK_83: 158 return 83333333; 159 case CPLD_SYSCLK_100: 160 return 100000000; 161 default: 162 return 66666666; 163 } 164} 165 166#define NUM_SRDS_BANKS 2 167 168int misc_init_r(void) 169{ 170 serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; 171 u32 actual[NUM_SRDS_BANKS]; 172 unsigned int i; 173 u8 sw; 174 static const int freq[][3] = { 175 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, 176 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25, 177 SRDS_PLLCR0_RFCK_SEL_125} 178 }; 179 180 sw = in_8(&CPLD_SW(2)) >> 2; 181 for (i = 0; i < NUM_SRDS_BANKS; i++) { 182 unsigned int clock = (sw >> (2 * i)) & 3; 183 if (clock == 0x3) { 184 printf("Warning: SDREFCLK%u switch setting of '11' is " 185 "unsupported\n", i + 1); 186 break; 187 } 188 if (i == 0 && clock == 0) 189 puts("Warning: SDREFCLK1 switch setting of" 190 "'00' is unsupported\n"); 191 else 192 actual[i] = freq[i][clock]; 193 194 /* 195 * PC board uses a different CPLD with PB board, this CPLD 196 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB 197 * board has cpld_ver_sub = 0, and pcba_ver = 4. 198 */ 199 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && 200 (CPLD_READ(pcba_ver) == 5)) { 201 /* PC board bank2 frequency */ 202 actual[i] = freq[i-1][clock]; 203 } 204 } 205 206 for (i = 0; i < NUM_SRDS_BANKS; i++) { 207 u32 expected = in_be32(®s->bank[i].pllcr0); 208 expected &= SRDS_PLLCR0_RFCK_SEL_MASK; 209 if (expected != actual[i]) { 210 printf("Warning: SERDES bank %u expects reference clock" 211 " %sMHz, but actual is %sMHz\n", i + 1, 212 serdes_clock_to_string(expected), 213 serdes_clock_to_string(actual[i])); 214 } 215 } 216 217 return 0; 218} 219 220int ft_board_setup(void *blob, struct bd_info *bd) 221{ 222 phys_addr_t base; 223 phys_size_t size; 224 225 ft_cpu_setup(blob, bd); 226 227 base = env_get_bootm_low(); 228 size = env_get_bootm_size(); 229 230 fdt_fixup_memory(blob, (u64)base, (u64)size); 231 232#if defined(CONFIG_HAS_FSL_DR_USB) 233 fsl_fdt_fixup_dr_usb(blob, bd); 234#endif 235 236#ifdef CONFIG_PCI 237 pci_of_setup(blob, bd); 238#endif 239 240 fdt_fixup_liodn(blob); 241#ifdef CONFIG_SYS_DPAA_FMAN 242#ifndef CONFIG_DM_ETH 243 fdt_fixup_fman_ethernet(blob); 244#endif 245#endif 246 247 return 0; 248} 249