1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Keystone2: Architecture initialization 4 * 5 * (C) Copyright 2012-2014 6 * Texas Instruments Incorporated, <www.ti.com> 7 */ 8 9#include <cpu_func.h> 10#include <init.h> 11#include <ns16550.h> 12#include <asm/cache.h> 13#include <asm/io.h> 14#include <asm/arch/msmc.h> 15#include <asm/arch/clock.h> 16#include <asm/arch/hardware.h> 17#include <asm/arch/psc_defs.h> 18#include <linux/bitops.h> 19 20#define MAX_PCI_PORTS 2 21enum pci_mode { 22 ENDPOINT, 23 LEGACY_ENDPOINT, 24 ROOTCOMPLEX, 25}; 26 27#define DEVCFG_MODE_MASK (BIT(2) | BIT(1)) 28#define DEVCFG_MODE_SHIFT 1 29 30void chip_configuration_unlock(void) 31{ 32 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); 33 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); 34} 35 36#ifdef CONFIG_SOC_K2L 37void osr_init(void) 38{ 39 u32 i; 40 u32 j; 41 u32 val; 42 u32 base = KS2_OSR_CFG_BASE; 43 u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS]; 44 45 /* Enable the OSR clock domain */ 46 psc_enable_module(KS2_LPSC_OSR); 47 48 /* Disable OSR ECC check for all the ram banks */ 49 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) { 50 val = i | KS2_OSR_ECC_VEC_TRIG_RD | 51 (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH); 52 53 writel(val , base + KS2_OSR_ECC_VEC); 54 55 /** 56 * wait till read is done. 57 * Print should be added after earlyprintk support is added. 58 */ 59 for (j = 0; j < 10000; j++) { 60 val = readl(base + KS2_OSR_ECC_VEC); 61 if (val & KS2_OSR_ECC_VEC_RD_DONE) 62 break; 63 } 64 65 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^ 66 KS2_OSR_ECC_CTRL_CHK; 67 68 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4); 69 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL); 70 } 71 72 /* Reset OSR memory to all zeros */ 73 for (i = 0; i < KS2_OSR_SIZE; i += 4) 74 writel(0, KS2_OSR_DATA_BASE + i); 75 76 /* Enable OSR ECC check for all the ram banks */ 77 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) 78 writel(ecc_ctrl[i] | 79 KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL); 80} 81#endif 82 83/* Function to set up PCIe mode */ 84static void config_pcie_mode(int pcie_port, enum pci_mode mode) 85{ 86 u32 val = __raw_readl(KS2_DEVCFG); 87 88 if (pcie_port >= MAX_PCI_PORTS) 89 return; 90 91 /** 92 * each pci port has two bits for mode and it starts at 93 * bit 1. So use port number to get the right bit position. 94 */ 95 pcie_port <<= 1; 96 val &= ~(DEVCFG_MODE_MASK << pcie_port); 97 val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port); 98 __raw_writel(val, KS2_DEVCFG); 99} 100 101static void msmc_k2hkle_common_setup(void) 102{ 103 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0); 104 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM); 105 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP); 106 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP); 107 msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0); 108 msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG); 109} 110 111static void msmc_k2hk_setup(void) 112{ 113 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1); 114 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2); 115 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3); 116 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4); 117 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5); 118 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6); 119 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7); 120 msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK); 121} 122 123static inline void msmc_k2l_setup(void) 124{ 125 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1); 126 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2); 127 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3); 128 msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1); 129} 130 131static inline void msmc_k2e_setup(void) 132{ 133 msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1); 134 msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK); 135 msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP); 136} 137 138static void msmc_k2g_setup(void) 139{ 140 msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0); 141 msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM); 142 msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0); 143 msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1); 144 msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS); 145 msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE); 146 msmc_share_all_segments(K2G_MSMC_SEGMENT_USB); 147 msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB); 148 msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC); 149 msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS); 150 msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC); 151 msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG); 152} 153 154int arch_cpu_init(void) 155{ 156 chip_configuration_unlock(); 157 icache_enable(); 158 159 if (cpu_is_k2g()) { 160 msmc_k2g_setup(); 161 } else { 162 msmc_k2hkle_common_setup(); 163 if (cpu_is_k2e()) 164 msmc_k2e_setup(); 165 else if (cpu_is_k2l()) 166 msmc_k2l_setup(); 167 else 168 msmc_k2hk_setup(); 169 } 170 171 /* Initialize the PCIe-0 to work as Root Complex */ 172 config_pcie_mode(0, ROOTCOMPLEX); 173#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) 174 /* Initialize the PCIe-1 to work as Root Complex */ 175 config_pcie_mode(1, ROOTCOMPLEX); 176#endif 177#ifdef CONFIG_SOC_K2L 178 osr_init(); 179#endif 180 181 /* 182 * just initialise the COM2 port so that TI specific 183 * UART register PWREMU_MGMT is initialized. Linux UART 184 * driver doesn't handle this. 185 */ 186#ifndef CONFIG_DM_SERIAL 187 ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2), 188 CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); 189#endif 190 191 return 0; 192} 193 194void reset_cpu(void) 195{ 196 volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); 197 u32 tmp; 198 199 tmp = *rstctrl & KS2_RSTCTRL_MASK; 200 *rstctrl = tmp | KS2_RSTCTRL_KEY; 201 202 *rstctrl &= KS2_RSTCTRL_SWRST; 203 204 for (;;) 205 ; 206} 207 208void enable_caches(void) 209{ 210#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) 211 /* Enable D-cache. I-cache is already enabled in start.S */ 212 dcache_enable(); 213#endif 214} 215 216#if defined(CONFIG_DISPLAY_CPUINFO) 217int print_cpuinfo(void) 218{ 219 u16 cpu = get_part_number(); 220 u8 rev = cpu_revision(); 221 222 puts("CPU: "); 223 switch (cpu) { 224 case CPU_66AK2Hx: 225 puts("66AK2Hx SR"); 226 break; 227 case CPU_66AK2Lx: 228 puts("66AK2Lx SR"); 229 break; 230 case CPU_66AK2Ex: 231 puts("66AK2Ex SR"); 232 break; 233 case CPU_66AK2Gx: 234 puts("66AK2Gx"); 235#ifdef CONFIG_SOC_K2G 236 { 237 int speed = get_max_arm_speed(speeds); 238 if (speed == SPD1000) 239 puts("-100 "); 240 else if (speed == SPD600) 241 puts("-60 "); 242 else 243 puts("-xx "); 244 } 245#endif 246 puts("SR"); 247 break; 248 default: 249 puts("Unknown\n"); 250 } 251 252 if (rev == 2) 253 puts("2.0\n"); 254 else if (rev == 1) 255 puts("1.1\n"); 256 else if (rev == 0) 257 puts("1.0\n"); 258 else if (rev == 8) 259 puts("1.0\n"); 260 return 0; 261} 262#endif 263