1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 */
6
7#ifndef __DWMMC_HW_H
8#define __DWMMC_HW_H
9
10#include <asm/cache.h>
11#include <asm/io.h>
12#include <mmc.h>
13#include <linux/bitops.h>
14
15#define DWMCI_CTRL		0x000
16#define	DWMCI_PWREN		0x004
17#define DWMCI_CLKDIV		0x008
18#define DWMCI_CLKSRC		0x00C
19#define DWMCI_CLKENA		0x010
20#define DWMCI_TMOUT		0x014
21#define DWMCI_CTYPE		0x018
22#define DWMCI_BLKSIZ		0x01C
23#define DWMCI_BYTCNT		0x020
24#define DWMCI_INTMASK		0x024
25#define DWMCI_CMDARG		0x028
26#define DWMCI_CMD		0x02C
27#define DWMCI_RESP0		0x030
28#define DWMCI_RESP1		0x034
29#define DWMCI_RESP2		0x038
30#define DWMCI_RESP3		0x03C
31#define DWMCI_MINTSTS		0x040
32#define DWMCI_RINTSTS		0x044
33#define DWMCI_STATUS		0x048
34#define DWMCI_FIFOTH		0x04C
35#define DWMCI_CDETECT		0x050
36#define DWMCI_WRTPRT		0x054
37#define DWMCI_GPIO		0x058
38#define DWMCI_TCMCNT		0x05C
39#define DWMCI_TBBCNT		0x060
40#define DWMCI_DEBNCE		0x064
41#define DWMCI_USRID		0x068
42#define DWMCI_VERID		0x06C
43#define DWMCI_HCON		0x070
44#define DWMCI_UHS_REG		0x074
45#define DWMCI_BMOD		0x080
46#define DWMCI_PLDMND		0x084
47#define DWMCI_DBADDR		0x088
48#define DWMCI_IDSTS		0x08C
49#define DWMCI_IDINTEN		0x090
50#define DWMCI_DSCADDR		0x094
51#define DWMCI_BUFADDR		0x098
52#define DWMCI_DATA		0x200
53
54/* Interrupt Mask register */
55#define DWMCI_INTMSK_ALL	0xffffffff
56#define DWMCI_INTMSK_RE		(1 << 1)
57#define DWMCI_INTMSK_CDONE	(1 << 2)
58#define DWMCI_INTMSK_DTO	(1 << 3)
59#define DWMCI_INTMSK_TXDR	(1 << 4)
60#define DWMCI_INTMSK_RXDR	(1 << 5)
61#define DWMCI_INTMSK_RCRC	(1 << 6)
62#define DWMCI_INTMSK_DCRC	(1 << 7)
63#define DWMCI_INTMSK_RTO	(1 << 8)
64#define DWMCI_INTMSK_DRTO	(1 << 9)
65#define DWMCI_INTMSK_HTO	(1 << 10)
66#define DWMCI_INTMSK_FRUN	(1 << 11)
67#define DWMCI_INTMSK_HLE	(1 << 12)
68#define DWMCI_INTMSK_SBE	(1 << 13)
69#define DWMCI_INTMSK_ACD	(1 << 14)
70#define DWMCI_INTMSK_EBE	(1 << 15)
71
72/* Raw interrupt Regsiter */
73#define DWMCI_DATA_ERR	(DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
74			DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
75#define DWMCI_DATA_TOUT	(DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
76/* CTRL register */
77#define DWMCI_CTRL_RESET	(1 << 0)
78#define DWMCI_CTRL_FIFO_RESET	(1 << 1)
79#define DWMCI_CTRL_DMA_RESET	(1 << 2)
80#define DWMCI_DMA_EN		(1 << 5)
81#define DWMCI_CTRL_SEND_AS_CCSD	(1 << 10)
82#define DWMCI_IDMAC_EN		(1 << 25)
83#define DWMCI_RESET_ALL		(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
84				DWMCI_CTRL_DMA_RESET)
85
86/* CMD register */
87#define DWMCI_CMD_RESP_EXP	(1 << 6)
88#define DWMCI_CMD_RESP_LENGTH	(1 << 7)
89#define DWMCI_CMD_CHECK_CRC	(1 << 8)
90#define DWMCI_CMD_DATA_EXP	(1 << 9)
91#define DWMCI_CMD_RW		(1 << 10)
92#define DWMCI_CMD_SEND_STOP	(1 << 12)
93#define DWMCI_CMD_ABORT_STOP	(1 << 14)
94#define DWMCI_CMD_PRV_DAT_WAIT	(1 << 13)
95#define DWMCI_CMD_UPD_CLK	(1 << 21)
96#define DWMCI_CMD_USE_HOLD_REG	(1 << 29)
97#define DWMCI_CMD_START		(1 << 31)
98
99/* CLKENA register */
100#define DWMCI_CLKEN_ENABLE	(1 << 0)
101#define DWMCI_CLKEN_LOW_PWR	(1 << 16)
102
103/* Card-type registe */
104#define DWMCI_CTYPE_1BIT	0
105#define DWMCI_CTYPE_4BIT	(1 << 0)
106#define DWMCI_CTYPE_8BIT	(1 << 16)
107
108/* Status Register */
109#define DWMCI_FIFO_EMPTY	(1 << 2)
110#define DWMCI_FIFO_FULL		(1 << 3)
111#define DWMCI_BUSY		(1 << 9)
112#define DWMCI_FIFO_MASK		0x1fff
113#define DWMCI_FIFO_SHIFT	17
114
115/* FIFOTH Register */
116#define MSIZE(x)		((x) << 28)
117#define RX_WMARK(x)		((x) << 16)
118#define TX_WMARK(x)		(x)
119#define RX_WMARK_SHIFT		16
120#define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)
121
122#define DWMCI_IDMAC_OWN		(1 << 31)
123#define DWMCI_IDMAC_CH		(1 << 4)
124#define DWMCI_IDMAC_FS		(1 << 3)
125#define DWMCI_IDMAC_LD		(1 << 2)
126
127/*  Bus Mode Register */
128#define DWMCI_BMOD_IDMAC_RESET	(1 << 0)
129#define DWMCI_BMOD_IDMAC_FB	(1 << 1)
130#define DWMCI_BMOD_IDMAC_EN	(1 << 7)
131
132/* UHS register */
133#define DWMCI_DDR_MODE	(1 << 16)
134
135/* Internal IDMAC interrupt defines */
136#define DWMCI_IDINTEN_RI		BIT(1)
137#define DWMCI_IDINTEN_TI		BIT(0)
138
139#define DWMCI_IDINTEN_MASK	(DWMCI_IDINTEN_TI | \
140				 DWMCI_IDINTEN_RI)
141
142/* quirks */
143#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)
144
145/**
146 * struct dwmci_host - Information about a designware MMC host
147 *
148 * @name:	Device name
149 * @ioaddr:	Base I/O address of controller
150 * @quirks:	Quick flags - see DWMCI_QUIRK_...
151 * @caps:	Capabilities - see MMC_MODE_...
152 * @bus_hz:	Bus speed in Hz, if @get_mmc_clk() is NULL
153 * @div:	Arbitrary clock divider value for use by controller
154 * @dev_index:	Arbitrary device index for use by controller
155 * @dev_id:	Arbitrary device ID for use by controller
156 * @buswidth:	Bus width in bits (8 or 4)
157 * @fifoth_val:	Value for FIFOTH register (or 0 to leave unset)
158 * @mmc:	Pointer to generic MMC structure for this device
159 * @priv:	Private pointer for use by controller
160 */
161struct dwmci_host {
162	const char *name;
163	void *ioaddr;
164	unsigned int quirks;
165	unsigned int caps;
166	unsigned int version;
167	unsigned int clock;
168	unsigned int bus_hz;
169	unsigned int div;
170	int dev_index;
171	int dev_id;
172	int buswidth;
173	u32 fifoth_val;
174	struct mmc *mmc;
175	void *priv;
176
177	int (*clksel)(struct dwmci_host *host);
178	void (*board_init)(struct dwmci_host *host);
179
180	/**
181	 * Get / set a particular MMC clock frequency
182	 *
183	 * This is used to request the current clock frequency of the clock
184	 * that drives the DWMMC peripheral. The caller will then use this
185	 * information to work out the divider it needs to achieve the
186	 * required MMC bus clock frequency. If you want to handle the
187	 * clock external to DWMMC, use @freq to select the frequency and
188	 * return that value too. Then DWMMC will put itself in bypass mode.
189	 *
190	 * @host:	DWMMC host
191	 * @freq:	Frequency the host is trying to achieve
192	 */
193	unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
194#ifndef CONFIG_BLK
195	struct mmc_config cfg;
196#endif
197
198	/* use fifo mode to read and write data */
199	bool fifo_mode;
200};
201
202struct dwmci_idmac {
203	u32 flags;
204	u32 cnt;
205	u32 addr;
206	u32 next_addr;
207} __aligned(ARCH_DMA_MINALIGN);
208
209static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
210{
211	writel(val, host->ioaddr + reg);
212}
213
214static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
215{
216	writew(val, host->ioaddr + reg);
217}
218
219static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
220{
221	writeb(val, host->ioaddr + reg);
222}
223static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
224{
225	return readl(host->ioaddr + reg);
226}
227
228static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
229{
230	return readw(host->ioaddr + reg);
231}
232
233static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
234{
235	return readb(host->ioaddr + reg);
236}
237
238#ifdef CONFIG_BLK
239/**
240 * dwmci_setup_cfg() - Set up the configuration for DWMMC
241 *
242 * This is used to set up a DWMMC device when you are using CONFIG_BLK.
243 *
244 * This should be called from your MMC driver's probe() method once you have
245 * the information required.
246 *
247 * Generally your driver will have a platform data structure which holds both
248 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
249 * For example:
250 *
251 * struct rockchip_mmc_plat {
252 *	struct mmc_config cfg;
253 *	struct mmc mmc;
254 * };
255 *
256 * ...
257 *
258 * Inside U_BOOT_DRIVER():
259 *	.plat_auto	= sizeof(struct rockchip_mmc_plat),
260 *
261 * To access platform data:
262 *	struct rockchip_mmc_plat *plat = dev_get_plat(dev);
263 *
264 * See rockchip_dw_mmc.c for an example.
265 *
266 * @cfg:	Configuration structure to fill in (generally &plat->mmc)
267 * @host:	DWMMC host
268 * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
269 * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
270 */
271void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
272		u32 max_clk, u32 min_clk);
273
274/**
275 * dwmci_bind() - Set up a new MMC block device
276 *
277 * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
278 * It should be called from your driver's bind() method.
279 *
280 * See rockchip_dw_mmc.c for an example.
281 *
282 * @dev:	Device to set up
283 * @mmc:	Pointer to mmc structure (normally &plat->mmc)
284 * @cfg:	Empty configuration structure (generally &plat->cfg). This is
285 *		normally all zeroes at this point. The only purpose of passing
286 *		this in is to set mmc->cfg to it.
287 * Return: 0 if OK, -ve if the block device could not be created
288 */
289int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
290
291#else
292/**
293 * add_dwmci() - Add a new DWMMC interface
294 *
295 * This is used when you are not using CONFIG_BLK. Convert your driver over!
296 *
297 * @host:	DWMMC host structure
298 * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
299 * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
300 * Return: 0 if OK, -ve on error
301 */
302int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
303#endif /* !CONFIG_BLK */
304
305#ifdef CONFIG_DM_MMC
306/* Export the operations to drivers */
307int dwmci_probe(struct udevice *dev);
308extern const struct dm_mmc_ops dm_dwmci_ops;
309#endif
310
311#endif	/* __DWMMC_HW_H */
312