Searched refs:reg_offset (Results 326 - 350 of 377) sorted by relevance

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/linux-master/drivers/gpu/drm/radeon/
H A Drv770_dpm.c237 u16 reg_offset, u32 *value)
242 pi->soft_regs_start + reg_offset,
248 u16 reg_offset, u32 value)
253 pi->soft_regs_start + reg_offset,
247 rv770_write_smc_soft_register(struct radeon_device *rdev, u16 reg_offset, u32 value) argument
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c328 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
H A Damdgpu_ras.h381 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
H A Dmmhub_v1_7.c1216 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
H A Dmmhub_v9_4.c1571 if (mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
H A Duvd_v7_0.c1302 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1303 reg += p->adev->reg_offset[UVD_HWIP][1][1];
H A Damdgpu_mes.c840 op_input.read_reg.reg_offset = reg;
865 op_input.write_reg.reg_offset = reg;
H A Damdgpu_uvd.c1143 offset = adev->reg_offset[UVD_HWIP][ring->me][1];
/linux-master/include/linux/
H A Dhisi_acc_qm.h173 u32 reg_offset; member in struct:dfx_diff_registers
/linux-master/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmac.c1160 u32 val, reg_offset; local
1181 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1196 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset);
1197 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset);
/linux-master/fs/xfs/
H A Dxfs_log.c2318 uint32_t reg_offset = 0; local
2405 reg_offset += rlen;
2406 rlen = reg->i_len - reg_offset;
2416 reg->i_addr + reg_offset,
/linux-master/drivers/pci/controller/
H A Dpcie-iproc.c404 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) argument
406 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
/linux-master/drivers/regulator/
H A Dpalmas-regulator.c322 .reg_offset = _offset, \
358 .reg_offset = _offset, \
H A Drk808-regulator.c370 static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv) argument
378 reg = rdev->desc->vsel_reg + reg_offset;
/linux-master/drivers/misc/
H A Dxilinx_sdfec.c252 u32 reg_offset, u32 bit_num,
258 reg_val = xsdfec_regread(xsdfec, reg_offset);
251 update_bool_config_from_reg(struct xsdfec_dev *xsdfec, u32 reg_offset, u32 bit_num, char *config_value) argument
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_main.c1307 u16 reg_offset; local
1314 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1318 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1335 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
4206 u32 reg_offset, vf_shift, vmolr; local
4228 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4231 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4232 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMAS
4614 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); local
[all...]
/linux-master/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c4164 int reg_offset; local
4167 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4172 val = REG_RD(bp, reg_offset);
4174 REG_WR(bp, reg_offset, val);
4191 val = REG_RD(bp, reg_offset);
4193 REG_WR(bp, reg_offset, val);
4217 int reg_offset; local
4219 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4222 val = REG_RD(bp, reg_offset);
4224 REG_WR(bp, reg_offset, va
4261 int reg_offset; local
6043 int reg_offset, reg_offset_en5; local
[all...]
/linux-master/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet.c978 u16 reg_offset; member in struct:bcmgenet_stats
1005 .reg_offset = offset, \
1227 val = bcmgenet_umac_readl(priv, s->reg_offset);
1231 s->reg_offset);
1234 s->reg_offset);
/linux-master/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c563 u32 reg_offset, u32 timeout_us,
569 ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset,
576 reg_offset, mask, is_clear);
562 cadence_nand_wait_for_value(struct cdns_nand_ctrl *cdns_ctrl, u32 reg_offset, u32 timeout_us, u32 mask, bool is_clear) argument
/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_hdmi.c726 u32 reg_offset, const u8 *buf, u32 len)
728 if ((reg_offset + len) > 32)
742 ((reg_offset + i)<<2));
725 hdmiphy_reg_write_buf(struct hdmi_context *hdata, u32 reg_offset, const u8 *buf, u32 len) argument
/linux-master/drivers/phy/cadence/
H A Dphy-cadence-torrent.c41 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
43 (((ln) << 9) << (reg_offset)))
45 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
47 (((ln) << 9) << (reg_offset)))
52 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
54 (((ln) << 8) << (reg_offset)))
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_debug.c2152 u32 offset = 0, reg_offset = 0; local
2159 while (reg_offset < total_len) {
2160 u32 curr_len = min_t(u32, read_len, total_len - reg_offset);
2167 reg_offset += curr_len;
2170 if (reg_offset < total_len) {
2174 reg_offset += curr_len;
3734 rule->reg_offset;
3874 rule->reg_offset;
/linux-master/drivers/net/wireless/marvell/mwifiex/
H A Dmain.h1503 u32 reg_offset, u32 reg_value);
1506 u32 reg_offset, u32 *value);
/linux-master/drivers/net/ipa/
H A Dipa_endpoint.c1652 iowrite32(val, ipa->reg_virt + reg_offset(reg));
2023 val = ioread32(ipa->reg_virt + reg_offset(reg));
/linux-master/drivers/net/ethernet/calxeda/
H A Dxgmac.c1563 #define XGMAC_HW_STAT(m, reg_offset) \
1564 { #m, reg_offset, true }

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