/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv770_dpm.c | 237 u16 reg_offset, u32 *value) 242 pi->soft_regs_start + reg_offset, 248 u16 reg_offset, u32 value) 253 pi->soft_regs_start + reg_offset, 247 rv770_write_smc_soft_register(struct radeon_device *rdev, u16 reg_offset, u32 value) argument
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | imu_v11_0.c | 328 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
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H A D | amdgpu_ras.h | 381 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
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H A D | mmhub_v1_7.c | 1216 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
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H A D | mmhub_v9_4.c | 1571 if (mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
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H A D | uvd_v7_0.c | 1302 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1303 reg += p->adev->reg_offset[UVD_HWIP][1][1];
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H A D | amdgpu_mes.c | 840 op_input.read_reg.reg_offset = reg; 865 op_input.write_reg.reg_offset = reg;
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H A D | amdgpu_uvd.c | 1143 offset = adev->reg_offset[UVD_HWIP][ring->me][1];
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/linux-master/include/linux/ |
H A D | hisi_acc_qm.h | 173 u32 reg_offset; member in struct:dfx_diff_registers
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/linux-master/drivers/net/wireless/mediatek/mt76/mt7915/ |
H A D | mac.c | 1160 u32 val, reg_offset; local 1181 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1196 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1197 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset);
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/linux-master/fs/xfs/ |
H A D | xfs_log.c | 2318 uint32_t reg_offset = 0; local 2405 reg_offset += rlen; 2406 rlen = reg->i_len - reg_offset; 2416 reg->i_addr + reg_offset,
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/linux-master/drivers/pci/controller/ |
H A D | pcie-iproc.c | 404 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset) argument 406 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
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/linux-master/drivers/regulator/ |
H A D | palmas-regulator.c | 322 .reg_offset = _offset, \ 358 .reg_offset = _offset, \
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H A D | rk808-regulator.c | 370 static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv) argument 378 reg = rdev->desc->vsel_reg + reg_offset;
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/linux-master/drivers/misc/ |
H A D | xilinx_sdfec.c | 252 u32 reg_offset, u32 bit_num, 258 reg_val = xsdfec_regread(xsdfec, reg_offset); 251 update_bool_config_from_reg(struct xsdfec_dev *xsdfec, u32 reg_offset, u32 bit_num, char *config_value) argument
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/linux-master/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_main.c | 1307 u16 reg_offset; local 1314 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1318 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1335 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 4206 u32 reg_offset, vf_shift, vmolr; local 4228 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4231 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4232 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMAS 4614 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); local [all...] |
/linux-master/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_main.c | 4164 int reg_offset; local 4167 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4172 val = REG_RD(bp, reg_offset); 4174 REG_WR(bp, reg_offset, val); 4191 val = REG_RD(bp, reg_offset); 4193 REG_WR(bp, reg_offset, val); 4217 int reg_offset; local 4219 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 4222 val = REG_RD(bp, reg_offset); 4224 REG_WR(bp, reg_offset, va 4261 int reg_offset; local 6043 int reg_offset, reg_offset_en5; local [all...] |
/linux-master/drivers/net/ethernet/broadcom/genet/ |
H A D | bcmgenet.c | 978 u16 reg_offset; member in struct:bcmgenet_stats 1005 .reg_offset = offset, \ 1227 val = bcmgenet_umac_readl(priv, s->reg_offset); 1231 s->reg_offset); 1234 s->reg_offset);
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/linux-master/drivers/mtd/nand/raw/ |
H A D | cadence-nand-controller.c | 563 u32 reg_offset, u32 timeout_us, 569 ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset, 576 reg_offset, mask, is_clear); 562 cadence_nand_wait_for_value(struct cdns_nand_ctrl *cdns_ctrl, u32 reg_offset, u32 timeout_us, u32 mask, bool is_clear) argument
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/linux-master/drivers/gpu/drm/exynos/ |
H A D | exynos_hdmi.c | 726 u32 reg_offset, const u8 *buf, u32 len) 728 if ((reg_offset + len) > 32) 742 ((reg_offset + i)<<2)); 725 hdmiphy_reg_write_buf(struct hdmi_context *hdata, u32 reg_offset, const u8 *buf, u32 len) argument
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/linux-master/drivers/phy/cadence/ |
H A D | phy-cadence-torrent.c | 41 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 43 (((ln) << 9) << (reg_offset))) 45 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 47 (((ln) << 9) << (reg_offset))) 52 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 54 (((ln) << 8) << (reg_offset)))
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/linux-master/drivers/net/ethernet/qlogic/qed/ |
H A D | qed_debug.c | 2152 u32 offset = 0, reg_offset = 0; local 2159 while (reg_offset < total_len) { 2160 u32 curr_len = min_t(u32, read_len, total_len - reg_offset); 2167 reg_offset += curr_len; 2170 if (reg_offset < total_len) { 2174 reg_offset += curr_len; 3734 rule->reg_offset; 3874 rule->reg_offset;
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/linux-master/drivers/net/wireless/marvell/mwifiex/ |
H A D | main.h | 1503 u32 reg_offset, u32 reg_value); 1506 u32 reg_offset, u32 *value);
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/linux-master/drivers/net/ipa/ |
H A D | ipa_endpoint.c | 1652 iowrite32(val, ipa->reg_virt + reg_offset(reg)); 2023 val = ioread32(ipa->reg_virt + reg_offset(reg));
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/linux-master/drivers/net/ethernet/calxeda/ |
H A D | xgmac.c | 1563 #define XGMAC_HW_STAT(m, reg_offset) \ 1564 { #m, reg_offset, true }
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