1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#include <linux/types.h> 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/netdevice.h> 8#include <linux/vmalloc.h> 9#include <linux/string.h> 10#include <linux/in.h> 11#include <linux/interrupt.h> 12#include <linux/ip.h> 13#include <linux/tcp.h> 14#include <linux/sctp.h> 15#include <linux/pkt_sched.h> 16#include <linux/ipv6.h> 17#include <linux/slab.h> 18#include <net/checksum.h> 19#include <net/ip6_checksum.h> 20#include <linux/etherdevice.h> 21#include <linux/ethtool.h> 22#include <linux/if.h> 23#include <linux/if_vlan.h> 24#include <linux/if_macvlan.h> 25#include <linux/if_bridge.h> 26#include <linux/prefetch.h> 27#include <linux/bpf.h> 28#include <linux/bpf_trace.h> 29#include <linux/atomic.h> 30#include <linux/numa.h> 31#include <generated/utsrelease.h> 32#include <scsi/fc/fc_fcoe.h> 33#include <net/udp_tunnel.h> 34#include <net/pkt_cls.h> 35#include <net/tc_act/tc_gact.h> 36#include <net/tc_act/tc_mirred.h> 37#include <net/vxlan.h> 38#include <net/mpls.h> 39#include <net/netdev_queues.h> 40#include <net/xdp_sock_drv.h> 41#include <net/xfrm.h> 42 43#include "ixgbe.h" 44#include "ixgbe_common.h" 45#include "ixgbe_dcb_82599.h" 46#include "ixgbe_phy.h" 47#include "ixgbe_sriov.h" 48#include "ixgbe_model.h" 49#include "ixgbe_txrx_common.h" 50 51char ixgbe_driver_name[] = "ixgbe"; 52static const char ixgbe_driver_string[] = 53 "Intel(R) 10 Gigabit PCI Express Network Driver"; 54#ifdef IXGBE_FCOE 55char ixgbe_default_device_descr[] = 56 "Intel(R) 10 Gigabit Network Connection"; 57#else 58static char ixgbe_default_device_descr[] = 59 "Intel(R) 10 Gigabit Network Connection"; 60#endif 61static const char ixgbe_copyright[] = 62 "Copyright (c) 1999-2016 Intel Corporation."; 63 64static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 65 66static const struct ixgbe_info *ixgbe_info_tbl[] = { 67 [board_82598] = &ixgbe_82598_info, 68 [board_82599] = &ixgbe_82599_info, 69 [board_X540] = &ixgbe_X540_info, 70 [board_X550] = &ixgbe_X550_info, 71 [board_X550EM_x] = &ixgbe_X550EM_x_info, 72 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 73 [board_x550em_a] = &ixgbe_x550em_a_info, 74 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 75}; 76 77/* ixgbe_pci_tbl - PCI Device ID Table 78 * 79 * Wildcard entries (PCI_ANY_ID) should come last 80 * Last entry must be all 0s 81 * 82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 83 * Class, Class Mask, private data (not used) } 84 */ 85static const struct pci_device_id ixgbe_pci_tbl[] = { 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, 95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, 119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x}, 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, 122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw}, 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a}, 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw }, 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw }, 133 /* required last entry */ 134 {0, } 135}; 136MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 137 138#ifdef CONFIG_IXGBE_DCA 139static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 140 void *p); 141static struct notifier_block dca_notifier = { 142 .notifier_call = ixgbe_notify_dca, 143 .next = NULL, 144 .priority = 0 145}; 146#endif 147 148#ifdef CONFIG_PCI_IOV 149static unsigned int max_vfs; 150module_param(max_vfs, uint, 0); 151MODULE_PARM_DESC(max_vfs, 152 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 153#endif /* CONFIG_PCI_IOV */ 154 155static bool allow_unsupported_sfp; 156module_param(allow_unsupported_sfp, bool, 0444); 157MODULE_PARM_DESC(allow_unsupported_sfp, 158 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 159 160#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 161static int debug = -1; 162module_param(debug, int, 0); 163MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 164 165MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 166MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 167MODULE_LICENSE("GPL v2"); 168 169DEFINE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 170EXPORT_SYMBOL(ixgbe_xdp_locking_key); 171 172static struct workqueue_struct *ixgbe_wq; 173 174static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 175static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 176 177static const struct net_device_ops ixgbe_netdev_ops; 178 179static bool netif_is_ixgbe(struct net_device *dev) 180{ 181 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 182} 183 184static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 185 u32 reg, u16 *value) 186{ 187 struct pci_dev *parent_dev; 188 struct pci_bus *parent_bus; 189 190 parent_bus = adapter->pdev->bus->parent; 191 if (!parent_bus) 192 return -1; 193 194 parent_dev = parent_bus->self; 195 if (!parent_dev) 196 return -1; 197 198 if (!pci_is_pcie(parent_dev)) 199 return -1; 200 201 pcie_capability_read_word(parent_dev, reg, value); 202 if (*value == IXGBE_FAILED_READ_CFG_WORD && 203 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 204 return -1; 205 return 0; 206} 207 208static int ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 209{ 210 struct ixgbe_hw *hw = &adapter->hw; 211 u16 link_status = 0; 212 int err; 213 214 hw->bus.type = ixgbe_bus_type_pci_express; 215 216 /* Get the negotiated link width and speed from PCI config space of the 217 * parent, as this device is behind a switch 218 */ 219 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 220 221 /* assume caller will handle error case */ 222 if (err) 223 return err; 224 225 hw->bus.width = ixgbe_convert_bus_width(link_status); 226 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 227 228 return 0; 229} 230 231/** 232 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent 233 * @hw: hw specific details 234 * 235 * This function is used by probe to determine whether a device's PCI-Express 236 * bandwidth details should be gathered from the parent bus instead of from the 237 * device. Used to ensure that various locations all have the correct device ID 238 * checks. 239 */ 240static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 241{ 242 switch (hw->device_id) { 243 case IXGBE_DEV_ID_82599_SFP_SF_QP: 244 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 245 return true; 246 default: 247 return false; 248 } 249} 250 251static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 252 int expected_gts) 253{ 254 struct ixgbe_hw *hw = &adapter->hw; 255 struct pci_dev *pdev; 256 257 /* Some devices are not connected over PCIe and thus do not negotiate 258 * speed. These devices do not have valid bus info, and thus any report 259 * we generate may not be correct. 260 */ 261 if (hw->bus.type == ixgbe_bus_type_internal) 262 return; 263 264 /* determine whether to use the parent device */ 265 if (ixgbe_pcie_from_parent(&adapter->hw)) 266 pdev = adapter->pdev->bus->parent->self; 267 else 268 pdev = adapter->pdev; 269 270 pcie_print_link_status(pdev); 271} 272 273static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 274{ 275 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 276 !test_bit(__IXGBE_REMOVING, &adapter->state) && 277 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 278 queue_work(ixgbe_wq, &adapter->service_task); 279} 280 281static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 282{ 283 struct ixgbe_adapter *adapter = hw->back; 284 285 if (!hw->hw_addr) 286 return; 287 hw->hw_addr = NULL; 288 e_dev_err("Adapter removed\n"); 289 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 290 ixgbe_service_event_schedule(adapter); 291} 292 293static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 294{ 295 u8 __iomem *reg_addr; 296 u32 value; 297 int i; 298 299 reg_addr = READ_ONCE(hw->hw_addr); 300 if (ixgbe_removed(reg_addr)) 301 return IXGBE_FAILED_READ_REG; 302 303 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 304 * so perform several status register reads to determine if the adapter 305 * has been removed. 306 */ 307 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 308 value = readl(reg_addr + IXGBE_STATUS); 309 if (value != IXGBE_FAILED_READ_REG) 310 break; 311 mdelay(3); 312 } 313 314 if (value == IXGBE_FAILED_READ_REG) 315 ixgbe_remove_adapter(hw); 316 else 317 value = readl(reg_addr + reg); 318 return value; 319} 320 321/** 322 * ixgbe_read_reg - Read from device register 323 * @hw: hw specific details 324 * @reg: offset of register to read 325 * 326 * Returns : value read or IXGBE_FAILED_READ_REG if removed 327 * 328 * This function is used to read device registers. It checks for device 329 * removal by confirming any read that returns all ones by checking the 330 * status register value for all ones. This function avoids reading from 331 * the hardware if a removal was previously detected in which case it 332 * returns IXGBE_FAILED_READ_REG (all ones). 333 */ 334u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 335{ 336 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 337 u32 value; 338 339 if (ixgbe_removed(reg_addr)) 340 return IXGBE_FAILED_READ_REG; 341 if (unlikely(hw->phy.nw_mng_if_sel & 342 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 343 struct ixgbe_adapter *adapter; 344 int i; 345 346 for (i = 0; i < 200; ++i) { 347 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 348 if (likely(!value)) 349 goto writes_completed; 350 if (value == IXGBE_FAILED_READ_REG) { 351 ixgbe_remove_adapter(hw); 352 return IXGBE_FAILED_READ_REG; 353 } 354 udelay(5); 355 } 356 357 adapter = hw->back; 358 e_warn(hw, "register writes incomplete %08x\n", value); 359 } 360 361writes_completed: 362 value = readl(reg_addr + reg); 363 if (unlikely(value == IXGBE_FAILED_READ_REG)) 364 value = ixgbe_check_remove(hw, reg); 365 return value; 366} 367 368static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 369{ 370 u16 value; 371 372 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 373 if (value == IXGBE_FAILED_READ_CFG_WORD) { 374 ixgbe_remove_adapter(hw); 375 return true; 376 } 377 return false; 378} 379 380u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 381{ 382 struct ixgbe_adapter *adapter = hw->back; 383 u16 value; 384 385 if (ixgbe_removed(hw->hw_addr)) 386 return IXGBE_FAILED_READ_CFG_WORD; 387 pci_read_config_word(adapter->pdev, reg, &value); 388 if (value == IXGBE_FAILED_READ_CFG_WORD && 389 ixgbe_check_cfg_remove(hw, adapter->pdev)) 390 return IXGBE_FAILED_READ_CFG_WORD; 391 return value; 392} 393 394#ifdef CONFIG_PCI_IOV 395static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 396{ 397 struct ixgbe_adapter *adapter = hw->back; 398 u32 value; 399 400 if (ixgbe_removed(hw->hw_addr)) 401 return IXGBE_FAILED_READ_CFG_DWORD; 402 pci_read_config_dword(adapter->pdev, reg, &value); 403 if (value == IXGBE_FAILED_READ_CFG_DWORD && 404 ixgbe_check_cfg_remove(hw, adapter->pdev)) 405 return IXGBE_FAILED_READ_CFG_DWORD; 406 return value; 407} 408#endif /* CONFIG_PCI_IOV */ 409 410void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 411{ 412 struct ixgbe_adapter *adapter = hw->back; 413 414 if (ixgbe_removed(hw->hw_addr)) 415 return; 416 pci_write_config_word(adapter->pdev, reg, value); 417} 418 419static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 420{ 421 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 422 423 /* flush memory to make sure state is correct before next watchdog */ 424 smp_mb__before_atomic(); 425 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 426} 427 428struct ixgbe_reg_info { 429 u32 ofs; 430 char *name; 431}; 432 433static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 434 435 /* General Registers */ 436 {IXGBE_CTRL, "CTRL"}, 437 {IXGBE_STATUS, "STATUS"}, 438 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 439 440 /* Interrupt Registers */ 441 {IXGBE_EICR, "EICR"}, 442 443 /* RX Registers */ 444 {IXGBE_SRRCTL(0), "SRRCTL"}, 445 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 446 {IXGBE_RDLEN(0), "RDLEN"}, 447 {IXGBE_RDH(0), "RDH"}, 448 {IXGBE_RDT(0), "RDT"}, 449 {IXGBE_RXDCTL(0), "RXDCTL"}, 450 {IXGBE_RDBAL(0), "RDBAL"}, 451 {IXGBE_RDBAH(0), "RDBAH"}, 452 453 /* TX Registers */ 454 {IXGBE_TDBAL(0), "TDBAL"}, 455 {IXGBE_TDBAH(0), "TDBAH"}, 456 {IXGBE_TDLEN(0), "TDLEN"}, 457 {IXGBE_TDH(0), "TDH"}, 458 {IXGBE_TDT(0), "TDT"}, 459 {IXGBE_TXDCTL(0), "TXDCTL"}, 460 461 /* List Terminator */ 462 { .name = NULL } 463}; 464 465 466/* 467 * ixgbe_regdump - register printout routine 468 */ 469static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 470{ 471 int i; 472 char rname[16]; 473 u32 regs[64]; 474 475 switch (reginfo->ofs) { 476 case IXGBE_SRRCTL(0): 477 for (i = 0; i < 64; i++) 478 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 479 break; 480 case IXGBE_DCA_RXCTRL(0): 481 for (i = 0; i < 64; i++) 482 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 483 break; 484 case IXGBE_RDLEN(0): 485 for (i = 0; i < 64; i++) 486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 487 break; 488 case IXGBE_RDH(0): 489 for (i = 0; i < 64; i++) 490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 491 break; 492 case IXGBE_RDT(0): 493 for (i = 0; i < 64; i++) 494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 495 break; 496 case IXGBE_RXDCTL(0): 497 for (i = 0; i < 64; i++) 498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 499 break; 500 case IXGBE_RDBAL(0): 501 for (i = 0; i < 64; i++) 502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 503 break; 504 case IXGBE_RDBAH(0): 505 for (i = 0; i < 64; i++) 506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 507 break; 508 case IXGBE_TDBAL(0): 509 for (i = 0; i < 64; i++) 510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 511 break; 512 case IXGBE_TDBAH(0): 513 for (i = 0; i < 64; i++) 514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 515 break; 516 case IXGBE_TDLEN(0): 517 for (i = 0; i < 64; i++) 518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 519 break; 520 case IXGBE_TDH(0): 521 for (i = 0; i < 64; i++) 522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 523 break; 524 case IXGBE_TDT(0): 525 for (i = 0; i < 64; i++) 526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 527 break; 528 case IXGBE_TXDCTL(0): 529 for (i = 0; i < 64; i++) 530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 531 break; 532 default: 533 pr_info("%-15s %08x\n", 534 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 535 return; 536 } 537 538 i = 0; 539 while (i < 64) { 540 int j; 541 char buf[9 * 8 + 1]; 542 char *p = buf; 543 544 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 545 for (j = 0; j < 8; j++) 546 p += sprintf(p, " %08x", regs[i++]); 547 pr_err("%-15s%s\n", rname, buf); 548 } 549 550} 551 552static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 553{ 554 struct ixgbe_tx_buffer *tx_buffer; 555 556 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 557 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 558 n, ring->next_to_use, ring->next_to_clean, 559 (u64)dma_unmap_addr(tx_buffer, dma), 560 dma_unmap_len(tx_buffer, len), 561 tx_buffer->next_to_watch, 562 (u64)tx_buffer->time_stamp); 563} 564 565/* 566 * ixgbe_dump - Print registers, tx-rings and rx-rings 567 */ 568static void ixgbe_dump(struct ixgbe_adapter *adapter) 569{ 570 struct net_device *netdev = adapter->netdev; 571 struct ixgbe_hw *hw = &adapter->hw; 572 struct ixgbe_reg_info *reginfo; 573 int n = 0; 574 struct ixgbe_ring *ring; 575 struct ixgbe_tx_buffer *tx_buffer; 576 union ixgbe_adv_tx_desc *tx_desc; 577 struct my_u0 { u64 a; u64 b; } *u0; 578 struct ixgbe_ring *rx_ring; 579 union ixgbe_adv_rx_desc *rx_desc; 580 struct ixgbe_rx_buffer *rx_buffer_info; 581 int i = 0; 582 583 if (!netif_msg_hw(adapter)) 584 return; 585 586 /* Print netdevice Info */ 587 if (netdev) { 588 dev_info(&adapter->pdev->dev, "Net device Info\n"); 589 pr_info("Device Name state " 590 "trans_start\n"); 591 pr_info("%-15s %016lX %016lX\n", 592 netdev->name, 593 netdev->state, 594 dev_trans_start(netdev)); 595 } 596 597 /* Print Registers */ 598 dev_info(&adapter->pdev->dev, "Register Dump\n"); 599 pr_info(" Register Name Value\n"); 600 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 601 reginfo->name; reginfo++) { 602 ixgbe_regdump(hw, reginfo); 603 } 604 605 /* Print TX Ring Summary */ 606 if (!netdev || !netif_running(netdev)) 607 return; 608 609 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 610 pr_info(" %s %s %s %s\n", 611 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 612 "leng", "ntw", "timestamp"); 613 for (n = 0; n < adapter->num_tx_queues; n++) { 614 ring = adapter->tx_ring[n]; 615 ixgbe_print_buffer(ring, n); 616 } 617 618 for (n = 0; n < adapter->num_xdp_queues; n++) { 619 ring = adapter->xdp_ring[n]; 620 ixgbe_print_buffer(ring, n); 621 } 622 623 /* Print TX Rings */ 624 if (!netif_msg_tx_done(adapter)) 625 goto rx_ring_summary; 626 627 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 628 629 /* Transmit Descriptor Formats 630 * 631 * 82598 Advanced Transmit Descriptor 632 * +--------------------------------------------------------------+ 633 * 0 | Buffer Address [63:0] | 634 * +--------------------------------------------------------------+ 635 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 636 * +--------------------------------------------------------------+ 637 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 638 * 639 * 82598 Advanced Transmit Descriptor (Write-Back Format) 640 * +--------------------------------------------------------------+ 641 * 0 | RSV [63:0] | 642 * +--------------------------------------------------------------+ 643 * 8 | RSV | STA | NXTSEQ | 644 * +--------------------------------------------------------------+ 645 * 63 36 35 32 31 0 646 * 647 * 82599+ Advanced Transmit Descriptor 648 * +--------------------------------------------------------------+ 649 * 0 | Buffer Address [63:0] | 650 * +--------------------------------------------------------------+ 651 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 652 * +--------------------------------------------------------------+ 653 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 654 * 655 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 656 * +--------------------------------------------------------------+ 657 * 0 | RSV [63:0] | 658 * +--------------------------------------------------------------+ 659 * 8 | RSV | STA | RSV | 660 * +--------------------------------------------------------------+ 661 * 63 36 35 32 31 0 662 */ 663 664 for (n = 0; n < adapter->num_tx_queues; n++) { 665 ring = adapter->tx_ring[n]; 666 pr_info("------------------------------------\n"); 667 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 668 pr_info("------------------------------------\n"); 669 pr_info("%s%s %s %s %s %s\n", 670 "T [desc] [address 63:0 ] ", 671 "[PlPOIdStDDt Ln] [bi->dma ] ", 672 "leng", "ntw", "timestamp", "bi->skb"); 673 674 for (i = 0; ring->desc && (i < ring->count); i++) { 675 tx_desc = IXGBE_TX_DESC(ring, i); 676 tx_buffer = &ring->tx_buffer_info[i]; 677 u0 = (struct my_u0 *)tx_desc; 678 if (dma_unmap_len(tx_buffer, len) > 0) { 679 const char *ring_desc; 680 681 if (i == ring->next_to_use && 682 i == ring->next_to_clean) 683 ring_desc = " NTC/U"; 684 else if (i == ring->next_to_use) 685 ring_desc = " NTU"; 686 else if (i == ring->next_to_clean) 687 ring_desc = " NTC"; 688 else 689 ring_desc = ""; 690 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 691 i, 692 le64_to_cpu((__force __le64)u0->a), 693 le64_to_cpu((__force __le64)u0->b), 694 (u64)dma_unmap_addr(tx_buffer, dma), 695 dma_unmap_len(tx_buffer, len), 696 tx_buffer->next_to_watch, 697 (u64)tx_buffer->time_stamp, 698 tx_buffer->skb, 699 ring_desc); 700 701 if (netif_msg_pktdata(adapter) && 702 tx_buffer->skb) 703 print_hex_dump(KERN_INFO, "", 704 DUMP_PREFIX_ADDRESS, 16, 1, 705 tx_buffer->skb->data, 706 dma_unmap_len(tx_buffer, len), 707 true); 708 } 709 } 710 } 711 712 /* Print RX Rings Summary */ 713rx_ring_summary: 714 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 715 pr_info("Queue [NTU] [NTC]\n"); 716 for (n = 0; n < adapter->num_rx_queues; n++) { 717 rx_ring = adapter->rx_ring[n]; 718 pr_info("%5d %5X %5X\n", 719 n, rx_ring->next_to_use, rx_ring->next_to_clean); 720 } 721 722 /* Print RX Rings */ 723 if (!netif_msg_rx_status(adapter)) 724 return; 725 726 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 727 728 /* Receive Descriptor Formats 729 * 730 * 82598 Advanced Receive Descriptor (Read) Format 731 * 63 1 0 732 * +-----------------------------------------------------+ 733 * 0 | Packet Buffer Address [63:1] |A0/NSE| 734 * +----------------------------------------------+------+ 735 * 8 | Header Buffer Address [63:1] | DD | 736 * +-----------------------------------------------------+ 737 * 738 * 739 * 82598 Advanced Receive Descriptor (Write-Back) Format 740 * 741 * 63 48 47 32 31 30 21 20 16 15 4 3 0 742 * +------------------------------------------------------+ 743 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 744 * | Packet | IP | | | | Type | Type | 745 * | Checksum | Ident | | | | | | 746 * +------------------------------------------------------+ 747 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 748 * +------------------------------------------------------+ 749 * 63 48 47 32 31 20 19 0 750 * 751 * 82599+ Advanced Receive Descriptor (Read) Format 752 * 63 1 0 753 * +-----------------------------------------------------+ 754 * 0 | Packet Buffer Address [63:1] |A0/NSE| 755 * +----------------------------------------------+------+ 756 * 8 | Header Buffer Address [63:1] | DD | 757 * +-----------------------------------------------------+ 758 * 759 * 760 * 82599+ Advanced Receive Descriptor (Write-Back) Format 761 * 762 * 63 48 47 32 31 30 21 20 17 16 4 3 0 763 * +------------------------------------------------------+ 764 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 765 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 766 * |/ Flow Dir Flt ID | | | | | | 767 * +------------------------------------------------------+ 768 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 769 * +------------------------------------------------------+ 770 * 63 48 47 32 31 20 19 0 771 */ 772 773 for (n = 0; n < adapter->num_rx_queues; n++) { 774 rx_ring = adapter->rx_ring[n]; 775 pr_info("------------------------------------\n"); 776 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 777 pr_info("------------------------------------\n"); 778 pr_info("%s%s%s\n", 779 "R [desc] [ PktBuf A0] ", 780 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 781 "<-- Adv Rx Read format"); 782 pr_info("%s%s%s\n", 783 "RWB[desc] [PcsmIpSHl PtRs] ", 784 "[vl er S cks ln] ---------------- [bi->skb ] ", 785 "<-- Adv Rx Write-Back format"); 786 787 for (i = 0; i < rx_ring->count; i++) { 788 const char *ring_desc; 789 790 if (i == rx_ring->next_to_use) 791 ring_desc = " NTU"; 792 else if (i == rx_ring->next_to_clean) 793 ring_desc = " NTC"; 794 else 795 ring_desc = ""; 796 797 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 798 rx_desc = IXGBE_RX_DESC(rx_ring, i); 799 u0 = (struct my_u0 *)rx_desc; 800 if (rx_desc->wb.upper.length) { 801 /* Descriptor Done */ 802 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 803 i, 804 le64_to_cpu((__force __le64)u0->a), 805 le64_to_cpu((__force __le64)u0->b), 806 rx_buffer_info->skb, 807 ring_desc); 808 } else { 809 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 810 i, 811 le64_to_cpu((__force __le64)u0->a), 812 le64_to_cpu((__force __le64)u0->b), 813 (u64)rx_buffer_info->dma, 814 rx_buffer_info->skb, 815 ring_desc); 816 817 if (netif_msg_pktdata(adapter) && 818 rx_buffer_info->dma) { 819 print_hex_dump(KERN_INFO, "", 820 DUMP_PREFIX_ADDRESS, 16, 1, 821 page_address(rx_buffer_info->page) + 822 rx_buffer_info->page_offset, 823 ixgbe_rx_bufsz(rx_ring), true); 824 } 825 } 826 } 827 } 828} 829 830static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 831{ 832 u32 ctrl_ext; 833 834 /* Let firmware take over control of h/w */ 835 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 837 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 838} 839 840static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 841{ 842 u32 ctrl_ext; 843 844 /* Let firmware know the driver has taken over */ 845 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 846 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 847 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 848} 849 850/** 851 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 852 * @adapter: pointer to adapter struct 853 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 854 * @queue: queue to map the corresponding interrupt to 855 * @msix_vector: the vector to map to the corresponding queue 856 * 857 */ 858static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 859 u8 queue, u8 msix_vector) 860{ 861 u32 ivar, index; 862 struct ixgbe_hw *hw = &adapter->hw; 863 switch (hw->mac.type) { 864 case ixgbe_mac_82598EB: 865 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 866 if (direction == -1) 867 direction = 0; 868 index = (((direction * 64) + queue) >> 2) & 0x1F; 869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 870 ivar &= ~(0xFF << (8 * (queue & 0x3))); 871 ivar |= (msix_vector << (8 * (queue & 0x3))); 872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 873 break; 874 case ixgbe_mac_82599EB: 875 case ixgbe_mac_X540: 876 case ixgbe_mac_X550: 877 case ixgbe_mac_X550EM_x: 878 case ixgbe_mac_x550em_a: 879 if (direction == -1) { 880 /* other causes */ 881 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 882 index = ((queue & 1) * 8); 883 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 884 ivar &= ~(0xFF << index); 885 ivar |= (msix_vector << index); 886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 887 break; 888 } else { 889 /* tx or rx causes */ 890 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 891 index = ((16 * (queue & 1)) + (8 * direction)); 892 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 893 ivar &= ~(0xFF << index); 894 ivar |= (msix_vector << index); 895 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 896 break; 897 } 898 default: 899 break; 900 } 901} 902 903void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 904 u64 qmask) 905{ 906 u32 mask; 907 908 switch (adapter->hw.mac.type) { 909 case ixgbe_mac_82598EB: 910 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 912 break; 913 case ixgbe_mac_82599EB: 914 case ixgbe_mac_X540: 915 case ixgbe_mac_X550: 916 case ixgbe_mac_X550EM_x: 917 case ixgbe_mac_x550em_a: 918 mask = (qmask & 0xFFFFFFFF); 919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 920 mask = (qmask >> 32); 921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 922 break; 923 default: 924 break; 925 } 926} 927 928static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 929{ 930 struct ixgbe_hw *hw = &adapter->hw; 931 struct ixgbe_hw_stats *hwstats = &adapter->stats; 932 int i; 933 u32 data; 934 935 if ((hw->fc.current_mode != ixgbe_fc_full) && 936 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 937 return; 938 939 switch (hw->mac.type) { 940 case ixgbe_mac_82598EB: 941 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 942 break; 943 default: 944 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 945 } 946 hwstats->lxoffrxc += data; 947 948 /* refill credits (no tx hang) if we received xoff */ 949 if (!data) 950 return; 951 952 for (i = 0; i < adapter->num_tx_queues; i++) 953 clear_bit(__IXGBE_HANG_CHECK_ARMED, 954 &adapter->tx_ring[i]->state); 955 956 for (i = 0; i < adapter->num_xdp_queues; i++) 957 clear_bit(__IXGBE_HANG_CHECK_ARMED, 958 &adapter->xdp_ring[i]->state); 959} 960 961static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 962{ 963 struct ixgbe_hw *hw = &adapter->hw; 964 struct ixgbe_hw_stats *hwstats = &adapter->stats; 965 u32 xoff[8] = {0}; 966 u8 tc; 967 int i; 968 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 969 970 if (adapter->ixgbe_ieee_pfc) 971 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 972 973 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 974 ixgbe_update_xoff_rx_lfc(adapter); 975 return; 976 } 977 978 /* update stats for each tc, only valid with PFC enabled */ 979 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 980 u32 pxoffrxc; 981 982 switch (hw->mac.type) { 983 case ixgbe_mac_82598EB: 984 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 985 break; 986 default: 987 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 988 } 989 hwstats->pxoffrxc[i] += pxoffrxc; 990 /* Get the TC for given UP */ 991 tc = netdev_get_prio_tc_map(adapter->netdev, i); 992 xoff[tc] += pxoffrxc; 993 } 994 995 /* disarm tx queues that have received xoff frames */ 996 for (i = 0; i < adapter->num_tx_queues; i++) { 997 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 998 999 tc = tx_ring->dcb_tc; 1000 if (xoff[tc]) 1001 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1002 } 1003 1004 for (i = 0; i < adapter->num_xdp_queues; i++) { 1005 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1006 1007 tc = xdp_ring->dcb_tc; 1008 if (xoff[tc]) 1009 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state); 1010 } 1011} 1012 1013static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1014{ 1015 return ring->stats.packets; 1016} 1017 1018static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1019{ 1020 unsigned int head, tail; 1021 1022 head = ring->next_to_clean; 1023 tail = ring->next_to_use; 1024 1025 return ((head <= tail) ? tail : tail + ring->count) - head; 1026} 1027 1028static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1029{ 1030 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1031 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1032 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1033 1034 clear_check_for_tx_hang(tx_ring); 1035 1036 /* 1037 * Check for a hung queue, but be thorough. This verifies 1038 * that a transmit has been completed since the previous 1039 * check AND there is at least one packet pending. The 1040 * ARMED bit is set to indicate a potential hang. The 1041 * bit is cleared if a pause frame is received to remove 1042 * false hang detection due to PFC or 802.3x frames. By 1043 * requiring this to fail twice we avoid races with 1044 * pfc clearing the ARMED bit and conditions where we 1045 * run the check_tx_hang logic with a transmit completion 1046 * pending but without time to complete it yet. 1047 */ 1048 if (tx_done_old == tx_done && tx_pending) 1049 /* make sure it is true for two checks in a row */ 1050 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1051 &tx_ring->state); 1052 /* update completed stats and continue */ 1053 tx_ring->tx_stats.tx_done_old = tx_done; 1054 /* reset the countdown */ 1055 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); 1056 1057 return false; 1058} 1059 1060/** 1061 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1062 * @adapter: driver private struct 1063 **/ 1064static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1065{ 1066 1067 /* Do the reset outside of interrupt context */ 1068 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1069 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1070 e_warn(drv, "initiating reset due to tx timeout\n"); 1071 ixgbe_service_event_schedule(adapter); 1072 } 1073} 1074 1075/** 1076 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1077 * @netdev: network interface device structure 1078 * @queue_index: Tx queue to set 1079 * @maxrate: desired maximum transmit bitrate 1080 **/ 1081static int ixgbe_tx_maxrate(struct net_device *netdev, 1082 int queue_index, u32 maxrate) 1083{ 1084 struct ixgbe_adapter *adapter = netdev_priv(netdev); 1085 struct ixgbe_hw *hw = &adapter->hw; 1086 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1087 1088 if (!maxrate) 1089 return 0; 1090 1091 /* Calculate the rate factor values to set */ 1092 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1093 bcnrc_val /= maxrate; 1094 1095 /* clear everything but the rate factor */ 1096 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1097 IXGBE_RTTBCNRC_RF_DEC_MASK; 1098 1099 /* enable the rate scheduler */ 1100 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1101 1102 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1103 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1104 1105 return 0; 1106} 1107 1108/** 1109 * ixgbe_update_tx_ring_stats - Update Tx ring specific counters 1110 * @tx_ring: ring to update 1111 * @q_vector: queue vector ring belongs to 1112 * @pkts: number of processed packets 1113 * @bytes: number of processed bytes 1114 */ 1115void ixgbe_update_tx_ring_stats(struct ixgbe_ring *tx_ring, 1116 struct ixgbe_q_vector *q_vector, u64 pkts, 1117 u64 bytes) 1118{ 1119 u64_stats_update_begin(&tx_ring->syncp); 1120 tx_ring->stats.bytes += bytes; 1121 tx_ring->stats.packets += pkts; 1122 u64_stats_update_end(&tx_ring->syncp); 1123 q_vector->tx.total_bytes += bytes; 1124 q_vector->tx.total_packets += pkts; 1125} 1126 1127/** 1128 * ixgbe_update_rx_ring_stats - Update Rx ring specific counters 1129 * @rx_ring: ring to update 1130 * @q_vector: queue vector ring belongs to 1131 * @pkts: number of processed packets 1132 * @bytes: number of processed bytes 1133 */ 1134void ixgbe_update_rx_ring_stats(struct ixgbe_ring *rx_ring, 1135 struct ixgbe_q_vector *q_vector, u64 pkts, 1136 u64 bytes) 1137{ 1138 u64_stats_update_begin(&rx_ring->syncp); 1139 rx_ring->stats.bytes += bytes; 1140 rx_ring->stats.packets += pkts; 1141 u64_stats_update_end(&rx_ring->syncp); 1142 q_vector->rx.total_bytes += bytes; 1143 q_vector->rx.total_packets += pkts; 1144} 1145 1146/** 1147 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1148 * @q_vector: structure containing interrupt and ring information 1149 * @tx_ring: tx ring to clean 1150 * @napi_budget: Used to determine if we are in netpoll 1151 **/ 1152static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1153 struct ixgbe_ring *tx_ring, int napi_budget) 1154{ 1155 struct ixgbe_adapter *adapter = q_vector->adapter; 1156 struct ixgbe_tx_buffer *tx_buffer; 1157 union ixgbe_adv_tx_desc *tx_desc; 1158 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1159 unsigned int budget = q_vector->tx.work_limit; 1160 unsigned int i = tx_ring->next_to_clean; 1161 struct netdev_queue *txq; 1162 1163 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1164 return true; 1165 1166 tx_buffer = &tx_ring->tx_buffer_info[i]; 1167 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1168 i -= tx_ring->count; 1169 1170 do { 1171 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1172 1173 /* if next_to_watch is not set then there is no work pending */ 1174 if (!eop_desc) 1175 break; 1176 1177 /* prevent any other reads prior to eop_desc */ 1178 smp_rmb(); 1179 1180 /* if DD is not set pending work has not been completed */ 1181 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1182 break; 1183 1184 /* clear next_to_watch to prevent false hangs */ 1185 tx_buffer->next_to_watch = NULL; 1186 1187 /* update the statistics for this packet */ 1188 total_bytes += tx_buffer->bytecount; 1189 total_packets += tx_buffer->gso_segs; 1190 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1191 total_ipsec++; 1192 1193 /* free the skb */ 1194 if (ring_is_xdp(tx_ring)) 1195 xdp_return_frame(tx_buffer->xdpf); 1196 else 1197 napi_consume_skb(tx_buffer->skb, napi_budget); 1198 1199 /* unmap skb header data */ 1200 dma_unmap_single(tx_ring->dev, 1201 dma_unmap_addr(tx_buffer, dma), 1202 dma_unmap_len(tx_buffer, len), 1203 DMA_TO_DEVICE); 1204 1205 /* clear tx_buffer data */ 1206 dma_unmap_len_set(tx_buffer, len, 0); 1207 1208 /* unmap remaining buffers */ 1209 while (tx_desc != eop_desc) { 1210 tx_buffer++; 1211 tx_desc++; 1212 i++; 1213 if (unlikely(!i)) { 1214 i -= tx_ring->count; 1215 tx_buffer = tx_ring->tx_buffer_info; 1216 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1217 } 1218 1219 /* unmap any remaining paged data */ 1220 if (dma_unmap_len(tx_buffer, len)) { 1221 dma_unmap_page(tx_ring->dev, 1222 dma_unmap_addr(tx_buffer, dma), 1223 dma_unmap_len(tx_buffer, len), 1224 DMA_TO_DEVICE); 1225 dma_unmap_len_set(tx_buffer, len, 0); 1226 } 1227 } 1228 1229 /* move us one more past the eop_desc for start of next pkt */ 1230 tx_buffer++; 1231 tx_desc++; 1232 i++; 1233 if (unlikely(!i)) { 1234 i -= tx_ring->count; 1235 tx_buffer = tx_ring->tx_buffer_info; 1236 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1237 } 1238 1239 /* issue prefetch for next Tx descriptor */ 1240 prefetch(tx_desc); 1241 1242 /* update budget accounting */ 1243 budget--; 1244 } while (likely(budget)); 1245 1246 i += tx_ring->count; 1247 tx_ring->next_to_clean = i; 1248 ixgbe_update_tx_ring_stats(tx_ring, q_vector, total_packets, 1249 total_bytes); 1250 adapter->tx_ipsec += total_ipsec; 1251 1252 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1253 /* schedule immediate reset if we believe we hung */ 1254 struct ixgbe_hw *hw = &adapter->hw; 1255 e_err(drv, "Detected Tx Unit Hang %s\n" 1256 " Tx Queue <%d>\n" 1257 " TDH, TDT <%x>, <%x>\n" 1258 " next_to_use <%x>\n" 1259 " next_to_clean <%x>\n" 1260 "tx_buffer_info[next_to_clean]\n" 1261 " time_stamp <%lx>\n" 1262 " jiffies <%lx>\n", 1263 ring_is_xdp(tx_ring) ? "(XDP)" : "", 1264 tx_ring->queue_index, 1265 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1266 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1267 tx_ring->next_to_use, i, 1268 tx_ring->tx_buffer_info[i].time_stamp, jiffies); 1269 1270 if (!ring_is_xdp(tx_ring)) 1271 netif_stop_subqueue(tx_ring->netdev, 1272 tx_ring->queue_index); 1273 1274 e_info(probe, 1275 "tx hang %d detected on queue %d, resetting adapter\n", 1276 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1277 1278 /* schedule immediate reset if we believe we hung */ 1279 ixgbe_tx_timeout_reset(adapter); 1280 1281 /* the adapter is about to reset, no point in enabling stuff */ 1282 return true; 1283 } 1284 1285 if (ring_is_xdp(tx_ring)) 1286 return !!budget; 1287 1288#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1289 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1290 if (!__netif_txq_completed_wake(txq, total_packets, total_bytes, 1291 ixgbe_desc_unused(tx_ring), 1292 TX_WAKE_THRESHOLD, 1293 !netif_carrier_ok(tx_ring->netdev) || 1294 test_bit(__IXGBE_DOWN, &adapter->state))) 1295 ++tx_ring->tx_stats.restart_queue; 1296 1297 return !!budget; 1298} 1299 1300#ifdef CONFIG_IXGBE_DCA 1301static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1302 struct ixgbe_ring *tx_ring, 1303 int cpu) 1304{ 1305 struct ixgbe_hw *hw = &adapter->hw; 1306 u32 txctrl = 0; 1307 u16 reg_offset; 1308 1309 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1310 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1311 1312 switch (hw->mac.type) { 1313 case ixgbe_mac_82598EB: 1314 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1315 break; 1316 case ixgbe_mac_82599EB: 1317 case ixgbe_mac_X540: 1318 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1319 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1320 break; 1321 default: 1322 /* for unknown hardware do not write register */ 1323 return; 1324 } 1325 1326 /* 1327 * We can enable relaxed ordering for reads, but not writes when 1328 * DCA is enabled. This is due to a known issue in some chipsets 1329 * which will cause the DCA tag to be cleared. 1330 */ 1331 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1332 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1333 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1334 1335 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1336} 1337 1338static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1339 struct ixgbe_ring *rx_ring, 1340 int cpu) 1341{ 1342 struct ixgbe_hw *hw = &adapter->hw; 1343 u32 rxctrl = 0; 1344 u8 reg_idx = rx_ring->reg_idx; 1345 1346 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1347 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1348 1349 switch (hw->mac.type) { 1350 case ixgbe_mac_82599EB: 1351 case ixgbe_mac_X540: 1352 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1353 break; 1354 default: 1355 break; 1356 } 1357 1358 /* 1359 * We can enable relaxed ordering for reads, but not writes when 1360 * DCA is enabled. This is due to a known issue in some chipsets 1361 * which will cause the DCA tag to be cleared. 1362 */ 1363 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1364 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1365 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1366 1367 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1368} 1369 1370static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1371{ 1372 struct ixgbe_adapter *adapter = q_vector->adapter; 1373 struct ixgbe_ring *ring; 1374 int cpu = get_cpu(); 1375 1376 if (q_vector->cpu == cpu) 1377 goto out_no_update; 1378 1379 ixgbe_for_each_ring(ring, q_vector->tx) 1380 ixgbe_update_tx_dca(adapter, ring, cpu); 1381 1382 ixgbe_for_each_ring(ring, q_vector->rx) 1383 ixgbe_update_rx_dca(adapter, ring, cpu); 1384 1385 q_vector->cpu = cpu; 1386out_no_update: 1387 put_cpu(); 1388} 1389 1390static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1391{ 1392 int i; 1393 1394 /* always use CB2 mode, difference is masked in the CB driver */ 1395 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1397 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1398 else 1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1400 IXGBE_DCA_CTRL_DCA_DISABLE); 1401 1402 for (i = 0; i < adapter->num_q_vectors; i++) { 1403 adapter->q_vector[i]->cpu = -1; 1404 ixgbe_update_dca(adapter->q_vector[i]); 1405 } 1406} 1407 1408static int __ixgbe_notify_dca(struct device *dev, void *data) 1409{ 1410 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1411 unsigned long event = *(unsigned long *)data; 1412 1413 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1414 return 0; 1415 1416 switch (event) { 1417 case DCA_PROVIDER_ADD: 1418 /* if we're already enabled, don't do it again */ 1419 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1420 break; 1421 if (dca_add_requester(dev) == 0) { 1422 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1424 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1425 break; 1426 } 1427 fallthrough; /* DCA is disabled. */ 1428 case DCA_PROVIDER_REMOVE: 1429 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1430 dca_remove_requester(dev); 1431 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1432 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1433 IXGBE_DCA_CTRL_DCA_DISABLE); 1434 } 1435 break; 1436 } 1437 1438 return 0; 1439} 1440 1441#endif /* CONFIG_IXGBE_DCA */ 1442 1443#define IXGBE_RSS_L4_TYPES_MASK \ 1444 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1445 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1446 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1447 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1448 1449static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1450 union ixgbe_adv_rx_desc *rx_desc, 1451 struct sk_buff *skb) 1452{ 1453 u16 rss_type; 1454 1455 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1456 return; 1457 1458 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1459 IXGBE_RXDADV_RSSTYPE_MASK; 1460 1461 if (!rss_type) 1462 return; 1463 1464 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1465 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1466 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1467} 1468 1469#ifdef IXGBE_FCOE 1470/** 1471 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1472 * @ring: structure containing ring specific data 1473 * @rx_desc: advanced rx descriptor 1474 * 1475 * Returns : true if it is FCoE pkt 1476 */ 1477static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1478 union ixgbe_adv_rx_desc *rx_desc) 1479{ 1480 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1481 1482 return test_bit(__IXGBE_RX_FCOE, &ring->state) && 1483 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1484 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1485 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1486} 1487 1488#endif /* IXGBE_FCOE */ 1489/** 1490 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1491 * @ring: structure containing ring specific data 1492 * @rx_desc: current Rx descriptor being processed 1493 * @skb: skb currently being received and modified 1494 **/ 1495static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1496 union ixgbe_adv_rx_desc *rx_desc, 1497 struct sk_buff *skb) 1498{ 1499 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1500 bool encap_pkt = false; 1501 1502 skb_checksum_none_assert(skb); 1503 1504 /* Rx csum disabled */ 1505 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1506 return; 1507 1508 /* check for VXLAN and Geneve packets */ 1509 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1510 encap_pkt = true; 1511 skb->encapsulation = 1; 1512 } 1513 1514 /* if IP and error */ 1515 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1516 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1517 ring->rx_stats.csum_err++; 1518 return; 1519 } 1520 1521 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1522 return; 1523 1524 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1525 /* 1526 * 82599 errata, UDP frames with a 0 checksum can be marked as 1527 * checksum errors. 1528 */ 1529 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1530 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) 1531 return; 1532 1533 ring->rx_stats.csum_err++; 1534 return; 1535 } 1536 1537 /* It must be a TCP or UDP packet with a valid checksum */ 1538 skb->ip_summed = CHECKSUM_UNNECESSARY; 1539 if (encap_pkt) { 1540 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1541 return; 1542 1543 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1544 skb->ip_summed = CHECKSUM_NONE; 1545 return; 1546 } 1547 /* If we checked the outer header let the stack know */ 1548 skb->csum_level = 1; 1549 } 1550} 1551 1552static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1553{ 1554 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1555} 1556 1557static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1558 struct ixgbe_rx_buffer *bi) 1559{ 1560 struct page *page = bi->page; 1561 dma_addr_t dma; 1562 1563 /* since we are recycling buffers we should seldom need to alloc */ 1564 if (likely(page)) 1565 return true; 1566 1567 /* alloc new page for storage */ 1568 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1569 if (unlikely(!page)) { 1570 rx_ring->rx_stats.alloc_rx_page_failed++; 1571 return false; 1572 } 1573 1574 /* map page for use */ 1575 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1576 ixgbe_rx_pg_size(rx_ring), 1577 DMA_FROM_DEVICE, 1578 IXGBE_RX_DMA_ATTR); 1579 1580 /* 1581 * if mapping failed free memory back to system since 1582 * there isn't much point in holding memory we can't use 1583 */ 1584 if (dma_mapping_error(rx_ring->dev, dma)) { 1585 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1586 1587 rx_ring->rx_stats.alloc_rx_page_failed++; 1588 return false; 1589 } 1590 1591 bi->dma = dma; 1592 bi->page = page; 1593 bi->page_offset = rx_ring->rx_offset; 1594 page_ref_add(page, USHRT_MAX - 1); 1595 bi->pagecnt_bias = USHRT_MAX; 1596 rx_ring->rx_stats.alloc_rx_page++; 1597 1598 return true; 1599} 1600 1601/** 1602 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1603 * @rx_ring: ring to place buffers on 1604 * @cleaned_count: number of buffers to replace 1605 **/ 1606void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1607{ 1608 union ixgbe_adv_rx_desc *rx_desc; 1609 struct ixgbe_rx_buffer *bi; 1610 u16 i = rx_ring->next_to_use; 1611 u16 bufsz; 1612 1613 /* nothing to do */ 1614 if (!cleaned_count) 1615 return; 1616 1617 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1618 bi = &rx_ring->rx_buffer_info[i]; 1619 i -= rx_ring->count; 1620 1621 bufsz = ixgbe_rx_bufsz(rx_ring); 1622 1623 do { 1624 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1625 break; 1626 1627 /* sync the buffer for use by the device */ 1628 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1629 bi->page_offset, bufsz, 1630 DMA_FROM_DEVICE); 1631 1632 /* 1633 * Refresh the desc even if buffer_addrs didn't change 1634 * because each write-back erases this info. 1635 */ 1636 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1637 1638 rx_desc++; 1639 bi++; 1640 i++; 1641 if (unlikely(!i)) { 1642 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1643 bi = rx_ring->rx_buffer_info; 1644 i -= rx_ring->count; 1645 } 1646 1647 /* clear the length for the next_to_use descriptor */ 1648 rx_desc->wb.upper.length = 0; 1649 1650 cleaned_count--; 1651 } while (cleaned_count); 1652 1653 i += rx_ring->count; 1654 1655 if (rx_ring->next_to_use != i) { 1656 rx_ring->next_to_use = i; 1657 1658 /* update next to alloc since we have filled the ring */ 1659 rx_ring->next_to_alloc = i; 1660 1661 /* Force memory writes to complete before letting h/w 1662 * know there are new descriptors to fetch. (Only 1663 * applicable for weak-ordered memory model archs, 1664 * such as IA-64). 1665 */ 1666 wmb(); 1667 writel(i, rx_ring->tail); 1668 } 1669} 1670 1671static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1672 struct sk_buff *skb) 1673{ 1674 u16 hdr_len = skb_headlen(skb); 1675 1676 /* set gso_size to avoid messing up TCP MSS */ 1677 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1678 IXGBE_CB(skb)->append_cnt); 1679 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1680} 1681 1682static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1683 struct sk_buff *skb) 1684{ 1685 /* if append_cnt is 0 then frame is not RSC */ 1686 if (!IXGBE_CB(skb)->append_cnt) 1687 return; 1688 1689 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1690 rx_ring->rx_stats.rsc_flush++; 1691 1692 ixgbe_set_rsc_gso_size(rx_ring, skb); 1693 1694 /* gso_size is computed using append_cnt so always clear it last */ 1695 IXGBE_CB(skb)->append_cnt = 0; 1696} 1697 1698/** 1699 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1700 * @rx_ring: rx descriptor ring packet is being transacted on 1701 * @rx_desc: pointer to the EOP Rx descriptor 1702 * @skb: pointer to current skb being populated 1703 * 1704 * This function checks the ring, descriptor, and packet information in 1705 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1706 * other fields within the skb. 1707 **/ 1708void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1709 union ixgbe_adv_rx_desc *rx_desc, 1710 struct sk_buff *skb) 1711{ 1712 struct net_device *dev = rx_ring->netdev; 1713 u32 flags = rx_ring->q_vector->adapter->flags; 1714 1715 ixgbe_update_rsc_stats(rx_ring, skb); 1716 1717 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1718 1719 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1720 1721 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1722 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1723 1724 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1725 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1726 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1727 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1728 } 1729 1730 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1731 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1732 1733 /* record Rx queue, or update MACVLAN statistics */ 1734 if (netif_is_ixgbe(dev)) 1735 skb_record_rx_queue(skb, rx_ring->queue_index); 1736 else 1737 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1738 false); 1739 1740 skb->protocol = eth_type_trans(skb, dev); 1741} 1742 1743void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1744 struct sk_buff *skb) 1745{ 1746 napi_gro_receive(&q_vector->napi, skb); 1747} 1748 1749/** 1750 * ixgbe_is_non_eop - process handling of non-EOP buffers 1751 * @rx_ring: Rx ring being processed 1752 * @rx_desc: Rx descriptor for current buffer 1753 * @skb: Current socket buffer containing buffer in progress 1754 * 1755 * This function updates next to clean. If the buffer is an EOP buffer 1756 * this function exits returning false, otherwise it will place the 1757 * sk_buff in the next buffer to be chained and return true indicating 1758 * that this is in fact a non-EOP buffer. 1759 **/ 1760static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1761 union ixgbe_adv_rx_desc *rx_desc, 1762 struct sk_buff *skb) 1763{ 1764 u32 ntc = rx_ring->next_to_clean + 1; 1765 1766 /* fetch, update, and store next to clean */ 1767 ntc = (ntc < rx_ring->count) ? ntc : 0; 1768 rx_ring->next_to_clean = ntc; 1769 1770 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1771 1772 /* update RSC append count if present */ 1773 if (ring_is_rsc_enabled(rx_ring)) { 1774 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1775 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1776 1777 if (unlikely(rsc_enabled)) { 1778 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1779 1780 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1781 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1782 1783 /* update ntc based on RSC value */ 1784 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1785 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1786 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1787 } 1788 } 1789 1790 /* if we are the last buffer then there is nothing else to do */ 1791 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1792 return false; 1793 1794 /* place skb in next buffer to be received */ 1795 rx_ring->rx_buffer_info[ntc].skb = skb; 1796 rx_ring->rx_stats.non_eop_descs++; 1797 1798 return true; 1799} 1800 1801/** 1802 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1803 * @rx_ring: rx descriptor ring packet is being transacted on 1804 * @skb: pointer to current skb being adjusted 1805 * 1806 * This function is an ixgbe specific version of __pskb_pull_tail. The 1807 * main difference between this version and the original function is that 1808 * this function can make several assumptions about the state of things 1809 * that allow for significant optimizations versus the standard function. 1810 * As a result we can do things like drop a frag and maintain an accurate 1811 * truesize for the skb. 1812 */ 1813static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1814 struct sk_buff *skb) 1815{ 1816 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1817 unsigned char *va; 1818 unsigned int pull_len; 1819 1820 /* 1821 * it is valid to use page_address instead of kmap since we are 1822 * working with pages allocated out of the lomem pool per 1823 * alloc_page(GFP_ATOMIC) 1824 */ 1825 va = skb_frag_address(frag); 1826 1827 /* 1828 * we need the header to contain the greater of either ETH_HLEN or 1829 * 60 bytes if the skb->len is less than 60 for skb_pad. 1830 */ 1831 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 1832 1833 /* align pull length to size of long to optimize memcpy performance */ 1834 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 1835 1836 /* update all of the pointers */ 1837 skb_frag_size_sub(frag, pull_len); 1838 skb_frag_off_add(frag, pull_len); 1839 skb->data_len -= pull_len; 1840 skb->tail += pull_len; 1841} 1842 1843/** 1844 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 1845 * @rx_ring: rx descriptor ring packet is being transacted on 1846 * @skb: pointer to current skb being updated 1847 * 1848 * This function provides a basic DMA sync up for the first fragment of an 1849 * skb. The reason for doing this is that the first fragment cannot be 1850 * unmapped until we have reached the end of packet descriptor for a buffer 1851 * chain. 1852 */ 1853static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 1854 struct sk_buff *skb) 1855{ 1856 if (ring_uses_build_skb(rx_ring)) { 1857 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1; 1858 unsigned long offset = (unsigned long)(skb->data) & mask; 1859 1860 dma_sync_single_range_for_cpu(rx_ring->dev, 1861 IXGBE_CB(skb)->dma, 1862 offset, 1863 skb_headlen(skb), 1864 DMA_FROM_DEVICE); 1865 } else { 1866 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1867 1868 dma_sync_single_range_for_cpu(rx_ring->dev, 1869 IXGBE_CB(skb)->dma, 1870 skb_frag_off(frag), 1871 skb_frag_size(frag), 1872 DMA_FROM_DEVICE); 1873 } 1874 1875 /* If the page was released, just unmap it. */ 1876 if (unlikely(IXGBE_CB(skb)->page_released)) { 1877 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 1878 ixgbe_rx_pg_size(rx_ring), 1879 DMA_FROM_DEVICE, 1880 IXGBE_RX_DMA_ATTR); 1881 } 1882} 1883 1884/** 1885 * ixgbe_cleanup_headers - Correct corrupted or empty headers 1886 * @rx_ring: rx descriptor ring packet is being transacted on 1887 * @rx_desc: pointer to the EOP Rx descriptor 1888 * @skb: pointer to current skb being fixed 1889 * 1890 * Check if the skb is valid in the XDP case it will be an error pointer. 1891 * Return true in this case to abort processing and advance to next 1892 * descriptor. 1893 * 1894 * Check for corrupted packet headers caused by senders on the local L2 1895 * embedded NIC switch not setting up their Tx Descriptors right. These 1896 * should be very rare. 1897 * 1898 * Also address the case where we are pulling data in on pages only 1899 * and as such no data is present in the skb header. 1900 * 1901 * In addition if skb is not at least 60 bytes we need to pad it so that 1902 * it is large enough to qualify as a valid Ethernet frame. 1903 * 1904 * Returns true if an error was encountered and skb was freed. 1905 **/ 1906bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 1907 union ixgbe_adv_rx_desc *rx_desc, 1908 struct sk_buff *skb) 1909{ 1910 struct net_device *netdev = rx_ring->netdev; 1911 1912 /* XDP packets use error pointer so abort at this point */ 1913 if (IS_ERR(skb)) 1914 return true; 1915 1916 /* Verify netdev is present, and that packet does not have any 1917 * errors that would be unacceptable to the netdev. 1918 */ 1919 if (!netdev || 1920 (unlikely(ixgbe_test_staterr(rx_desc, 1921 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 1922 !(netdev->features & NETIF_F_RXALL)))) { 1923 dev_kfree_skb_any(skb); 1924 return true; 1925 } 1926 1927 /* place header in linear portion of buffer */ 1928 if (!skb_headlen(skb)) 1929 ixgbe_pull_tail(rx_ring, skb); 1930 1931#ifdef IXGBE_FCOE 1932 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 1933 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 1934 return false; 1935 1936#endif 1937 /* if eth_skb_pad returns an error the skb was freed */ 1938 if (eth_skb_pad(skb)) 1939 return true; 1940 1941 return false; 1942} 1943 1944/** 1945 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 1946 * @rx_ring: rx descriptor ring to store buffers on 1947 * @old_buff: donor buffer to have page reused 1948 * 1949 * Synchronizes page for reuse by the adapter 1950 **/ 1951static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 1952 struct ixgbe_rx_buffer *old_buff) 1953{ 1954 struct ixgbe_rx_buffer *new_buff; 1955 u16 nta = rx_ring->next_to_alloc; 1956 1957 new_buff = &rx_ring->rx_buffer_info[nta]; 1958 1959 /* update, and store next to alloc */ 1960 nta++; 1961 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1962 1963 /* Transfer page from old buffer to new buffer. 1964 * Move each member individually to avoid possible store 1965 * forwarding stalls and unnecessary copy of skb. 1966 */ 1967 new_buff->dma = old_buff->dma; 1968 new_buff->page = old_buff->page; 1969 new_buff->page_offset = old_buff->page_offset; 1970 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1971} 1972 1973static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 1974 int rx_buffer_pgcnt) 1975{ 1976 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1977 struct page *page = rx_buffer->page; 1978 1979 /* avoid re-using remote and pfmemalloc pages */ 1980 if (!dev_page_is_reusable(page)) 1981 return false; 1982 1983#if (PAGE_SIZE < 8192) 1984 /* if we are only owner of page we can reuse it */ 1985 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 1986 return false; 1987#else 1988 /* The last offset is a bit aggressive in that we assume the 1989 * worst case of FCoE being enabled and using a 3K buffer. 1990 * However this should have minimal impact as the 1K extra is 1991 * still less than one buffer in size. 1992 */ 1993#define IXGBE_LAST_OFFSET \ 1994 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 1995 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 1996 return false; 1997#endif 1998 1999 /* If we have drained the page fragment pool we need to update 2000 * the pagecnt_bias and page count so that we fully restock the 2001 * number of references the driver holds. 2002 */ 2003 if (unlikely(pagecnt_bias == 1)) { 2004 page_ref_add(page, USHRT_MAX - 1); 2005 rx_buffer->pagecnt_bias = USHRT_MAX; 2006 } 2007 2008 return true; 2009} 2010 2011/** 2012 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2013 * @rx_ring: rx descriptor ring to transact packets on 2014 * @rx_buffer: buffer containing page to add 2015 * @skb: sk_buff to place the data into 2016 * @size: size of data in rx_buffer 2017 * 2018 * This function will add the data contained in rx_buffer->page to the skb. 2019 * This is done either through a direct copy if the data in the buffer is 2020 * less than the skb header size, otherwise it will just attach the page as 2021 * a frag to the skb. 2022 * 2023 * The function will then update the page offset if necessary and return 2024 * true if the buffer can be reused by the adapter. 2025 **/ 2026static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2027 struct ixgbe_rx_buffer *rx_buffer, 2028 struct sk_buff *skb, 2029 unsigned int size) 2030{ 2031#if (PAGE_SIZE < 8192) 2032 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2033#else 2034 unsigned int truesize = rx_ring->rx_offset ? 2035 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2036 SKB_DATA_ALIGN(size); 2037#endif 2038 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2039 rx_buffer->page_offset, size, truesize); 2040#if (PAGE_SIZE < 8192) 2041 rx_buffer->page_offset ^= truesize; 2042#else 2043 rx_buffer->page_offset += truesize; 2044#endif 2045} 2046 2047static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2048 union ixgbe_adv_rx_desc *rx_desc, 2049 struct sk_buff **skb, 2050 const unsigned int size, 2051 int *rx_buffer_pgcnt) 2052{ 2053 struct ixgbe_rx_buffer *rx_buffer; 2054 2055 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2056 *rx_buffer_pgcnt = 2057#if (PAGE_SIZE < 8192) 2058 page_count(rx_buffer->page); 2059#else 2060 0; 2061#endif 2062 prefetchw(rx_buffer->page); 2063 *skb = rx_buffer->skb; 2064 2065 /* Delay unmapping of the first packet. It carries the header 2066 * information, HW may still access the header after the writeback. 2067 * Only unmap it when EOP is reached 2068 */ 2069 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2070 if (!*skb) 2071 goto skip_sync; 2072 } else { 2073 if (*skb) 2074 ixgbe_dma_sync_frag(rx_ring, *skb); 2075 } 2076 2077 /* we are reusing so sync this buffer for CPU use */ 2078 dma_sync_single_range_for_cpu(rx_ring->dev, 2079 rx_buffer->dma, 2080 rx_buffer->page_offset, 2081 size, 2082 DMA_FROM_DEVICE); 2083skip_sync: 2084 rx_buffer->pagecnt_bias--; 2085 2086 return rx_buffer; 2087} 2088 2089static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2090 struct ixgbe_rx_buffer *rx_buffer, 2091 struct sk_buff *skb, 2092 int rx_buffer_pgcnt) 2093{ 2094 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2095 /* hand second half of page back to the ring */ 2096 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2097 } else { 2098 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2099 /* the page has been released from the ring */ 2100 IXGBE_CB(skb)->page_released = true; 2101 } else { 2102 /* we are not reusing the buffer so unmap it */ 2103 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2104 ixgbe_rx_pg_size(rx_ring), 2105 DMA_FROM_DEVICE, 2106 IXGBE_RX_DMA_ATTR); 2107 } 2108 __page_frag_cache_drain(rx_buffer->page, 2109 rx_buffer->pagecnt_bias); 2110 } 2111 2112 /* clear contents of rx_buffer */ 2113 rx_buffer->page = NULL; 2114 rx_buffer->skb = NULL; 2115} 2116 2117static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2118 struct ixgbe_rx_buffer *rx_buffer, 2119 struct xdp_buff *xdp, 2120 union ixgbe_adv_rx_desc *rx_desc) 2121{ 2122 unsigned int size = xdp->data_end - xdp->data; 2123#if (PAGE_SIZE < 8192) 2124 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2125#else 2126 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2127 xdp->data_hard_start); 2128#endif 2129 struct sk_buff *skb; 2130 2131 /* prefetch first cache line of first page */ 2132 net_prefetch(xdp->data); 2133 2134 /* Note, we get here by enabling legacy-rx via: 2135 * 2136 * ethtool --set-priv-flags <dev> legacy-rx on 2137 * 2138 * In this mode, we currently get 0 extra XDP headroom as 2139 * opposed to having legacy-rx off, where we process XDP 2140 * packets going to stack via ixgbe_build_skb(). The latter 2141 * provides us currently with 192 bytes of headroom. 2142 * 2143 * For ixgbe_construct_skb() mode it means that the 2144 * xdp->data_meta will always point to xdp->data, since 2145 * the helper cannot expand the head. Should this ever 2146 * change in future for legacy-rx mode on, then lets also 2147 * add xdp->data_meta handling here. 2148 */ 2149 2150 /* allocate a skb to store the frags */ 2151 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2152 if (unlikely(!skb)) 2153 return NULL; 2154 2155 if (size > IXGBE_RX_HDR_SIZE) { 2156 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2157 IXGBE_CB(skb)->dma = rx_buffer->dma; 2158 2159 skb_add_rx_frag(skb, 0, rx_buffer->page, 2160 xdp->data - page_address(rx_buffer->page), 2161 size, truesize); 2162#if (PAGE_SIZE < 8192) 2163 rx_buffer->page_offset ^= truesize; 2164#else 2165 rx_buffer->page_offset += truesize; 2166#endif 2167 } else { 2168 memcpy(__skb_put(skb, size), 2169 xdp->data, ALIGN(size, sizeof(long))); 2170 rx_buffer->pagecnt_bias++; 2171 } 2172 2173 return skb; 2174} 2175 2176static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2177 struct ixgbe_rx_buffer *rx_buffer, 2178 struct xdp_buff *xdp, 2179 union ixgbe_adv_rx_desc *rx_desc) 2180{ 2181 unsigned int metasize = xdp->data - xdp->data_meta; 2182#if (PAGE_SIZE < 8192) 2183 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2184#else 2185 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2186 SKB_DATA_ALIGN(xdp->data_end - 2187 xdp->data_hard_start); 2188#endif 2189 struct sk_buff *skb; 2190 2191 /* Prefetch first cache line of first page. If xdp->data_meta 2192 * is unused, this points extactly as xdp->data, otherwise we 2193 * likely have a consumer accessing first few bytes of meta 2194 * data, and then actual data. 2195 */ 2196 net_prefetch(xdp->data_meta); 2197 2198 /* build an skb to around the page buffer */ 2199 skb = napi_build_skb(xdp->data_hard_start, truesize); 2200 if (unlikely(!skb)) 2201 return NULL; 2202 2203 /* update pointers within the skb to store the data */ 2204 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2205 __skb_put(skb, xdp->data_end - xdp->data); 2206 if (metasize) 2207 skb_metadata_set(skb, metasize); 2208 2209 /* record DMA address if this is the start of a chain of buffers */ 2210 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2211 IXGBE_CB(skb)->dma = rx_buffer->dma; 2212 2213 /* update buffer offset */ 2214#if (PAGE_SIZE < 8192) 2215 rx_buffer->page_offset ^= truesize; 2216#else 2217 rx_buffer->page_offset += truesize; 2218#endif 2219 2220 return skb; 2221} 2222 2223static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2224 struct ixgbe_ring *rx_ring, 2225 struct xdp_buff *xdp) 2226{ 2227 int err, result = IXGBE_XDP_PASS; 2228 struct bpf_prog *xdp_prog; 2229 struct ixgbe_ring *ring; 2230 struct xdp_frame *xdpf; 2231 u32 act; 2232 2233 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2234 2235 if (!xdp_prog) 2236 goto xdp_out; 2237 2238 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2239 2240 act = bpf_prog_run_xdp(xdp_prog, xdp); 2241 switch (act) { 2242 case XDP_PASS: 2243 break; 2244 case XDP_TX: 2245 xdpf = xdp_convert_buff_to_frame(xdp); 2246 if (unlikely(!xdpf)) 2247 goto out_failure; 2248 ring = ixgbe_determine_xdp_ring(adapter); 2249 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2250 spin_lock(&ring->tx_lock); 2251 result = ixgbe_xmit_xdp_ring(ring, xdpf); 2252 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2253 spin_unlock(&ring->tx_lock); 2254 if (result == IXGBE_XDP_CONSUMED) 2255 goto out_failure; 2256 break; 2257 case XDP_REDIRECT: 2258 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2259 if (err) 2260 goto out_failure; 2261 result = IXGBE_XDP_REDIR; 2262 break; 2263 default: 2264 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2265 fallthrough; 2266 case XDP_ABORTED: 2267out_failure: 2268 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2269 fallthrough; /* handle aborts by dropping packet */ 2270 case XDP_DROP: 2271 result = IXGBE_XDP_CONSUMED; 2272 break; 2273 } 2274xdp_out: 2275 return ERR_PTR(-result); 2276} 2277 2278static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2279 unsigned int size) 2280{ 2281 unsigned int truesize; 2282 2283#if (PAGE_SIZE < 8192) 2284 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2285#else 2286 truesize = rx_ring->rx_offset ? 2287 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2288 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2289 SKB_DATA_ALIGN(size); 2290#endif 2291 return truesize; 2292} 2293 2294static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2295 struct ixgbe_rx_buffer *rx_buffer, 2296 unsigned int size) 2297{ 2298 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2299#if (PAGE_SIZE < 8192) 2300 rx_buffer->page_offset ^= truesize; 2301#else 2302 rx_buffer->page_offset += truesize; 2303#endif 2304} 2305 2306/** 2307 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2308 * @q_vector: structure containing interrupt and ring information 2309 * @rx_ring: rx descriptor ring to transact packets on 2310 * @budget: Total limit on number of packets to process 2311 * 2312 * This function provides a "bounce buffer" approach to Rx interrupt 2313 * processing. The advantage to this is that on systems that have 2314 * expensive overhead for IOMMU access this provides a means of avoiding 2315 * it by maintaining the mapping of the page to the syste. 2316 * 2317 * Returns amount of work completed 2318 **/ 2319static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2320 struct ixgbe_ring *rx_ring, 2321 const int budget) 2322{ 2323 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2324 struct ixgbe_adapter *adapter = q_vector->adapter; 2325#ifdef IXGBE_FCOE 2326 int ddp_bytes; 2327 unsigned int mss = 0; 2328#endif /* IXGBE_FCOE */ 2329 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2330 unsigned int offset = rx_ring->rx_offset; 2331 unsigned int xdp_xmit = 0; 2332 struct xdp_buff xdp; 2333 2334 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2335#if (PAGE_SIZE < 8192) 2336 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2337#endif 2338 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2339 2340 while (likely(total_rx_packets < budget)) { 2341 union ixgbe_adv_rx_desc *rx_desc; 2342 struct ixgbe_rx_buffer *rx_buffer; 2343 struct sk_buff *skb; 2344 int rx_buffer_pgcnt; 2345 unsigned int size; 2346 2347 /* return some buffers to hardware, one at a time is too slow */ 2348 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2349 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2350 cleaned_count = 0; 2351 } 2352 2353 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2354 size = le16_to_cpu(rx_desc->wb.upper.length); 2355 if (!size) 2356 break; 2357 2358 /* This memory barrier is needed to keep us from reading 2359 * any other fields out of the rx_desc until we know the 2360 * descriptor has been written back 2361 */ 2362 dma_rmb(); 2363 2364 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2365 2366 /* retrieve a buffer from the ring */ 2367 if (!skb) { 2368 unsigned char *hard_start; 2369 2370 hard_start = page_address(rx_buffer->page) + 2371 rx_buffer->page_offset - offset; 2372 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2373 xdp_buff_clear_frags_flag(&xdp); 2374#if (PAGE_SIZE > 4096) 2375 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2376 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2377#endif 2378 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2379 } 2380 2381 if (IS_ERR(skb)) { 2382 unsigned int xdp_res = -PTR_ERR(skb); 2383 2384 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2385 xdp_xmit |= xdp_res; 2386 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2387 } else { 2388 rx_buffer->pagecnt_bias++; 2389 } 2390 total_rx_packets++; 2391 total_rx_bytes += size; 2392 } else if (skb) { 2393 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2394 } else if (ring_uses_build_skb(rx_ring)) { 2395 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2396 &xdp, rx_desc); 2397 } else { 2398 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2399 &xdp, rx_desc); 2400 } 2401 2402 /* exit if we failed to retrieve a buffer */ 2403 if (!skb) { 2404 rx_ring->rx_stats.alloc_rx_buff_failed++; 2405 rx_buffer->pagecnt_bias++; 2406 break; 2407 } 2408 2409 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2410 cleaned_count++; 2411 2412 /* place incomplete frames back on ring for completion */ 2413 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2414 continue; 2415 2416 /* verify the packet layout is correct */ 2417 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2418 continue; 2419 2420 /* probably a little skewed due to removing CRC */ 2421 total_rx_bytes += skb->len; 2422 2423 /* populate checksum, timestamp, VLAN, and protocol */ 2424 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2425 2426#ifdef IXGBE_FCOE 2427 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2428 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2429 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2430 /* include DDPed FCoE data */ 2431 if (ddp_bytes > 0) { 2432 if (!mss) { 2433 mss = rx_ring->netdev->mtu - 2434 sizeof(struct fcoe_hdr) - 2435 sizeof(struct fc_frame_header) - 2436 sizeof(struct fcoe_crc_eof); 2437 if (mss > 512) 2438 mss &= ~511; 2439 } 2440 total_rx_bytes += ddp_bytes; 2441 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2442 mss); 2443 } 2444 if (!ddp_bytes) { 2445 dev_kfree_skb_any(skb); 2446 continue; 2447 } 2448 } 2449 2450#endif /* IXGBE_FCOE */ 2451 ixgbe_rx_skb(q_vector, skb); 2452 2453 /* update budget accounting */ 2454 total_rx_packets++; 2455 } 2456 2457 if (xdp_xmit & IXGBE_XDP_REDIR) 2458 xdp_do_flush(); 2459 2460 if (xdp_xmit & IXGBE_XDP_TX) { 2461 struct ixgbe_ring *ring = ixgbe_determine_xdp_ring(adapter); 2462 2463 ixgbe_xdp_ring_update_tail_locked(ring); 2464 } 2465 2466 ixgbe_update_rx_ring_stats(rx_ring, q_vector, total_rx_packets, 2467 total_rx_bytes); 2468 2469 return total_rx_packets; 2470} 2471 2472/** 2473 * ixgbe_configure_msix - Configure MSI-X hardware 2474 * @adapter: board private structure 2475 * 2476 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2477 * interrupts. 2478 **/ 2479static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2480{ 2481 struct ixgbe_q_vector *q_vector; 2482 int v_idx; 2483 u32 mask; 2484 2485 /* Populate MSIX to EITR Select */ 2486 if (adapter->num_vfs > 32) { 2487 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2488 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2489 } 2490 2491 /* 2492 * Populate the IVAR table and set the ITR values to the 2493 * corresponding register. 2494 */ 2495 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2496 struct ixgbe_ring *ring; 2497 q_vector = adapter->q_vector[v_idx]; 2498 2499 ixgbe_for_each_ring(ring, q_vector->rx) 2500 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2501 2502 ixgbe_for_each_ring(ring, q_vector->tx) 2503 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2504 2505 ixgbe_write_eitr(q_vector); 2506 } 2507 2508 switch (adapter->hw.mac.type) { 2509 case ixgbe_mac_82598EB: 2510 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2511 v_idx); 2512 break; 2513 case ixgbe_mac_82599EB: 2514 case ixgbe_mac_X540: 2515 case ixgbe_mac_X550: 2516 case ixgbe_mac_X550EM_x: 2517 case ixgbe_mac_x550em_a: 2518 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2519 break; 2520 default: 2521 break; 2522 } 2523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2524 2525 /* set up to autoclear timer, and the vectors */ 2526 mask = IXGBE_EIMS_ENABLE_MASK; 2527 mask &= ~(IXGBE_EIMS_OTHER | 2528 IXGBE_EIMS_MAILBOX | 2529 IXGBE_EIMS_LSC); 2530 2531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2532} 2533 2534/** 2535 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2536 * @q_vector: structure containing interrupt and ring information 2537 * @ring_container: structure containing ring performance data 2538 * 2539 * Stores a new ITR value based on packets and byte 2540 * counts during the last interrupt. The advantage of per interrupt 2541 * computation is faster updates and more accurate ITR for the current 2542 * traffic pattern. Constants in this function were computed 2543 * based on theoretical maximum wire speed and thresholds were set based 2544 * on testing data as well as attempting to minimize response time 2545 * while increasing bulk throughput. 2546 **/ 2547static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2548 struct ixgbe_ring_container *ring_container) 2549{ 2550 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2551 IXGBE_ITR_ADAPTIVE_LATENCY; 2552 unsigned int avg_wire_size, packets, bytes; 2553 unsigned long next_update = jiffies; 2554 2555 /* If we don't have any rings just leave ourselves set for maximum 2556 * possible latency so we take ourselves out of the equation. 2557 */ 2558 if (!ring_container->ring) 2559 return; 2560 2561 /* If we didn't update within up to 1 - 2 jiffies we can assume 2562 * that either packets are coming in so slow there hasn't been 2563 * any work, or that there is so much work that NAPI is dealing 2564 * with interrupt moderation and we don't need to do anything. 2565 */ 2566 if (time_after(next_update, ring_container->next_update)) 2567 goto clear_counts; 2568 2569 packets = ring_container->total_packets; 2570 2571 /* We have no packets to actually measure against. This means 2572 * either one of the other queues on this vector is active or 2573 * we are a Tx queue doing TSO with too high of an interrupt rate. 2574 * 2575 * When this occurs just tick up our delay by the minimum value 2576 * and hope that this extra delay will prevent us from being called 2577 * without any work on our queue. 2578 */ 2579 if (!packets) { 2580 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2581 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2582 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2583 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2584 goto clear_counts; 2585 } 2586 2587 bytes = ring_container->total_bytes; 2588 2589 /* If packets are less than 4 or bytes are less than 9000 assume 2590 * insufficient data to use bulk rate limiting approach. We are 2591 * likely latency driven. 2592 */ 2593 if (packets < 4 && bytes < 9000) { 2594 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2595 goto adjust_by_size; 2596 } 2597 2598 /* Between 4 and 48 we can assume that our current interrupt delay 2599 * is only slightly too low. As such we should increase it by a small 2600 * fixed amount. 2601 */ 2602 if (packets < 48) { 2603 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2604 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2605 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2606 goto clear_counts; 2607 } 2608 2609 /* Between 48 and 96 is our "goldilocks" zone where we are working 2610 * out "just right". Just report that our current ITR is good for us. 2611 */ 2612 if (packets < 96) { 2613 itr = q_vector->itr >> 2; 2614 goto clear_counts; 2615 } 2616 2617 /* If packet count is 96 or greater we are likely looking at a slight 2618 * overrun of the delay we want. Try halving our delay to see if that 2619 * will cut the number of packets in half per interrupt. 2620 */ 2621 if (packets < 256) { 2622 itr = q_vector->itr >> 3; 2623 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2624 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2625 goto clear_counts; 2626 } 2627 2628 /* The paths below assume we are dealing with a bulk ITR since number 2629 * of packets is 256 or greater. We are just going to have to compute 2630 * a value and try to bring the count under control, though for smaller 2631 * packet sizes there isn't much we can do as NAPI polling will likely 2632 * be kicking in sooner rather than later. 2633 */ 2634 itr = IXGBE_ITR_ADAPTIVE_BULK; 2635 2636adjust_by_size: 2637 /* If packet counts are 256 or greater we can assume we have a gross 2638 * overestimation of what the rate should be. Instead of trying to fine 2639 * tune it just use the formula below to try and dial in an exact value 2640 * give the current packet size of the frame. 2641 */ 2642 avg_wire_size = bytes / packets; 2643 2644 /* The following is a crude approximation of: 2645 * wmem_default / (size + overhead) = desired_pkts_per_int 2646 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2647 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2648 * 2649 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2650 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2651 * formula down to 2652 * 2653 * (170 * (size + 24)) / (size + 640) = ITR 2654 * 2655 * We first do some math on the packet size and then finally bitshift 2656 * by 8 after rounding up. We also have to account for PCIe link speed 2657 * difference as ITR scales based on this. 2658 */ 2659 if (avg_wire_size <= 60) { 2660 /* Start at 50k ints/sec */ 2661 avg_wire_size = 5120; 2662 } else if (avg_wire_size <= 316) { 2663 /* 50K ints/sec to 16K ints/sec */ 2664 avg_wire_size *= 40; 2665 avg_wire_size += 2720; 2666 } else if (avg_wire_size <= 1084) { 2667 /* 16K ints/sec to 9.2K ints/sec */ 2668 avg_wire_size *= 15; 2669 avg_wire_size += 11452; 2670 } else if (avg_wire_size < 1968) { 2671 /* 9.2K ints/sec to 8K ints/sec */ 2672 avg_wire_size *= 5; 2673 avg_wire_size += 22420; 2674 } else { 2675 /* plateau at a limit of 8K ints/sec */ 2676 avg_wire_size = 32256; 2677 } 2678 2679 /* If we are in low latency mode half our delay which doubles the rate 2680 * to somewhere between 100K to 16K ints/sec 2681 */ 2682 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2683 avg_wire_size >>= 1; 2684 2685 /* Resultant value is 256 times larger than it needs to be. This 2686 * gives us room to adjust the value as needed to either increase 2687 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2688 * 2689 * Use addition as we have already recorded the new latency flag 2690 * for the ITR value. 2691 */ 2692 switch (q_vector->adapter->link_speed) { 2693 case IXGBE_LINK_SPEED_10GB_FULL: 2694 case IXGBE_LINK_SPEED_100_FULL: 2695 default: 2696 itr += DIV_ROUND_UP(avg_wire_size, 2697 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2698 IXGBE_ITR_ADAPTIVE_MIN_INC; 2699 break; 2700 case IXGBE_LINK_SPEED_2_5GB_FULL: 2701 case IXGBE_LINK_SPEED_1GB_FULL: 2702 case IXGBE_LINK_SPEED_10_FULL: 2703 if (avg_wire_size > 8064) 2704 avg_wire_size = 8064; 2705 itr += DIV_ROUND_UP(avg_wire_size, 2706 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2707 IXGBE_ITR_ADAPTIVE_MIN_INC; 2708 break; 2709 } 2710 2711clear_counts: 2712 /* write back value */ 2713 ring_container->itr = itr; 2714 2715 /* next update should occur within next jiffy */ 2716 ring_container->next_update = next_update + 1; 2717 2718 ring_container->total_bytes = 0; 2719 ring_container->total_packets = 0; 2720} 2721 2722/** 2723 * ixgbe_write_eitr - write EITR register in hardware specific way 2724 * @q_vector: structure containing interrupt and ring information 2725 * 2726 * This function is made to be called by ethtool and by the driver 2727 * when it needs to update EITR registers at runtime. Hardware 2728 * specific quirks/differences are taken care of here. 2729 */ 2730void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2731{ 2732 struct ixgbe_adapter *adapter = q_vector->adapter; 2733 struct ixgbe_hw *hw = &adapter->hw; 2734 int v_idx = q_vector->v_idx; 2735 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2736 2737 switch (adapter->hw.mac.type) { 2738 case ixgbe_mac_82598EB: 2739 /* must write high and low 16 bits to reset counter */ 2740 itr_reg |= (itr_reg << 16); 2741 break; 2742 case ixgbe_mac_82599EB: 2743 case ixgbe_mac_X540: 2744 case ixgbe_mac_X550: 2745 case ixgbe_mac_X550EM_x: 2746 case ixgbe_mac_x550em_a: 2747 /* 2748 * set the WDIS bit to not clear the timer bits and cause an 2749 * immediate assertion of the interrupt 2750 */ 2751 itr_reg |= IXGBE_EITR_CNT_WDIS; 2752 break; 2753 default: 2754 break; 2755 } 2756 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2757} 2758 2759static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2760{ 2761 u32 new_itr; 2762 2763 ixgbe_update_itr(q_vector, &q_vector->tx); 2764 ixgbe_update_itr(q_vector, &q_vector->rx); 2765 2766 /* use the smallest value of new ITR delay calculations */ 2767 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2768 2769 /* Clear latency flag if set, shift into correct position */ 2770 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2771 new_itr <<= 2; 2772 2773 if (new_itr != q_vector->itr) { 2774 /* save the algorithm value here */ 2775 q_vector->itr = new_itr; 2776 2777 ixgbe_write_eitr(q_vector); 2778 } 2779} 2780 2781/** 2782 * ixgbe_check_overtemp_subtask - check for over temperature 2783 * @adapter: pointer to adapter 2784 **/ 2785static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2786{ 2787 struct ixgbe_hw *hw = &adapter->hw; 2788 u32 eicr = adapter->interrupt_event; 2789 2790 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2791 return; 2792 2793 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2794 return; 2795 2796 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2797 2798 switch (hw->device_id) { 2799 case IXGBE_DEV_ID_82599_T3_LOM: 2800 /* 2801 * Since the warning interrupt is for both ports 2802 * we don't have to check if: 2803 * - This interrupt wasn't for our port. 2804 * - We may have missed the interrupt so always have to 2805 * check if we got a LSC 2806 */ 2807 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2808 !(eicr & IXGBE_EICR_LSC)) 2809 return; 2810 2811 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2812 u32 speed; 2813 bool link_up = false; 2814 2815 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2816 2817 if (link_up) 2818 return; 2819 } 2820 2821 /* Check if this is not due to overtemp */ 2822 if (!hw->phy.ops.check_overtemp(hw)) 2823 return; 2824 2825 break; 2826 case IXGBE_DEV_ID_X550EM_A_1G_T: 2827 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 2828 if (!hw->phy.ops.check_overtemp(hw)) 2829 return; 2830 break; 2831 default: 2832 if (adapter->hw.mac.type >= ixgbe_mac_X540) 2833 return; 2834 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 2835 return; 2836 break; 2837 } 2838 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2839 2840 adapter->interrupt_event = 0; 2841} 2842 2843static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 2844{ 2845 struct ixgbe_hw *hw = &adapter->hw; 2846 2847 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 2848 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2849 e_crit(probe, "Fan has stopped, replace the adapter\n"); 2850 /* write to clear the interrupt */ 2851 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2852 } 2853} 2854 2855static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 2856{ 2857 struct ixgbe_hw *hw = &adapter->hw; 2858 2859 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 2860 return; 2861 2862 switch (adapter->hw.mac.type) { 2863 case ixgbe_mac_82599EB: 2864 /* 2865 * Need to check link state so complete overtemp check 2866 * on service task 2867 */ 2868 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 2869 (eicr & IXGBE_EICR_LSC)) && 2870 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 2871 adapter->interrupt_event = eicr; 2872 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2873 ixgbe_service_event_schedule(adapter); 2874 return; 2875 } 2876 return; 2877 case ixgbe_mac_x550em_a: 2878 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 2879 adapter->interrupt_event = eicr; 2880 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2881 ixgbe_service_event_schedule(adapter); 2882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 2883 IXGBE_EICR_GPI_SDP0_X550EM_a); 2884 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 2885 IXGBE_EICR_GPI_SDP0_X550EM_a); 2886 } 2887 return; 2888 case ixgbe_mac_X550: 2889 case ixgbe_mac_X540: 2890 if (!(eicr & IXGBE_EICR_TS)) 2891 return; 2892 break; 2893 default: 2894 return; 2895 } 2896 2897 e_crit(drv, "%s\n", ixgbe_overheat_msg); 2898} 2899 2900static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 2901{ 2902 switch (hw->mac.type) { 2903 case ixgbe_mac_82598EB: 2904 if (hw->phy.type == ixgbe_phy_nl) 2905 return true; 2906 return false; 2907 case ixgbe_mac_82599EB: 2908 case ixgbe_mac_X550EM_x: 2909 case ixgbe_mac_x550em_a: 2910 switch (hw->mac.ops.get_media_type(hw)) { 2911 case ixgbe_media_type_fiber: 2912 case ixgbe_media_type_fiber_qsfp: 2913 return true; 2914 default: 2915 return false; 2916 } 2917 default: 2918 return false; 2919 } 2920} 2921 2922static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 2923{ 2924 struct ixgbe_hw *hw = &adapter->hw; 2925 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 2926 2927 if (!ixgbe_is_sfp(hw)) 2928 return; 2929 2930 /* Later MAC's use different SDP */ 2931 if (hw->mac.type >= ixgbe_mac_X540) 2932 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 2933 2934 if (eicr & eicr_mask) { 2935 /* Clear the interrupt */ 2936 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 2937 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2938 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 2939 adapter->sfp_poll_time = 0; 2940 ixgbe_service_event_schedule(adapter); 2941 } 2942 } 2943 2944 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 2945 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 2946 /* Clear the interrupt */ 2947 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 2948 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2949 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 2950 ixgbe_service_event_schedule(adapter); 2951 } 2952 } 2953} 2954 2955static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 2956{ 2957 struct ixgbe_hw *hw = &adapter->hw; 2958 2959 adapter->lsc_int++; 2960 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2961 adapter->link_check_timeout = jiffies; 2962 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 2963 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 2964 IXGBE_WRITE_FLUSH(hw); 2965 ixgbe_service_event_schedule(adapter); 2966 } 2967} 2968 2969static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 2970 u64 qmask) 2971{ 2972 struct ixgbe_hw *hw = &adapter->hw; 2973 u32 mask; 2974 2975 switch (hw->mac.type) { 2976 case ixgbe_mac_82598EB: 2977 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 2978 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 2979 break; 2980 case ixgbe_mac_82599EB: 2981 case ixgbe_mac_X540: 2982 case ixgbe_mac_X550: 2983 case ixgbe_mac_X550EM_x: 2984 case ixgbe_mac_x550em_a: 2985 mask = (qmask & 0xFFFFFFFF); 2986 if (mask) 2987 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 2988 mask = (qmask >> 32); 2989 if (mask) 2990 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 2991 break; 2992 default: 2993 break; 2994 } 2995 /* skip the flush */ 2996} 2997 2998/** 2999 * ixgbe_irq_enable - Enable default interrupt generation settings 3000 * @adapter: board private structure 3001 * @queues: enable irqs for queues 3002 * @flush: flush register write 3003 **/ 3004static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3005 bool flush) 3006{ 3007 struct ixgbe_hw *hw = &adapter->hw; 3008 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3009 3010 /* don't reenable LSC while waiting for link */ 3011 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3012 mask &= ~IXGBE_EIMS_LSC; 3013 3014 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3015 switch (adapter->hw.mac.type) { 3016 case ixgbe_mac_82599EB: 3017 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3018 break; 3019 case ixgbe_mac_X540: 3020 case ixgbe_mac_X550: 3021 case ixgbe_mac_X550EM_x: 3022 case ixgbe_mac_x550em_a: 3023 mask |= IXGBE_EIMS_TS; 3024 break; 3025 default: 3026 break; 3027 } 3028 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3029 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3030 switch (adapter->hw.mac.type) { 3031 case ixgbe_mac_82599EB: 3032 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3033 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3034 fallthrough; 3035 case ixgbe_mac_X540: 3036 case ixgbe_mac_X550: 3037 case ixgbe_mac_X550EM_x: 3038 case ixgbe_mac_x550em_a: 3039 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3040 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3041 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3042 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3043 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3044 mask |= IXGBE_EICR_GPI_SDP0_X540; 3045 mask |= IXGBE_EIMS_ECC; 3046 mask |= IXGBE_EIMS_MAILBOX; 3047 break; 3048 default: 3049 break; 3050 } 3051 3052 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3053 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3054 mask |= IXGBE_EIMS_FLOW_DIR; 3055 3056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3057 if (queues) 3058 ixgbe_irq_enable_queues(adapter, ~0); 3059 if (flush) 3060 IXGBE_WRITE_FLUSH(&adapter->hw); 3061} 3062 3063static irqreturn_t ixgbe_msix_other(int irq, void *data) 3064{ 3065 struct ixgbe_adapter *adapter = data; 3066 struct ixgbe_hw *hw = &adapter->hw; 3067 u32 eicr; 3068 3069 /* 3070 * Workaround for Silicon errata. Use clear-by-write instead 3071 * of clear-by-read. Reading with EICS will return the 3072 * interrupt causes without clearing, which later be done 3073 * with the write to EICR. 3074 */ 3075 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3076 3077 /* The lower 16bits of the EICR register are for the queue interrupts 3078 * which should be masked here in order to not accidentally clear them if 3079 * the bits are high when ixgbe_msix_other is called. There is a race 3080 * condition otherwise which results in possible performance loss 3081 * especially if the ixgbe_msix_other interrupt is triggering 3082 * consistently (as it would when PPS is turned on for the X540 device) 3083 */ 3084 eicr &= 0xFFFF0000; 3085 3086 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3087 3088 if (eicr & IXGBE_EICR_LSC) 3089 ixgbe_check_lsc(adapter); 3090 3091 if (eicr & IXGBE_EICR_MAILBOX) 3092 ixgbe_msg_task(adapter); 3093 3094 switch (hw->mac.type) { 3095 case ixgbe_mac_82599EB: 3096 case ixgbe_mac_X540: 3097 case ixgbe_mac_X550: 3098 case ixgbe_mac_X550EM_x: 3099 case ixgbe_mac_x550em_a: 3100 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3101 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3102 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3103 ixgbe_service_event_schedule(adapter); 3104 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3105 IXGBE_EICR_GPI_SDP0_X540); 3106 } 3107 if (eicr & IXGBE_EICR_ECC) { 3108 e_info(link, "Received ECC Err, initiating reset\n"); 3109 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3110 ixgbe_service_event_schedule(adapter); 3111 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3112 } 3113 /* Handle Flow Director Full threshold interrupt */ 3114 if (eicr & IXGBE_EICR_FLOW_DIR) { 3115 int reinit_count = 0; 3116 int i; 3117 for (i = 0; i < adapter->num_tx_queues; i++) { 3118 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3119 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3120 &ring->state)) 3121 reinit_count++; 3122 } 3123 if (reinit_count) { 3124 /* no more flow director interrupts until after init */ 3125 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3126 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3127 ixgbe_service_event_schedule(adapter); 3128 } 3129 } 3130 ixgbe_check_sfp_event(adapter, eicr); 3131 ixgbe_check_overtemp_event(adapter, eicr); 3132 break; 3133 default: 3134 break; 3135 } 3136 3137 ixgbe_check_fan_failure(adapter, eicr); 3138 3139 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3140 ixgbe_ptp_check_pps_event(adapter); 3141 3142 /* re-enable the original interrupt state, no lsc, no queues */ 3143 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3144 ixgbe_irq_enable(adapter, false, false); 3145 3146 return IRQ_HANDLED; 3147} 3148 3149static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3150{ 3151 struct ixgbe_q_vector *q_vector = data; 3152 3153 /* EIAM disabled interrupts (on this vector) for us */ 3154 3155 if (q_vector->rx.ring || q_vector->tx.ring) 3156 napi_schedule_irqoff(&q_vector->napi); 3157 3158 return IRQ_HANDLED; 3159} 3160 3161/** 3162 * ixgbe_poll - NAPI Rx polling callback 3163 * @napi: structure for representing this polling device 3164 * @budget: how many packets driver is allowed to clean 3165 * 3166 * This function is used for legacy and MSI, NAPI mode 3167 **/ 3168int ixgbe_poll(struct napi_struct *napi, int budget) 3169{ 3170 struct ixgbe_q_vector *q_vector = 3171 container_of(napi, struct ixgbe_q_vector, napi); 3172 struct ixgbe_adapter *adapter = q_vector->adapter; 3173 struct ixgbe_ring *ring; 3174 int per_ring_budget, work_done = 0; 3175 bool clean_complete = true; 3176 3177#ifdef CONFIG_IXGBE_DCA 3178 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3179 ixgbe_update_dca(q_vector); 3180#endif 3181 3182 ixgbe_for_each_ring(ring, q_vector->tx) { 3183 bool wd = ring->xsk_pool ? 3184 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3185 ixgbe_clean_tx_irq(q_vector, ring, budget); 3186 3187 if (!wd) 3188 clean_complete = false; 3189 } 3190 3191 /* Exit if we are called by netpoll */ 3192 if (budget <= 0) 3193 return budget; 3194 3195 /* attempt to distribute budget to each queue fairly, but don't allow 3196 * the budget to go below 1 because we'll exit polling */ 3197 if (q_vector->rx.count > 1) 3198 per_ring_budget = max(budget/q_vector->rx.count, 1); 3199 else 3200 per_ring_budget = budget; 3201 3202 ixgbe_for_each_ring(ring, q_vector->rx) { 3203 int cleaned = ring->xsk_pool ? 3204 ixgbe_clean_rx_irq_zc(q_vector, ring, 3205 per_ring_budget) : 3206 ixgbe_clean_rx_irq(q_vector, ring, 3207 per_ring_budget); 3208 3209 work_done += cleaned; 3210 if (cleaned >= per_ring_budget) 3211 clean_complete = false; 3212 } 3213 3214 /* If all work not completed, return budget and keep polling */ 3215 if (!clean_complete) 3216 return budget; 3217 3218 /* all work done, exit the polling mode */ 3219 if (likely(napi_complete_done(napi, work_done))) { 3220 if (adapter->rx_itr_setting & 1) 3221 ixgbe_set_itr(q_vector); 3222 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3223 ixgbe_irq_enable_queues(adapter, 3224 BIT_ULL(q_vector->v_idx)); 3225 } 3226 3227 return min(work_done, budget - 1); 3228} 3229 3230/** 3231 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3232 * @adapter: board private structure 3233 * 3234 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3235 * interrupts from the kernel. 3236 **/ 3237static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3238{ 3239 struct net_device *netdev = adapter->netdev; 3240 unsigned int ri = 0, ti = 0; 3241 int vector, err; 3242 3243 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3244 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3245 struct msix_entry *entry = &adapter->msix_entries[vector]; 3246 3247 if (q_vector->tx.ring && q_vector->rx.ring) { 3248 snprintf(q_vector->name, sizeof(q_vector->name), 3249 "%s-TxRx-%u", netdev->name, ri++); 3250 ti++; 3251 } else if (q_vector->rx.ring) { 3252 snprintf(q_vector->name, sizeof(q_vector->name), 3253 "%s-rx-%u", netdev->name, ri++); 3254 } else if (q_vector->tx.ring) { 3255 snprintf(q_vector->name, sizeof(q_vector->name), 3256 "%s-tx-%u", netdev->name, ti++); 3257 } else { 3258 /* skip this unused q_vector */ 3259 continue; 3260 } 3261 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3262 q_vector->name, q_vector); 3263 if (err) { 3264 e_err(probe, "request_irq failed for MSIX interrupt " 3265 "Error: %d\n", err); 3266 goto free_queue_irqs; 3267 } 3268 /* If Flow Director is enabled, set interrupt affinity */ 3269 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3270 /* assign the mask for this irq */ 3271 irq_update_affinity_hint(entry->vector, 3272 &q_vector->affinity_mask); 3273 } 3274 } 3275 3276 err = request_irq(adapter->msix_entries[vector].vector, 3277 ixgbe_msix_other, 0, netdev->name, adapter); 3278 if (err) { 3279 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3280 goto free_queue_irqs; 3281 } 3282 3283 return 0; 3284 3285free_queue_irqs: 3286 while (vector) { 3287 vector--; 3288 irq_update_affinity_hint(adapter->msix_entries[vector].vector, 3289 NULL); 3290 free_irq(adapter->msix_entries[vector].vector, 3291 adapter->q_vector[vector]); 3292 } 3293 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3294 pci_disable_msix(adapter->pdev); 3295 kfree(adapter->msix_entries); 3296 adapter->msix_entries = NULL; 3297 return err; 3298} 3299 3300/** 3301 * ixgbe_intr - legacy mode Interrupt Handler 3302 * @irq: interrupt number 3303 * @data: pointer to a network interface device structure 3304 **/ 3305static irqreturn_t ixgbe_intr(int irq, void *data) 3306{ 3307 struct ixgbe_adapter *adapter = data; 3308 struct ixgbe_hw *hw = &adapter->hw; 3309 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3310 u32 eicr; 3311 3312 /* 3313 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3314 * before the read of EICR. 3315 */ 3316 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3317 3318 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3319 * therefore no explicit interrupt disable is necessary */ 3320 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3321 if (!eicr) { 3322 /* 3323 * shared interrupt alert! 3324 * make sure interrupts are enabled because the read will 3325 * have disabled interrupts due to EIAM 3326 * finish the workaround of silicon errata on 82598. Unmask 3327 * the interrupt that we masked before the EICR read. 3328 */ 3329 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3330 ixgbe_irq_enable(adapter, true, true); 3331 return IRQ_NONE; /* Not our interrupt */ 3332 } 3333 3334 if (eicr & IXGBE_EICR_LSC) 3335 ixgbe_check_lsc(adapter); 3336 3337 switch (hw->mac.type) { 3338 case ixgbe_mac_82599EB: 3339 ixgbe_check_sfp_event(adapter, eicr); 3340 fallthrough; 3341 case ixgbe_mac_X540: 3342 case ixgbe_mac_X550: 3343 case ixgbe_mac_X550EM_x: 3344 case ixgbe_mac_x550em_a: 3345 if (eicr & IXGBE_EICR_ECC) { 3346 e_info(link, "Received ECC Err, initiating reset\n"); 3347 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3348 ixgbe_service_event_schedule(adapter); 3349 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3350 } 3351 ixgbe_check_overtemp_event(adapter, eicr); 3352 break; 3353 default: 3354 break; 3355 } 3356 3357 ixgbe_check_fan_failure(adapter, eicr); 3358 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3359 ixgbe_ptp_check_pps_event(adapter); 3360 3361 /* would disable interrupts here but EIAM disabled it */ 3362 napi_schedule_irqoff(&q_vector->napi); 3363 3364 /* 3365 * re-enable link(maybe) and non-queue interrupts, no flush. 3366 * ixgbe_poll will re-enable the queue interrupts 3367 */ 3368 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3369 ixgbe_irq_enable(adapter, false, false); 3370 3371 return IRQ_HANDLED; 3372} 3373 3374/** 3375 * ixgbe_request_irq - initialize interrupts 3376 * @adapter: board private structure 3377 * 3378 * Attempts to configure interrupts using the best available 3379 * capabilities of the hardware and kernel. 3380 **/ 3381static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3382{ 3383 struct net_device *netdev = adapter->netdev; 3384 int err; 3385 3386 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3387 err = ixgbe_request_msix_irqs(adapter); 3388 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3389 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3390 netdev->name, adapter); 3391 else 3392 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3393 netdev->name, adapter); 3394 3395 if (err) 3396 e_err(probe, "request_irq failed, Error %d\n", err); 3397 3398 return err; 3399} 3400 3401static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3402{ 3403 int vector; 3404 3405 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3406 free_irq(adapter->pdev->irq, adapter); 3407 return; 3408 } 3409 3410 if (!adapter->msix_entries) 3411 return; 3412 3413 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3414 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3415 struct msix_entry *entry = &adapter->msix_entries[vector]; 3416 3417 /* free only the irqs that were actually requested */ 3418 if (!q_vector->rx.ring && !q_vector->tx.ring) 3419 continue; 3420 3421 /* clear the affinity_mask in the IRQ descriptor */ 3422 irq_update_affinity_hint(entry->vector, NULL); 3423 3424 free_irq(entry->vector, q_vector); 3425 } 3426 3427 free_irq(adapter->msix_entries[vector].vector, adapter); 3428} 3429 3430/** 3431 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3432 * @adapter: board private structure 3433 **/ 3434static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3435{ 3436 switch (adapter->hw.mac.type) { 3437 case ixgbe_mac_82598EB: 3438 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3439 break; 3440 case ixgbe_mac_82599EB: 3441 case ixgbe_mac_X540: 3442 case ixgbe_mac_X550: 3443 case ixgbe_mac_X550EM_x: 3444 case ixgbe_mac_x550em_a: 3445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3447 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3448 break; 3449 default: 3450 break; 3451 } 3452 IXGBE_WRITE_FLUSH(&adapter->hw); 3453 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3454 int vector; 3455 3456 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3457 synchronize_irq(adapter->msix_entries[vector].vector); 3458 3459 synchronize_irq(adapter->msix_entries[vector++].vector); 3460 } else { 3461 synchronize_irq(adapter->pdev->irq); 3462 } 3463} 3464 3465/** 3466 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3467 * @adapter: board private structure 3468 * 3469 **/ 3470static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3471{ 3472 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3473 3474 ixgbe_write_eitr(q_vector); 3475 3476 ixgbe_set_ivar(adapter, 0, 0, 0); 3477 ixgbe_set_ivar(adapter, 1, 0, 0); 3478 3479 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3480} 3481 3482/** 3483 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3484 * @adapter: board private structure 3485 * @ring: structure containing ring specific data 3486 * 3487 * Configure the Tx descriptor ring after a reset. 3488 **/ 3489void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3490 struct ixgbe_ring *ring) 3491{ 3492 struct ixgbe_hw *hw = &adapter->hw; 3493 u64 tdba = ring->dma; 3494 int wait_loop = 10; 3495 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3496 u8 reg_idx = ring->reg_idx; 3497 3498 ring->xsk_pool = NULL; 3499 if (ring_is_xdp(ring)) 3500 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3501 3502 /* disable queue to avoid issues while updating state */ 3503 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3504 IXGBE_WRITE_FLUSH(hw); 3505 3506 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3507 (tdba & DMA_BIT_MASK(32))); 3508 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3509 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3510 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3511 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3512 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3513 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3514 3515 /* 3516 * set WTHRESH to encourage burst writeback, it should not be set 3517 * higher than 1 when: 3518 * - ITR is 0 as it could cause false TX hangs 3519 * - ITR is set to > 100k int/sec and BQL is enabled 3520 * 3521 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3522 * to or less than the number of on chip descriptors, which is 3523 * currently 40. 3524 */ 3525 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3526 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3527 else 3528 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3529 3530 /* 3531 * Setting PTHRESH to 32 both improves performance 3532 * and avoids a TX hang with DFP enabled 3533 */ 3534 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3535 32; /* PTHRESH = 32 */ 3536 3537 /* reinitialize flowdirector state */ 3538 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3539 ring->atr_sample_rate = adapter->atr_sample_rate; 3540 ring->atr_count = 0; 3541 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); 3542 } else { 3543 ring->atr_sample_rate = 0; 3544 } 3545 3546 /* initialize XPS */ 3547 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { 3548 struct ixgbe_q_vector *q_vector = ring->q_vector; 3549 3550 if (q_vector) 3551 netif_set_xps_queue(ring->netdev, 3552 &q_vector->affinity_mask, 3553 ring->queue_index); 3554 } 3555 3556 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); 3557 3558 /* reinitialize tx_buffer_info */ 3559 memset(ring->tx_buffer_info, 0, 3560 sizeof(struct ixgbe_tx_buffer) * ring->count); 3561 3562 /* enable queue */ 3563 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3564 3565 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3566 if (hw->mac.type == ixgbe_mac_82598EB && 3567 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3568 return; 3569 3570 /* poll to verify queue is enabled */ 3571 do { 3572 usleep_range(1000, 2000); 3573 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3574 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3575 if (!wait_loop) 3576 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3577} 3578 3579static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3580{ 3581 struct ixgbe_hw *hw = &adapter->hw; 3582 u32 rttdcs, mtqc; 3583 u8 tcs = adapter->hw_tcs; 3584 3585 if (hw->mac.type == ixgbe_mac_82598EB) 3586 return; 3587 3588 /* disable the arbiter while setting MTQC */ 3589 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 3590 rttdcs |= IXGBE_RTTDCS_ARBDIS; 3591 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3592 3593 /* set transmit pool layout */ 3594 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3595 mtqc = IXGBE_MTQC_VT_ENA; 3596 if (tcs > 4) 3597 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3598 else if (tcs > 1) 3599 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3600 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3601 IXGBE_82599_VMDQ_4Q_MASK) 3602 mtqc |= IXGBE_MTQC_32VF; 3603 else 3604 mtqc |= IXGBE_MTQC_64VF; 3605 } else { 3606 if (tcs > 4) { 3607 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 3608 } else if (tcs > 1) { 3609 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3610 } else { 3611 u8 max_txq = adapter->num_tx_queues + 3612 adapter->num_xdp_queues; 3613 if (max_txq > 63) 3614 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 3615 else 3616 mtqc = IXGBE_MTQC_64Q_1PB; 3617 } 3618 } 3619 3620 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 3621 3622 /* Enable Security TX Buffer IFG for multiple pb */ 3623 if (tcs) { 3624 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 3625 sectx |= IXGBE_SECTX_DCB; 3626 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 3627 } 3628 3629 /* re-enable the arbiter */ 3630 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 3631 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 3632} 3633 3634/** 3635 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 3636 * @adapter: board private structure 3637 * 3638 * Configure the Tx unit of the MAC after a reset. 3639 **/ 3640static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 3641{ 3642 struct ixgbe_hw *hw = &adapter->hw; 3643 u32 dmatxctl; 3644 u32 i; 3645 3646 ixgbe_setup_mtqc(adapter); 3647 3648 if (hw->mac.type != ixgbe_mac_82598EB) { 3649 /* DMATXCTL.EN must be before Tx queues are enabled */ 3650 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 3651 dmatxctl |= IXGBE_DMATXCTL_TE; 3652 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 3653 } 3654 3655 /* Setup the HW Tx Head and Tail descriptor pointers */ 3656 for (i = 0; i < adapter->num_tx_queues; i++) 3657 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 3658 for (i = 0; i < adapter->num_xdp_queues; i++) 3659 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 3660} 3661 3662static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 3663 struct ixgbe_ring *ring) 3664{ 3665 struct ixgbe_hw *hw = &adapter->hw; 3666 u8 reg_idx = ring->reg_idx; 3667 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3668 3669 srrctl |= IXGBE_SRRCTL_DROP_EN; 3670 3671 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3672} 3673 3674static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 3675 struct ixgbe_ring *ring) 3676{ 3677 struct ixgbe_hw *hw = &adapter->hw; 3678 u8 reg_idx = ring->reg_idx; 3679 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 3680 3681 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 3682 3683 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3684} 3685 3686#ifdef CONFIG_IXGBE_DCB 3687void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3688#else 3689static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 3690#endif 3691{ 3692 int i; 3693 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 3694 3695 if (adapter->ixgbe_ieee_pfc) 3696 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 3697 3698 /* 3699 * We should set the drop enable bit if: 3700 * SR-IOV is enabled 3701 * or 3702 * Number of Rx queues > 1 and flow control is disabled 3703 * 3704 * This allows us to avoid head of line blocking for security 3705 * and performance reasons. 3706 */ 3707 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 3708 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 3709 for (i = 0; i < adapter->num_rx_queues; i++) 3710 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 3711 } else { 3712 for (i = 0; i < adapter->num_rx_queues; i++) 3713 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 3714 } 3715} 3716 3717#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 3718 3719static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 3720 struct ixgbe_ring *rx_ring) 3721{ 3722 struct ixgbe_hw *hw = &adapter->hw; 3723 u32 srrctl; 3724 u8 reg_idx = rx_ring->reg_idx; 3725 3726 if (hw->mac.type == ixgbe_mac_82598EB) { 3727 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 3728 3729 /* 3730 * if VMDq is not active we must program one srrctl register 3731 * per RSS queue since we have enabled RDRXCTL.MVMEN 3732 */ 3733 reg_idx &= mask; 3734 } 3735 3736 /* configure header buffer length, needed for RSC */ 3737 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 3738 3739 /* configure the packet buffer length */ 3740 if (rx_ring->xsk_pool) { 3741 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 3742 3743 /* If the MAC support setting RXDCTL.RLPML, the 3744 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 3745 * RXDCTL.RLPML is set to the actual UMEM buffer 3746 * size. If not, then we are stuck with a 1k buffer 3747 * size resolution. In this case frames larger than 3748 * the UMEM buffer size viewed in a 1k resolution will 3749 * be dropped. 3750 */ 3751 if (hw->mac.type != ixgbe_mac_82599EB) 3752 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3753 else 3754 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3755 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) { 3756 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3757 } else { 3758 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 3759 } 3760 3761 /* configure descriptor type */ 3762 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 3763 3764 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 3765} 3766 3767/** 3768 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 3769 * @adapter: device handle 3770 * 3771 * - 82598/82599/X540: 128 3772 * - X550(non-SRIOV mode): 512 3773 * - X550(SRIOV mode): 64 3774 */ 3775u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 3776{ 3777 if (adapter->hw.mac.type < ixgbe_mac_X550) 3778 return 128; 3779 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 3780 return 64; 3781 else 3782 return 512; 3783} 3784 3785/** 3786 * ixgbe_store_key - Write the RSS key to HW 3787 * @adapter: device handle 3788 * 3789 * Write the RSS key stored in adapter.rss_key to HW. 3790 */ 3791void ixgbe_store_key(struct ixgbe_adapter *adapter) 3792{ 3793 struct ixgbe_hw *hw = &adapter->hw; 3794 int i; 3795 3796 for (i = 0; i < 10; i++) 3797 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 3798} 3799 3800/** 3801 * ixgbe_init_rss_key - Initialize adapter RSS key 3802 * @adapter: device handle 3803 * 3804 * Allocates and initializes the RSS key if it is not allocated. 3805 **/ 3806static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 3807{ 3808 u32 *rss_key; 3809 3810 if (!adapter->rss_key) { 3811 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 3812 if (unlikely(!rss_key)) 3813 return -ENOMEM; 3814 3815 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 3816 adapter->rss_key = rss_key; 3817 } 3818 3819 return 0; 3820} 3821 3822/** 3823 * ixgbe_store_reta - Write the RETA table to HW 3824 * @adapter: device handle 3825 * 3826 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3827 */ 3828void ixgbe_store_reta(struct ixgbe_adapter *adapter) 3829{ 3830 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3831 struct ixgbe_hw *hw = &adapter->hw; 3832 u32 reta = 0; 3833 u32 indices_multi; 3834 u8 *indir_tbl = adapter->rss_indir_tbl; 3835 3836 /* Fill out the redirection table as follows: 3837 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 3838 * indices. 3839 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 3840 * - X550: 8 bit wide entries containing 6 bit RSS index 3841 */ 3842 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 3843 indices_multi = 0x11; 3844 else 3845 indices_multi = 0x1; 3846 3847 /* Write redirection table to HW */ 3848 for (i = 0; i < reta_entries; i++) { 3849 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 3850 if ((i & 3) == 3) { 3851 if (i < 128) 3852 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 3853 else 3854 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 3855 reta); 3856 reta = 0; 3857 } 3858 } 3859} 3860 3861/** 3862 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 3863 * @adapter: device handle 3864 * 3865 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 3866 */ 3867static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 3868{ 3869 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3870 struct ixgbe_hw *hw = &adapter->hw; 3871 u32 vfreta = 0; 3872 3873 /* Write redirection table to HW */ 3874 for (i = 0; i < reta_entries; i++) { 3875 u16 pool = adapter->num_rx_pools; 3876 3877 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 3878 if ((i & 3) != 3) 3879 continue; 3880 3881 while (pool--) 3882 IXGBE_WRITE_REG(hw, 3883 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 3884 vfreta); 3885 vfreta = 0; 3886 } 3887} 3888 3889static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 3890{ 3891 u32 i, j; 3892 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 3893 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3894 3895 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 3896 * make full use of any rings they may have. We will use the 3897 * PSRTYPE register to control how many rings we use within the PF. 3898 */ 3899 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 3900 rss_i = 4; 3901 3902 /* Fill out hash function seeds */ 3903 ixgbe_store_key(adapter); 3904 3905 /* Fill out redirection table */ 3906 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 3907 3908 for (i = 0, j = 0; i < reta_entries; i++, j++) { 3909 if (j == rss_i) 3910 j = 0; 3911 3912 adapter->rss_indir_tbl[i] = j; 3913 } 3914 3915 ixgbe_store_reta(adapter); 3916} 3917 3918static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 3919{ 3920 struct ixgbe_hw *hw = &adapter->hw; 3921 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 3922 int i, j; 3923 3924 /* Fill out hash function seeds */ 3925 for (i = 0; i < 10; i++) { 3926 u16 pool = adapter->num_rx_pools; 3927 3928 while (pool--) 3929 IXGBE_WRITE_REG(hw, 3930 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 3931 *(adapter->rss_key + i)); 3932 } 3933 3934 /* Fill out the redirection table */ 3935 for (i = 0, j = 0; i < 64; i++, j++) { 3936 if (j == rss_i) 3937 j = 0; 3938 3939 adapter->rss_indir_tbl[i] = j; 3940 } 3941 3942 ixgbe_store_vfreta(adapter); 3943} 3944 3945static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 3946{ 3947 struct ixgbe_hw *hw = &adapter->hw; 3948 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 3949 u32 rxcsum; 3950 3951 /* Disable indicating checksum in descriptor, enables RSS hash */ 3952 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 3953 rxcsum |= IXGBE_RXCSUM_PCSD; 3954 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 3955 3956 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 3957 if (adapter->ring_feature[RING_F_RSS].mask) 3958 mrqc = IXGBE_MRQC_RSSEN; 3959 } else { 3960 u8 tcs = adapter->hw_tcs; 3961 3962 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 3963 if (tcs > 4) 3964 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 3965 else if (tcs > 1) 3966 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 3967 else if (adapter->ring_feature[RING_F_VMDQ].mask == 3968 IXGBE_82599_VMDQ_4Q_MASK) 3969 mrqc = IXGBE_MRQC_VMDQRSS32EN; 3970 else 3971 mrqc = IXGBE_MRQC_VMDQRSS64EN; 3972 3973 /* Enable L3/L4 for Tx Switched packets only for X550, 3974 * older devices do not support this feature 3975 */ 3976 if (hw->mac.type >= ixgbe_mac_X550) 3977 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 3978 } else { 3979 if (tcs > 4) 3980 mrqc = IXGBE_MRQC_RTRSS8TCEN; 3981 else if (tcs > 1) 3982 mrqc = IXGBE_MRQC_RTRSS4TCEN; 3983 else 3984 mrqc = IXGBE_MRQC_RSSEN; 3985 } 3986 } 3987 3988 /* Perform hash on these packet types */ 3989 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 3990 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 3991 IXGBE_MRQC_RSS_FIELD_IPV6 | 3992 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 3993 3994 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 3995 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 3996 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 3997 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 3998 3999 if ((hw->mac.type >= ixgbe_mac_X550) && 4000 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 4001 u16 pool = adapter->num_rx_pools; 4002 4003 /* Enable VF RSS mode */ 4004 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 4005 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4006 4007 /* Setup RSS through the VF registers */ 4008 ixgbe_setup_vfreta(adapter); 4009 vfmrqc = IXGBE_MRQC_RSSEN; 4010 vfmrqc |= rss_field; 4011 4012 while (pool--) 4013 IXGBE_WRITE_REG(hw, 4014 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4015 vfmrqc); 4016 } else { 4017 ixgbe_setup_reta(adapter); 4018 mrqc |= rss_field; 4019 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4020 } 4021} 4022 4023/** 4024 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4025 * @adapter: address of board private structure 4026 * @ring: structure containing ring specific data 4027 **/ 4028static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4029 struct ixgbe_ring *ring) 4030{ 4031 struct ixgbe_hw *hw = &adapter->hw; 4032 u32 rscctrl; 4033 u8 reg_idx = ring->reg_idx; 4034 4035 if (!ring_is_rsc_enabled(ring)) 4036 return; 4037 4038 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4039 rscctrl |= IXGBE_RSCCTL_RSCEN; 4040 /* 4041 * we must limit the number of descriptors so that the 4042 * total size of max desc * buf_len is not greater 4043 * than 65536 4044 */ 4045 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4046 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4047} 4048 4049#define IXGBE_MAX_RX_DESC_POLL 10 4050static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4051 struct ixgbe_ring *ring) 4052{ 4053 struct ixgbe_hw *hw = &adapter->hw; 4054 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4055 u32 rxdctl; 4056 u8 reg_idx = ring->reg_idx; 4057 4058 if (ixgbe_removed(hw->hw_addr)) 4059 return; 4060 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4061 if (hw->mac.type == ixgbe_mac_82598EB && 4062 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4063 return; 4064 4065 do { 4066 usleep_range(1000, 2000); 4067 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4068 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4069 4070 if (!wait_loop) { 4071 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4072 "the polling period\n", reg_idx); 4073 } 4074} 4075 4076void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4077 struct ixgbe_ring *ring) 4078{ 4079 struct ixgbe_hw *hw = &adapter->hw; 4080 union ixgbe_adv_rx_desc *rx_desc; 4081 u64 rdba = ring->dma; 4082 u32 rxdctl; 4083 u8 reg_idx = ring->reg_idx; 4084 4085 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4086 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4087 if (ring->xsk_pool) { 4088 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4089 MEM_TYPE_XSK_BUFF_POOL, 4090 NULL)); 4091 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4092 } else { 4093 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4094 MEM_TYPE_PAGE_SHARED, NULL)); 4095 } 4096 4097 /* disable queue to avoid use of these values while updating state */ 4098 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4099 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4100 4101 /* write value back with RXDCTL.ENABLE bit cleared */ 4102 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4103 IXGBE_WRITE_FLUSH(hw); 4104 4105 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4106 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4107 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4108 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4109 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4110 IXGBE_WRITE_FLUSH(hw); 4111 4112 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4113 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4114 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4115 4116 ixgbe_configure_srrctl(adapter, ring); 4117 ixgbe_configure_rscctl(adapter, ring); 4118 4119 if (hw->mac.type == ixgbe_mac_82598EB) { 4120 /* 4121 * enable cache line friendly hardware writes: 4122 * PTHRESH=32 descriptors (half the internal cache), 4123 * this also removes ugly rx_no_buffer_count increment 4124 * HTHRESH=4 descriptors (to minimize latency on fetch) 4125 * WTHRESH=8 burst writeback up to two cache lines 4126 */ 4127 rxdctl &= ~0x3FFFFF; 4128 rxdctl |= 0x080420; 4129#if (PAGE_SIZE < 8192) 4130 /* RXDCTL.RLPML does not work on 82599 */ 4131 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4132 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4133 IXGBE_RXDCTL_RLPML_EN); 4134 4135 /* Limit the maximum frame size so we don't overrun the skb. 4136 * This can happen in SRIOV mode when the MTU of the VF is 4137 * higher than the MTU of the PF. 4138 */ 4139 if (ring_uses_build_skb(ring) && 4140 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state)) 4141 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4142 IXGBE_RXDCTL_RLPML_EN; 4143#endif 4144 } 4145 4146 ring->rx_offset = ixgbe_rx_offset(ring); 4147 4148 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4149 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4150 4151 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4152 IXGBE_RXDCTL_RLPML_EN); 4153 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4154 4155 ring->rx_buf_len = xsk_buf_len; 4156 } 4157 4158 /* initialize rx_buffer_info */ 4159 memset(ring->rx_buffer_info, 0, 4160 sizeof(struct ixgbe_rx_buffer) * ring->count); 4161 4162 /* initialize Rx descriptor 0 */ 4163 rx_desc = IXGBE_RX_DESC(ring, 0); 4164 rx_desc->wb.upper.length = 0; 4165 4166 /* enable receive descriptor ring */ 4167 rxdctl |= IXGBE_RXDCTL_ENABLE; 4168 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4169 4170 ixgbe_rx_desc_queue_enable(adapter, ring); 4171 if (ring->xsk_pool) 4172 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4173 else 4174 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4175} 4176 4177static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4178{ 4179 struct ixgbe_hw *hw = &adapter->hw; 4180 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4181 u16 pool = adapter->num_rx_pools; 4182 4183 /* PSRTYPE must be initialized in non 82598 adapters */ 4184 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4185 IXGBE_PSRTYPE_UDPHDR | 4186 IXGBE_PSRTYPE_IPV4HDR | 4187 IXGBE_PSRTYPE_L2HDR | 4188 IXGBE_PSRTYPE_IPV6HDR; 4189 4190 if (hw->mac.type == ixgbe_mac_82598EB) 4191 return; 4192 4193 if (rss_i > 3) 4194 psrtype |= 2u << 29; 4195 else if (rss_i > 1) 4196 psrtype |= 1u << 29; 4197 4198 while (pool--) 4199 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4200} 4201 4202static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4203{ 4204 struct ixgbe_hw *hw = &adapter->hw; 4205 u16 pool = adapter->num_rx_pools; 4206 u32 reg_offset, vf_shift, vmolr; 4207 u32 gcr_ext, vmdctl; 4208 int i; 4209 4210 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4211 return; 4212 4213 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4214 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4215 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4216 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4217 vmdctl |= IXGBE_VT_CTL_REPLEN; 4218 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4219 4220 /* accept untagged packets until a vlan tag is 4221 * specifically set for the VMDQ queue/pool 4222 */ 4223 vmolr = IXGBE_VMOLR_AUPE; 4224 while (pool--) 4225 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4226 4227 vf_shift = VMDQ_P(0) % 32; 4228 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4229 4230 /* Enable only the PF's pool for Tx/Rx */ 4231 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4232 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4234 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4235 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4236 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4237 4238 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4239 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4240 4241 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4242 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4243 4244 /* 4245 * Set up VF register offsets for selected VT Mode, 4246 * i.e. 32 or 64 VFs for SR-IOV 4247 */ 4248 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4249 case IXGBE_82599_VMDQ_8Q_MASK: 4250 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4251 break; 4252 case IXGBE_82599_VMDQ_4Q_MASK: 4253 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4254 break; 4255 default: 4256 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4257 break; 4258 } 4259 4260 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4261 4262 for (i = 0; i < adapter->num_vfs; i++) { 4263 /* configure spoof checking */ 4264 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4265 adapter->vfinfo[i].spoofchk_enabled); 4266 4267 /* Enable/Disable RSS query feature */ 4268 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4269 adapter->vfinfo[i].rss_query_enabled); 4270 } 4271} 4272 4273static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4274{ 4275 struct ixgbe_hw *hw = &adapter->hw; 4276 struct net_device *netdev = adapter->netdev; 4277 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4278 struct ixgbe_ring *rx_ring; 4279 int i; 4280 u32 mhadd, hlreg0; 4281 4282#ifdef IXGBE_FCOE 4283 /* adjust max frame to be able to do baby jumbo for FCoE */ 4284 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4285 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4286 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4287 4288#endif /* IXGBE_FCOE */ 4289 4290 /* adjust max frame to be at least the size of a standard frame */ 4291 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4292 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4293 4294 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4295 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4296 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4297 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4298 4299 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4300 } 4301 4302 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4303 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4304 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4305 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4306 4307 /* 4308 * Setup the HW Rx Head and Tail Descriptor Pointers and 4309 * the Base and Length of the Rx Descriptor Ring 4310 */ 4311 for (i = 0; i < adapter->num_rx_queues; i++) { 4312 rx_ring = adapter->rx_ring[i]; 4313 4314 clear_ring_rsc_enabled(rx_ring); 4315 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4316 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4317 4318 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4319 set_ring_rsc_enabled(rx_ring); 4320 4321 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state)) 4322 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4323 4324 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4325 continue; 4326 4327 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state); 4328 4329#if (PAGE_SIZE < 8192) 4330 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4331 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4332 4333 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4334 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4335 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state); 4336#endif 4337 } 4338} 4339 4340static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4341{ 4342 struct ixgbe_hw *hw = &adapter->hw; 4343 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4344 4345 switch (hw->mac.type) { 4346 case ixgbe_mac_82598EB: 4347 /* 4348 * For VMDq support of different descriptor types or 4349 * buffer sizes through the use of multiple SRRCTL 4350 * registers, RDRXCTL.MVMEN must be set to 1 4351 * 4352 * also, the manual doesn't mention it clearly but DCA hints 4353 * will only use queue 0's tags unless this bit is set. Side 4354 * effects of setting this bit are only that SRRCTL must be 4355 * fully programmed [0..15] 4356 */ 4357 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4358 break; 4359 case ixgbe_mac_X550: 4360 case ixgbe_mac_X550EM_x: 4361 case ixgbe_mac_x550em_a: 4362 if (adapter->num_vfs) 4363 rdrxctl |= IXGBE_RDRXCTL_PSP; 4364 fallthrough; 4365 case ixgbe_mac_82599EB: 4366 case ixgbe_mac_X540: 4367 /* Disable RSC for ACK packets */ 4368 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4369 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4370 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4371 /* hardware requires some bits to be set by default */ 4372 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4373 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4374 break; 4375 default: 4376 /* We should do nothing since we don't know this hardware */ 4377 return; 4378 } 4379 4380 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4381} 4382 4383/** 4384 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4385 * @adapter: board private structure 4386 * 4387 * Configure the Rx unit of the MAC after a reset. 4388 **/ 4389static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4390{ 4391 struct ixgbe_hw *hw = &adapter->hw; 4392 int i; 4393 u32 rxctrl, rfctl; 4394 4395 /* disable receives while setting up the descriptors */ 4396 hw->mac.ops.disable_rx(hw); 4397 4398 ixgbe_setup_psrtype(adapter); 4399 ixgbe_setup_rdrxctl(adapter); 4400 4401 /* RSC Setup */ 4402 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4403 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4404 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4405 rfctl |= IXGBE_RFCTL_RSC_DIS; 4406 4407 /* disable NFS filtering */ 4408 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4409 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4410 4411 /* Program registers for the distribution of queues */ 4412 ixgbe_setup_mrqc(adapter); 4413 4414 /* set_rx_buffer_len must be called before ring initialization */ 4415 ixgbe_set_rx_buffer_len(adapter); 4416 4417 /* 4418 * Setup the HW Rx Head and Tail Descriptor Pointers and 4419 * the Base and Length of the Rx Descriptor Ring 4420 */ 4421 for (i = 0; i < adapter->num_rx_queues; i++) 4422 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4423 4424 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4425 /* disable drop enable for 82598 parts */ 4426 if (hw->mac.type == ixgbe_mac_82598EB) 4427 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4428 4429 /* enable all receives */ 4430 rxctrl |= IXGBE_RXCTRL_RXEN; 4431 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4432} 4433 4434static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4435 __be16 proto, u16 vid) 4436{ 4437 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4438 struct ixgbe_hw *hw = &adapter->hw; 4439 4440 /* add VID to filter table */ 4441 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4442 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4443 4444 set_bit(vid, adapter->active_vlans); 4445 4446 return 0; 4447} 4448 4449static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4450{ 4451 u32 vlvf; 4452 int idx; 4453 4454 /* short cut the special case */ 4455 if (vlan == 0) 4456 return 0; 4457 4458 /* Search for the vlan id in the VLVF entries */ 4459 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4460 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4461 if ((vlvf & VLAN_VID_MASK) == vlan) 4462 break; 4463 } 4464 4465 return idx; 4466} 4467 4468void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4469{ 4470 struct ixgbe_hw *hw = &adapter->hw; 4471 u32 bits, word; 4472 int idx; 4473 4474 idx = ixgbe_find_vlvf_entry(hw, vid); 4475 if (!idx) 4476 return; 4477 4478 /* See if any other pools are set for this VLAN filter 4479 * entry other than the PF. 4480 */ 4481 word = idx * 2 + (VMDQ_P(0) / 32); 4482 bits = ~BIT(VMDQ_P(0) % 32); 4483 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4484 4485 /* Disable the filter so this falls into the default pool. */ 4486 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4487 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4488 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4489 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4490 } 4491} 4492 4493static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4494 __be16 proto, u16 vid) 4495{ 4496 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4497 struct ixgbe_hw *hw = &adapter->hw; 4498 4499 /* remove VID from filter table */ 4500 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4501 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4502 4503 clear_bit(vid, adapter->active_vlans); 4504 4505 return 0; 4506} 4507 4508/** 4509 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4510 * @adapter: driver data 4511 */ 4512static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4513{ 4514 struct ixgbe_hw *hw = &adapter->hw; 4515 u32 vlnctrl; 4516 int i, j; 4517 4518 switch (hw->mac.type) { 4519 case ixgbe_mac_82598EB: 4520 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4521 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4522 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4523 break; 4524 case ixgbe_mac_82599EB: 4525 case ixgbe_mac_X540: 4526 case ixgbe_mac_X550: 4527 case ixgbe_mac_X550EM_x: 4528 case ixgbe_mac_x550em_a: 4529 for (i = 0; i < adapter->num_rx_queues; i++) { 4530 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4531 4532 if (!netif_is_ixgbe(ring->netdev)) 4533 continue; 4534 4535 j = ring->reg_idx; 4536 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4537 vlnctrl &= ~IXGBE_RXDCTL_VME; 4538 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4539 } 4540 break; 4541 default: 4542 break; 4543 } 4544} 4545 4546/** 4547 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4548 * @adapter: driver data 4549 */ 4550static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4551{ 4552 struct ixgbe_hw *hw = &adapter->hw; 4553 u32 vlnctrl; 4554 int i, j; 4555 4556 switch (hw->mac.type) { 4557 case ixgbe_mac_82598EB: 4558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4559 vlnctrl |= IXGBE_VLNCTRL_VME; 4560 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4561 break; 4562 case ixgbe_mac_82599EB: 4563 case ixgbe_mac_X540: 4564 case ixgbe_mac_X550: 4565 case ixgbe_mac_X550EM_x: 4566 case ixgbe_mac_x550em_a: 4567 for (i = 0; i < adapter->num_rx_queues; i++) { 4568 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4569 4570 if (!netif_is_ixgbe(ring->netdev)) 4571 continue; 4572 4573 j = ring->reg_idx; 4574 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4575 vlnctrl |= IXGBE_RXDCTL_VME; 4576 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4577 } 4578 break; 4579 default: 4580 break; 4581 } 4582} 4583 4584static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 4585{ 4586 struct ixgbe_hw *hw = &adapter->hw; 4587 u32 vlnctrl, i; 4588 4589 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4590 4591 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 4592 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 4593 vlnctrl |= IXGBE_VLNCTRL_VFE; 4594 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4595 } else { 4596 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 4597 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4598 return; 4599 } 4600 4601 /* Nothing to do for 82598 */ 4602 if (hw->mac.type == ixgbe_mac_82598EB) 4603 return; 4604 4605 /* We are already in VLAN promisc, nothing to do */ 4606 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 4607 return; 4608 4609 /* Set flag so we don't redo unnecessary work */ 4610 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 4611 4612 /* Add PF to all active pools */ 4613 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4614 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 4615 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 4616 4617 vlvfb |= BIT(VMDQ_P(0) % 32); 4618 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 4619 } 4620 4621 /* Set all bits in the VLAN filter table array */ 4622 for (i = hw->mac.vft_size; i--;) 4623 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 4624} 4625 4626#define VFTA_BLOCK_SIZE 8 4627static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 4628{ 4629 struct ixgbe_hw *hw = &adapter->hw; 4630 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 4631 u32 vid_start = vfta_offset * 32; 4632 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 4633 u32 i, vid, word, bits; 4634 4635 for (i = IXGBE_VLVF_ENTRIES; --i;) { 4636 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 4637 4638 /* pull VLAN ID from VLVF */ 4639 vid = vlvf & VLAN_VID_MASK; 4640 4641 /* only concern outselves with a certain range */ 4642 if (vid < vid_start || vid >= vid_end) 4643 continue; 4644 4645 if (vlvf) { 4646 /* record VLAN ID in VFTA */ 4647 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 4648 4649 /* if PF is part of this then continue */ 4650 if (test_bit(vid, adapter->active_vlans)) 4651 continue; 4652 } 4653 4654 /* remove PF from the pool */ 4655 word = i * 2 + VMDQ_P(0) / 32; 4656 bits = ~BIT(VMDQ_P(0) % 32); 4657 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4658 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 4659 } 4660 4661 /* extract values from active_vlans and write back to VFTA */ 4662 for (i = VFTA_BLOCK_SIZE; i--;) { 4663 vid = (vfta_offset + i) * 32; 4664 word = vid / BITS_PER_LONG; 4665 bits = vid % BITS_PER_LONG; 4666 4667 vfta[i] |= adapter->active_vlans[word] >> bits; 4668 4669 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 4670 } 4671} 4672 4673static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 4674{ 4675 struct ixgbe_hw *hw = &adapter->hw; 4676 u32 vlnctrl, i; 4677 4678 /* Set VLAN filtering to enabled */ 4679 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4680 vlnctrl |= IXGBE_VLNCTRL_VFE; 4681 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4682 4683 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 4684 hw->mac.type == ixgbe_mac_82598EB) 4685 return; 4686 4687 /* We are not in VLAN promisc, nothing to do */ 4688 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4689 return; 4690 4691 /* Set flag so we don't redo unnecessary work */ 4692 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4693 4694 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 4695 ixgbe_scrub_vfta(adapter, i); 4696} 4697 4698static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 4699{ 4700 u16 vid = 1; 4701 4702 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 4703 4704 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 4705 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 4706} 4707 4708/** 4709 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 4710 * @netdev: network interface device structure 4711 * 4712 * Writes multicast address list to the MTA hash table. 4713 * Returns: -ENOMEM on failure 4714 * 0 on no addresses written 4715 * X on writing X addresses to MTA 4716 **/ 4717static int ixgbe_write_mc_addr_list(struct net_device *netdev) 4718{ 4719 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4720 struct ixgbe_hw *hw = &adapter->hw; 4721 4722 if (!netif_running(netdev)) 4723 return 0; 4724 4725 if (hw->mac.ops.update_mc_addr_list) 4726 hw->mac.ops.update_mc_addr_list(hw, netdev); 4727 else 4728 return -ENOMEM; 4729 4730#ifdef CONFIG_PCI_IOV 4731 ixgbe_restore_vf_multicasts(adapter); 4732#endif 4733 4734 return netdev_mc_count(netdev); 4735} 4736 4737#ifdef CONFIG_PCI_IOV 4738void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 4739{ 4740 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4741 struct ixgbe_hw *hw = &adapter->hw; 4742 int i; 4743 4744 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4745 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4746 4747 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4748 hw->mac.ops.set_rar(hw, i, 4749 mac_table->addr, 4750 mac_table->pool, 4751 IXGBE_RAH_AV); 4752 else 4753 hw->mac.ops.clear_rar(hw, i); 4754 } 4755} 4756 4757#endif 4758static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 4759{ 4760 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4761 struct ixgbe_hw *hw = &adapter->hw; 4762 int i; 4763 4764 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4765 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 4766 continue; 4767 4768 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 4769 4770 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4771 hw->mac.ops.set_rar(hw, i, 4772 mac_table->addr, 4773 mac_table->pool, 4774 IXGBE_RAH_AV); 4775 else 4776 hw->mac.ops.clear_rar(hw, i); 4777 } 4778} 4779 4780static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 4781{ 4782 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4783 struct ixgbe_hw *hw = &adapter->hw; 4784 int i; 4785 4786 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4787 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4788 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4789 } 4790 4791 ixgbe_sync_mac_table(adapter); 4792} 4793 4794static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 4795{ 4796 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4797 struct ixgbe_hw *hw = &adapter->hw; 4798 int i, count = 0; 4799 4800 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4801 /* do not count default RAR as available */ 4802 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 4803 continue; 4804 4805 /* only count unused and addresses that belong to us */ 4806 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 4807 if (mac_table->pool != pool) 4808 continue; 4809 } 4810 4811 count++; 4812 } 4813 4814 return count; 4815} 4816 4817/* this function destroys the first RAR entry */ 4818static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 4819{ 4820 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4821 struct ixgbe_hw *hw = &adapter->hw; 4822 4823 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 4824 mac_table->pool = VMDQ_P(0); 4825 4826 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 4827 4828 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 4829 IXGBE_RAH_AV); 4830} 4831 4832int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 4833 const u8 *addr, u16 pool) 4834{ 4835 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4836 struct ixgbe_hw *hw = &adapter->hw; 4837 int i; 4838 4839 if (is_zero_ether_addr(addr)) 4840 return -EINVAL; 4841 4842 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4843 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 4844 continue; 4845 4846 ether_addr_copy(mac_table->addr, addr); 4847 mac_table->pool = pool; 4848 4849 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 4850 IXGBE_MAC_STATE_IN_USE; 4851 4852 ixgbe_sync_mac_table(adapter); 4853 4854 return i; 4855 } 4856 4857 return -ENOMEM; 4858} 4859 4860int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 4861 const u8 *addr, u16 pool) 4862{ 4863 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 4864 struct ixgbe_hw *hw = &adapter->hw; 4865 int i; 4866 4867 if (is_zero_ether_addr(addr)) 4868 return -EINVAL; 4869 4870 /* search table for addr, if found clear IN_USE flag and sync */ 4871 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 4872 /* we can only delete an entry if it is in use */ 4873 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 4874 continue; 4875 /* we only care about entries that belong to the given pool */ 4876 if (mac_table->pool != pool) 4877 continue; 4878 /* we only care about a specific MAC address */ 4879 if (!ether_addr_equal(addr, mac_table->addr)) 4880 continue; 4881 4882 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 4883 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 4884 4885 ixgbe_sync_mac_table(adapter); 4886 4887 return 0; 4888 } 4889 4890 return -ENOMEM; 4891} 4892 4893static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 4894{ 4895 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4896 int ret; 4897 4898 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 4899 4900 return min_t(int, ret, 0); 4901} 4902 4903static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 4904{ 4905 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4906 4907 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 4908 4909 return 0; 4910} 4911 4912/** 4913 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 4914 * @netdev: network interface device structure 4915 * 4916 * The set_rx_method entry point is called whenever the unicast/multicast 4917 * address list or the network interface flags are updated. This routine is 4918 * responsible for configuring the hardware for proper unicast, multicast and 4919 * promiscuous mode. 4920 **/ 4921void ixgbe_set_rx_mode(struct net_device *netdev) 4922{ 4923 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4924 struct ixgbe_hw *hw = &adapter->hw; 4925 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 4926 netdev_features_t features = netdev->features; 4927 int count; 4928 4929 /* Check for Promiscuous and All Multicast modes */ 4930 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4931 4932 /* set all bits that we expect to always be set */ 4933 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 4934 fctrl |= IXGBE_FCTRL_BAM; 4935 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 4936 fctrl |= IXGBE_FCTRL_PMCF; 4937 4938 /* clear the bits we are changing the status of */ 4939 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4940 if (netdev->flags & IFF_PROMISC) { 4941 hw->addr_ctrl.user_set_promisc = true; 4942 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4943 vmolr |= IXGBE_VMOLR_MPE; 4944 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 4945 } else { 4946 if (netdev->flags & IFF_ALLMULTI) { 4947 fctrl |= IXGBE_FCTRL_MPE; 4948 vmolr |= IXGBE_VMOLR_MPE; 4949 } 4950 hw->addr_ctrl.user_set_promisc = false; 4951 } 4952 4953 /* 4954 * Write addresses to available RAR registers, if there is not 4955 * sufficient space to store all the addresses then enable 4956 * unicast promiscuous mode 4957 */ 4958 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 4959 fctrl |= IXGBE_FCTRL_UPE; 4960 vmolr |= IXGBE_VMOLR_ROPE; 4961 } 4962 4963 /* Write addresses to the MTA, if the attempt fails 4964 * then we should just turn on promiscuous mode so 4965 * that we can at least receive multicast traffic 4966 */ 4967 count = ixgbe_write_mc_addr_list(netdev); 4968 if (count < 0) { 4969 fctrl |= IXGBE_FCTRL_MPE; 4970 vmolr |= IXGBE_VMOLR_MPE; 4971 } else if (count) { 4972 vmolr |= IXGBE_VMOLR_ROMPE; 4973 } 4974 4975 if (hw->mac.type != ixgbe_mac_82598EB) { 4976 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 4977 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 4978 IXGBE_VMOLR_ROPE); 4979 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 4980 } 4981 4982 /* This is useful for sniffing bad packets. */ 4983 if (features & NETIF_F_RXALL) { 4984 /* UPE and MPE will be handled by normal PROMISC logic 4985 * in e1000e_set_rx_mode */ 4986 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 4987 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 4988 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 4989 4990 fctrl &= ~(IXGBE_FCTRL_DPF); 4991 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 4992 } 4993 4994 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4995 4996 if (features & NETIF_F_HW_VLAN_CTAG_RX) 4997 ixgbe_vlan_strip_enable(adapter); 4998 else 4999 ixgbe_vlan_strip_disable(adapter); 5000 5001 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5002 ixgbe_vlan_promisc_disable(adapter); 5003 else 5004 ixgbe_vlan_promisc_enable(adapter); 5005} 5006 5007static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5008{ 5009 int q_idx; 5010 5011 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5012 napi_enable(&adapter->q_vector[q_idx]->napi); 5013} 5014 5015static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5016{ 5017 int q_idx; 5018 5019 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5020 napi_disable(&adapter->q_vector[q_idx]->napi); 5021} 5022 5023static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 5024{ 5025 struct ixgbe_adapter *adapter = netdev_priv(dev); 5026 struct ixgbe_hw *hw = &adapter->hw; 5027 struct udp_tunnel_info ti; 5028 5029 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5030 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5031 adapter->vxlan_port = ti.port; 5032 else 5033 adapter->geneve_port = ti.port; 5034 5035 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5036 ntohs(adapter->vxlan_port) | 5037 ntohs(adapter->geneve_port) << 5038 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5039 return 0; 5040} 5041 5042static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5043 .sync_table = ixgbe_udp_tunnel_sync, 5044 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5045 .tables = { 5046 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5047 }, 5048}; 5049 5050static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5051 .sync_table = ixgbe_udp_tunnel_sync, 5052 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5053 .tables = { 5054 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5055 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5056 }, 5057}; 5058 5059#ifdef CONFIG_IXGBE_DCB 5060/** 5061 * ixgbe_configure_dcb - Configure DCB hardware 5062 * @adapter: ixgbe adapter struct 5063 * 5064 * This is called by the driver on open to configure the DCB hardware. 5065 * This is also called by the gennetlink interface when reconfiguring 5066 * the DCB state. 5067 */ 5068static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5069{ 5070 struct ixgbe_hw *hw = &adapter->hw; 5071 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5072 5073 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5074 if (hw->mac.type == ixgbe_mac_82598EB) 5075 netif_set_tso_max_size(adapter->netdev, 65536); 5076 return; 5077 } 5078 5079 if (hw->mac.type == ixgbe_mac_82598EB) 5080 netif_set_tso_max_size(adapter->netdev, 32768); 5081 5082#ifdef IXGBE_FCOE 5083 if (adapter->netdev->features & NETIF_F_FCOE_MTU) 5084 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5085#endif 5086 5087 /* reconfigure the hardware */ 5088 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5089 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5090 DCB_TX_CONFIG); 5091 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5092 DCB_RX_CONFIG); 5093 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5094 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5095 ixgbe_dcb_hw_ets(&adapter->hw, 5096 adapter->ixgbe_ieee_ets, 5097 max_frame); 5098 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5099 adapter->ixgbe_ieee_pfc->pfc_en, 5100 adapter->ixgbe_ieee_ets->prio_tc); 5101 } 5102 5103 /* Enable RSS Hash per TC */ 5104 if (hw->mac.type != ixgbe_mac_82598EB) { 5105 u32 msb = 0; 5106 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5107 5108 while (rss_i) { 5109 msb++; 5110 rss_i >>= 1; 5111 } 5112 5113 /* write msb to all 8 TCs in one write */ 5114 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5115 } 5116} 5117#endif 5118 5119/* Additional bittime to account for IXGBE framing */ 5120#define IXGBE_ETH_FRAMING 20 5121 5122/** 5123 * ixgbe_hpbthresh - calculate high water mark for flow control 5124 * 5125 * @adapter: board private structure to calculate for 5126 * @pb: packet buffer to calculate 5127 */ 5128static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5129{ 5130 struct ixgbe_hw *hw = &adapter->hw; 5131 struct net_device *dev = adapter->netdev; 5132 int link, tc, kb, marker; 5133 u32 dv_id, rx_pba; 5134 5135 /* Calculate max LAN frame size */ 5136 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5137 5138#ifdef IXGBE_FCOE 5139 /* FCoE traffic class uses FCOE jumbo frames */ 5140 if ((dev->features & NETIF_F_FCOE_MTU) && 5141 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5142 (pb == ixgbe_fcoe_get_tc(adapter))) 5143 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5144#endif 5145 5146 /* Calculate delay value for device */ 5147 switch (hw->mac.type) { 5148 case ixgbe_mac_X540: 5149 case ixgbe_mac_X550: 5150 case ixgbe_mac_X550EM_x: 5151 case ixgbe_mac_x550em_a: 5152 dv_id = IXGBE_DV_X540(link, tc); 5153 break; 5154 default: 5155 dv_id = IXGBE_DV(link, tc); 5156 break; 5157 } 5158 5159 /* Loopback switch introduces additional latency */ 5160 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5161 dv_id += IXGBE_B2BT(tc); 5162 5163 /* Delay value is calculated in bit times convert to KB */ 5164 kb = IXGBE_BT2KB(dv_id); 5165 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5166 5167 marker = rx_pba - kb; 5168 5169 /* It is possible that the packet buffer is not large enough 5170 * to provide required headroom. In this case throw an error 5171 * to user and a do the best we can. 5172 */ 5173 if (marker < 0) { 5174 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5175 "headroom to support flow control." 5176 "Decrease MTU or number of traffic classes\n", pb); 5177 marker = tc + 1; 5178 } 5179 5180 return marker; 5181} 5182 5183/** 5184 * ixgbe_lpbthresh - calculate low water mark for flow control 5185 * 5186 * @adapter: board private structure to calculate for 5187 * @pb: packet buffer to calculate 5188 */ 5189static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5190{ 5191 struct ixgbe_hw *hw = &adapter->hw; 5192 struct net_device *dev = adapter->netdev; 5193 int tc; 5194 u32 dv_id; 5195 5196 /* Calculate max LAN frame size */ 5197 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5198 5199#ifdef IXGBE_FCOE 5200 /* FCoE traffic class uses FCOE jumbo frames */ 5201 if ((dev->features & NETIF_F_FCOE_MTU) && 5202 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && 5203 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5204 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5205#endif 5206 5207 /* Calculate delay value for device */ 5208 switch (hw->mac.type) { 5209 case ixgbe_mac_X540: 5210 case ixgbe_mac_X550: 5211 case ixgbe_mac_X550EM_x: 5212 case ixgbe_mac_x550em_a: 5213 dv_id = IXGBE_LOW_DV_X540(tc); 5214 break; 5215 default: 5216 dv_id = IXGBE_LOW_DV(tc); 5217 break; 5218 } 5219 5220 /* Delay value is calculated in bit times convert to KB */ 5221 return IXGBE_BT2KB(dv_id); 5222} 5223 5224/* 5225 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5226 */ 5227static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5228{ 5229 struct ixgbe_hw *hw = &adapter->hw; 5230 int num_tc = adapter->hw_tcs; 5231 int i; 5232 5233 if (!num_tc) 5234 num_tc = 1; 5235 5236 for (i = 0; i < num_tc; i++) { 5237 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5238 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5239 5240 /* Low water marks must not be larger than high water marks */ 5241 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5242 hw->fc.low_water[i] = 0; 5243 } 5244 5245 for (; i < MAX_TRAFFIC_CLASS; i++) 5246 hw->fc.high_water[i] = 0; 5247} 5248 5249static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5250{ 5251 struct ixgbe_hw *hw = &adapter->hw; 5252 int hdrm; 5253 u8 tc = adapter->hw_tcs; 5254 5255 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5256 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5257 hdrm = 32 << adapter->fdir_pballoc; 5258 else 5259 hdrm = 0; 5260 5261 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5262 ixgbe_pbthresh_setup(adapter); 5263} 5264 5265static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5266{ 5267 struct ixgbe_hw *hw = &adapter->hw; 5268 struct hlist_node *node2; 5269 struct ixgbe_fdir_filter *filter; 5270 u8 queue; 5271 5272 spin_lock(&adapter->fdir_perfect_lock); 5273 5274 if (!hlist_empty(&adapter->fdir_filter_list)) 5275 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5276 5277 hlist_for_each_entry_safe(filter, node2, 5278 &adapter->fdir_filter_list, fdir_node) { 5279 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5280 queue = IXGBE_FDIR_DROP_QUEUE; 5281 } else { 5282 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5283 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5284 5285 if (!vf && (ring >= adapter->num_rx_queues)) { 5286 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5287 ring); 5288 continue; 5289 } else if (vf && 5290 ((vf > adapter->num_vfs) || 5291 ring >= adapter->num_rx_queues_per_pool)) { 5292 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5293 vf, ring); 5294 continue; 5295 } 5296 5297 /* Map the ring onto the absolute queue index */ 5298 if (!vf) 5299 queue = adapter->rx_ring[ring]->reg_idx; 5300 else 5301 queue = ((vf - 1) * 5302 adapter->num_rx_queues_per_pool) + ring; 5303 } 5304 5305 ixgbe_fdir_write_perfect_filter_82599(hw, 5306 &filter->filter, filter->sw_idx, queue); 5307 } 5308 5309 spin_unlock(&adapter->fdir_perfect_lock); 5310} 5311 5312/** 5313 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5314 * @rx_ring: ring to free buffers from 5315 **/ 5316static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5317{ 5318 u16 i = rx_ring->next_to_clean; 5319 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5320 5321 if (rx_ring->xsk_pool) { 5322 ixgbe_xsk_clean_rx_ring(rx_ring); 5323 goto skip_free; 5324 } 5325 5326 /* Free all the Rx ring sk_buffs */ 5327 while (i != rx_ring->next_to_alloc) { 5328 if (rx_buffer->skb) { 5329 struct sk_buff *skb = rx_buffer->skb; 5330 if (IXGBE_CB(skb)->page_released) 5331 dma_unmap_page_attrs(rx_ring->dev, 5332 IXGBE_CB(skb)->dma, 5333 ixgbe_rx_pg_size(rx_ring), 5334 DMA_FROM_DEVICE, 5335 IXGBE_RX_DMA_ATTR); 5336 dev_kfree_skb(skb); 5337 } 5338 5339 /* Invalidate cache lines that may have been written to by 5340 * device so that we avoid corrupting memory. 5341 */ 5342 dma_sync_single_range_for_cpu(rx_ring->dev, 5343 rx_buffer->dma, 5344 rx_buffer->page_offset, 5345 ixgbe_rx_bufsz(rx_ring), 5346 DMA_FROM_DEVICE); 5347 5348 /* free resources associated with mapping */ 5349 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5350 ixgbe_rx_pg_size(rx_ring), 5351 DMA_FROM_DEVICE, 5352 IXGBE_RX_DMA_ATTR); 5353 __page_frag_cache_drain(rx_buffer->page, 5354 rx_buffer->pagecnt_bias); 5355 5356 i++; 5357 rx_buffer++; 5358 if (i == rx_ring->count) { 5359 i = 0; 5360 rx_buffer = rx_ring->rx_buffer_info; 5361 } 5362 } 5363 5364skip_free: 5365 rx_ring->next_to_alloc = 0; 5366 rx_ring->next_to_clean = 0; 5367 rx_ring->next_to_use = 0; 5368} 5369 5370static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5371 struct ixgbe_fwd_adapter *accel) 5372{ 5373 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5374 int num_tc = netdev_get_num_tc(adapter->netdev); 5375 struct net_device *vdev = accel->netdev; 5376 int i, baseq, err; 5377 5378 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5379 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5380 accel->pool, adapter->num_rx_pools, 5381 baseq, baseq + adapter->num_rx_queues_per_pool); 5382 5383 accel->rx_base_queue = baseq; 5384 accel->tx_base_queue = baseq; 5385 5386 /* record configuration for macvlan interface in vdev */ 5387 for (i = 0; i < num_tc; i++) 5388 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5389 i, rss_i, baseq + (rss_i * i)); 5390 5391 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5392 adapter->rx_ring[baseq + i]->netdev = vdev; 5393 5394 /* Guarantee all rings are updated before we update the 5395 * MAC address filter. 5396 */ 5397 wmb(); 5398 5399 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5400 * need to only treat it as an error value if it is negative. 5401 */ 5402 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5403 VMDQ_P(accel->pool)); 5404 if (err >= 0) 5405 return 0; 5406 5407 /* if we cannot add the MAC rule then disable the offload */ 5408 macvlan_release_l2fw_offload(vdev); 5409 5410 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5411 adapter->rx_ring[baseq + i]->netdev = NULL; 5412 5413 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5414 5415 /* unbind the queues and drop the subordinate channel config */ 5416 netdev_unbind_sb_channel(adapter->netdev, vdev); 5417 netdev_set_sb_channel(vdev, 0); 5418 5419 clear_bit(accel->pool, adapter->fwd_bitmask); 5420 kfree(accel); 5421 5422 return err; 5423} 5424 5425static int ixgbe_macvlan_up(struct net_device *vdev, 5426 struct netdev_nested_priv *priv) 5427{ 5428 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5429 struct ixgbe_fwd_adapter *accel; 5430 5431 if (!netif_is_macvlan(vdev)) 5432 return 0; 5433 5434 accel = macvlan_accel_priv(vdev); 5435 if (!accel) 5436 return 0; 5437 5438 ixgbe_fwd_ring_up(adapter, accel); 5439 5440 return 0; 5441} 5442 5443static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5444{ 5445 struct netdev_nested_priv priv = { 5446 .data = (void *)adapter, 5447 }; 5448 5449 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5450 ixgbe_macvlan_up, &priv); 5451} 5452 5453static void ixgbe_configure(struct ixgbe_adapter *adapter) 5454{ 5455 struct ixgbe_hw *hw = &adapter->hw; 5456 5457 ixgbe_configure_pb(adapter); 5458#ifdef CONFIG_IXGBE_DCB 5459 ixgbe_configure_dcb(adapter); 5460#endif 5461 /* 5462 * We must restore virtualization before VLANs or else 5463 * the VLVF registers will not be populated 5464 */ 5465 ixgbe_configure_virtualization(adapter); 5466 5467 ixgbe_set_rx_mode(adapter->netdev); 5468 ixgbe_restore_vlan(adapter); 5469 ixgbe_ipsec_restore(adapter); 5470 5471 switch (hw->mac.type) { 5472 case ixgbe_mac_82599EB: 5473 case ixgbe_mac_X540: 5474 hw->mac.ops.disable_rx_buff(hw); 5475 break; 5476 default: 5477 break; 5478 } 5479 5480 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5481 ixgbe_init_fdir_signature_82599(&adapter->hw, 5482 adapter->fdir_pballoc); 5483 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5484 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5485 adapter->fdir_pballoc); 5486 ixgbe_fdir_filter_restore(adapter); 5487 } 5488 5489 switch (hw->mac.type) { 5490 case ixgbe_mac_82599EB: 5491 case ixgbe_mac_X540: 5492 hw->mac.ops.enable_rx_buff(hw); 5493 break; 5494 default: 5495 break; 5496 } 5497 5498#ifdef CONFIG_IXGBE_DCA 5499 /* configure DCA */ 5500 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5501 ixgbe_setup_dca(adapter); 5502#endif /* CONFIG_IXGBE_DCA */ 5503 5504#ifdef IXGBE_FCOE 5505 /* configure FCoE L2 filters, redirection table, and Rx control */ 5506 ixgbe_configure_fcoe(adapter); 5507 5508#endif /* IXGBE_FCOE */ 5509 ixgbe_configure_tx(adapter); 5510 ixgbe_configure_rx(adapter); 5511 ixgbe_configure_dfwd(adapter); 5512} 5513 5514/** 5515 * ixgbe_sfp_link_config - set up SFP+ link 5516 * @adapter: pointer to private adapter struct 5517 **/ 5518static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5519{ 5520 /* 5521 * We are assuming the worst case scenario here, and that 5522 * is that an SFP was inserted/removed after the reset 5523 * but before SFP detection was enabled. As such the best 5524 * solution is to just start searching as soon as we start 5525 */ 5526 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5527 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5528 5529 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5530 adapter->sfp_poll_time = 0; 5531} 5532 5533/** 5534 * ixgbe_non_sfp_link_config - set up non-SFP+ link 5535 * @hw: pointer to private hardware struct 5536 * 5537 * Returns 0 on success, negative on failure 5538 **/ 5539static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 5540{ 5541 u32 speed; 5542 bool autoneg, link_up = false; 5543 int ret = -EIO; 5544 5545 if (hw->mac.ops.check_link) 5546 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 5547 5548 if (ret) 5549 return ret; 5550 5551 speed = hw->phy.autoneg_advertised; 5552 if (!speed && hw->mac.ops.get_link_capabilities) { 5553 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 5554 &autoneg); 5555 /* remove NBASE-T speeds from default autonegotiation 5556 * to accommodate broken network switches in the field 5557 * which cannot cope with advertised NBASE-T speeds 5558 */ 5559 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 5560 IXGBE_LINK_SPEED_2_5GB_FULL); 5561 } 5562 5563 if (ret) 5564 return ret; 5565 5566 if (hw->mac.ops.setup_link) 5567 ret = hw->mac.ops.setup_link(hw, speed, link_up); 5568 5569 return ret; 5570} 5571 5572/** 5573 * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset 5574 * @adapter: board private structure 5575 * 5576 * On a reset we need to clear out the VF stats or accounting gets 5577 * messed up because they're not clear on read. 5578 **/ 5579static void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter) 5580{ 5581 struct ixgbe_hw *hw = &adapter->hw; 5582 int i; 5583 5584 for (i = 0; i < adapter->num_vfs; i++) { 5585 adapter->vfinfo[i].last_vfstats.gprc = 5586 IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i)); 5587 adapter->vfinfo[i].saved_rst_vfstats.gprc += 5588 adapter->vfinfo[i].vfstats.gprc; 5589 adapter->vfinfo[i].vfstats.gprc = 0; 5590 adapter->vfinfo[i].last_vfstats.gptc = 5591 IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i)); 5592 adapter->vfinfo[i].saved_rst_vfstats.gptc += 5593 adapter->vfinfo[i].vfstats.gptc; 5594 adapter->vfinfo[i].vfstats.gptc = 0; 5595 adapter->vfinfo[i].last_vfstats.gorc = 5596 IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i)); 5597 adapter->vfinfo[i].saved_rst_vfstats.gorc += 5598 adapter->vfinfo[i].vfstats.gorc; 5599 adapter->vfinfo[i].vfstats.gorc = 0; 5600 adapter->vfinfo[i].last_vfstats.gotc = 5601 IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i)); 5602 adapter->vfinfo[i].saved_rst_vfstats.gotc += 5603 adapter->vfinfo[i].vfstats.gotc; 5604 adapter->vfinfo[i].vfstats.gotc = 0; 5605 adapter->vfinfo[i].last_vfstats.mprc = 5606 IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i)); 5607 adapter->vfinfo[i].saved_rst_vfstats.mprc += 5608 adapter->vfinfo[i].vfstats.mprc; 5609 adapter->vfinfo[i].vfstats.mprc = 0; 5610 } 5611} 5612 5613static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 5614{ 5615 struct ixgbe_hw *hw = &adapter->hw; 5616 u32 gpie = 0; 5617 5618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 5619 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5620 IXGBE_GPIE_OCD; 5621 gpie |= IXGBE_GPIE_EIAME; 5622 /* 5623 * use EIAM to auto-mask when MSI-X interrupt is asserted 5624 * this saves a register write for every interrupt 5625 */ 5626 switch (hw->mac.type) { 5627 case ixgbe_mac_82598EB: 5628 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5629 break; 5630 case ixgbe_mac_82599EB: 5631 case ixgbe_mac_X540: 5632 case ixgbe_mac_X550: 5633 case ixgbe_mac_X550EM_x: 5634 case ixgbe_mac_x550em_a: 5635 default: 5636 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5637 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5638 break; 5639 } 5640 } else { 5641 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 5642 * specifically only auto mask tx and rx interrupts */ 5643 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5644 } 5645 5646 /* XXX: to interrupt immediately for EICS writes, enable this */ 5647 /* gpie |= IXGBE_GPIE_EIMEN; */ 5648 5649 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 5650 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 5651 5652 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 5653 case IXGBE_82599_VMDQ_8Q_MASK: 5654 gpie |= IXGBE_GPIE_VTMODE_16; 5655 break; 5656 case IXGBE_82599_VMDQ_4Q_MASK: 5657 gpie |= IXGBE_GPIE_VTMODE_32; 5658 break; 5659 default: 5660 gpie |= IXGBE_GPIE_VTMODE_64; 5661 break; 5662 } 5663 } 5664 5665 /* Enable Thermal over heat sensor interrupt */ 5666 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 5667 switch (adapter->hw.mac.type) { 5668 case ixgbe_mac_82599EB: 5669 gpie |= IXGBE_SDP0_GPIEN_8259X; 5670 break; 5671 default: 5672 break; 5673 } 5674 } 5675 5676 /* Enable fan failure interrupt */ 5677 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 5678 gpie |= IXGBE_SDP1_GPIEN(hw); 5679 5680 switch (hw->mac.type) { 5681 case ixgbe_mac_82599EB: 5682 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 5683 break; 5684 case ixgbe_mac_X550EM_x: 5685 case ixgbe_mac_x550em_a: 5686 gpie |= IXGBE_SDP0_GPIEN_X540; 5687 break; 5688 default: 5689 break; 5690 } 5691 5692 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5693} 5694 5695static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 5696{ 5697 struct ixgbe_hw *hw = &adapter->hw; 5698 int err; 5699 u32 ctrl_ext; 5700 5701 ixgbe_get_hw_control(adapter); 5702 ixgbe_setup_gpie(adapter); 5703 5704 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 5705 ixgbe_configure_msix(adapter); 5706 else 5707 ixgbe_configure_msi_and_legacy(adapter); 5708 5709 /* enable the optics for 82599 SFP+ fiber */ 5710 if (hw->mac.ops.enable_tx_laser) 5711 hw->mac.ops.enable_tx_laser(hw); 5712 5713 if (hw->phy.ops.set_phy_power) 5714 hw->phy.ops.set_phy_power(hw, true); 5715 5716 smp_mb__before_atomic(); 5717 clear_bit(__IXGBE_DOWN, &adapter->state); 5718 ixgbe_napi_enable_all(adapter); 5719 5720 if (ixgbe_is_sfp(hw)) { 5721 ixgbe_sfp_link_config(adapter); 5722 } else { 5723 err = ixgbe_non_sfp_link_config(hw); 5724 if (err) 5725 e_err(probe, "link_config FAILED %d\n", err); 5726 } 5727 5728 /* clear any pending interrupts, may auto mask */ 5729 IXGBE_READ_REG(hw, IXGBE_EICR); 5730 ixgbe_irq_enable(adapter, true, true); 5731 5732 /* 5733 * If this adapter has a fan, check to see if we had a failure 5734 * before we enabled the interrupt. 5735 */ 5736 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 5737 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 5738 if (esdp & IXGBE_ESDP_SDP1) 5739 e_crit(drv, "Fan has stopped, replace the adapter\n"); 5740 } 5741 5742 /* bring the link up in the watchdog, this could race with our first 5743 * link up interrupt but shouldn't be a problem */ 5744 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 5745 adapter->link_check_timeout = jiffies; 5746 mod_timer(&adapter->service_timer, jiffies); 5747 5748 ixgbe_clear_vf_stats_counters(adapter); 5749 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 5750 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 5751 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 5752 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 5753 5754 /* update setting rx tx for all active vfs */ 5755 ixgbe_set_all_vfs(adapter); 5756} 5757 5758void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 5759{ 5760 /* put off any impending NetWatchDogTimeout */ 5761 netif_trans_update(adapter->netdev); 5762 5763 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 5764 usleep_range(1000, 2000); 5765 if (adapter->hw.phy.type == ixgbe_phy_fw) 5766 ixgbe_watchdog_link_is_down(adapter); 5767 ixgbe_down(adapter); 5768 /* 5769 * If SR-IOV enabled then wait a bit before bringing the adapter 5770 * back up to give the VFs time to respond to the reset. The 5771 * two second wait is based upon the watchdog timer cycle in 5772 * the VF driver. 5773 */ 5774 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5775 msleep(2000); 5776 ixgbe_up(adapter); 5777 clear_bit(__IXGBE_RESETTING, &adapter->state); 5778} 5779 5780void ixgbe_up(struct ixgbe_adapter *adapter) 5781{ 5782 /* hardware has been reset, we need to reload some things */ 5783 ixgbe_configure(adapter); 5784 5785 ixgbe_up_complete(adapter); 5786} 5787 5788static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 5789{ 5790 u16 devctl2; 5791 5792 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 5793 5794 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 5795 case IXGBE_PCIDEVCTRL2_17_34s: 5796 case IXGBE_PCIDEVCTRL2_4_8s: 5797 /* For now we cap the upper limit on delay to 2 seconds 5798 * as we end up going up to 34 seconds of delay in worst 5799 * case timeout value. 5800 */ 5801 case IXGBE_PCIDEVCTRL2_1_2s: 5802 return 2000000ul; /* 2.0 s */ 5803 case IXGBE_PCIDEVCTRL2_260_520ms: 5804 return 520000ul; /* 520 ms */ 5805 case IXGBE_PCIDEVCTRL2_65_130ms: 5806 return 130000ul; /* 130 ms */ 5807 case IXGBE_PCIDEVCTRL2_16_32ms: 5808 return 32000ul; /* 32 ms */ 5809 case IXGBE_PCIDEVCTRL2_1_2ms: 5810 return 2000ul; /* 2 ms */ 5811 case IXGBE_PCIDEVCTRL2_50_100us: 5812 return 100ul; /* 100 us */ 5813 case IXGBE_PCIDEVCTRL2_16_32ms_def: 5814 return 32000ul; /* 32 ms */ 5815 default: 5816 break; 5817 } 5818 5819 /* We shouldn't need to hit this path, but just in case default as 5820 * though completion timeout is not supported and support 32ms. 5821 */ 5822 return 32000ul; 5823} 5824 5825void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 5826{ 5827 unsigned long wait_delay, delay_interval; 5828 struct ixgbe_hw *hw = &adapter->hw; 5829 int i, wait_loop; 5830 u32 rxdctl; 5831 5832 /* disable receives */ 5833 hw->mac.ops.disable_rx(hw); 5834 5835 if (ixgbe_removed(hw->hw_addr)) 5836 return; 5837 5838 /* disable all enabled Rx queues */ 5839 for (i = 0; i < adapter->num_rx_queues; i++) { 5840 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5841 u8 reg_idx = ring->reg_idx; 5842 5843 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5844 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 5845 rxdctl |= IXGBE_RXDCTL_SWFLSH; 5846 5847 /* write value back with RXDCTL.ENABLE bit cleared */ 5848 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 5849 } 5850 5851 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 5852 if (hw->mac.type == ixgbe_mac_82598EB && 5853 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5854 return; 5855 5856 /* Determine our minimum delay interval. We will increase this value 5857 * with each subsequent test. This way if the device returns quickly 5858 * we should spend as little time as possible waiting, however as 5859 * the time increases we will wait for larger periods of time. 5860 * 5861 * The trick here is that we increase the interval using the 5862 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5863 * of that wait is that it totals up to 100x whatever interval we 5864 * choose. Since our minimum wait is 100us we can just divide the 5865 * total timeout by 100 to get our minimum delay interval. 5866 */ 5867 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5868 5869 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5870 wait_delay = delay_interval; 5871 5872 while (wait_loop--) { 5873 usleep_range(wait_delay, wait_delay + 10); 5874 wait_delay += delay_interval * 2; 5875 rxdctl = 0; 5876 5877 /* OR together the reading of all the active RXDCTL registers, 5878 * and then test the result. We need the disable to complete 5879 * before we start freeing the memory and invalidating the 5880 * DMA mappings. 5881 */ 5882 for (i = 0; i < adapter->num_rx_queues; i++) { 5883 struct ixgbe_ring *ring = adapter->rx_ring[i]; 5884 u8 reg_idx = ring->reg_idx; 5885 5886 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 5887 } 5888 5889 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 5890 return; 5891 } 5892 5893 e_err(drv, 5894 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5895} 5896 5897void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 5898{ 5899 unsigned long wait_delay, delay_interval; 5900 struct ixgbe_hw *hw = &adapter->hw; 5901 int i, wait_loop; 5902 u32 txdctl; 5903 5904 if (ixgbe_removed(hw->hw_addr)) 5905 return; 5906 5907 /* disable all enabled Tx queues */ 5908 for (i = 0; i < adapter->num_tx_queues; i++) { 5909 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5910 u8 reg_idx = ring->reg_idx; 5911 5912 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5913 } 5914 5915 /* disable all enabled XDP Tx queues */ 5916 for (i = 0; i < adapter->num_xdp_queues; i++) { 5917 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5918 u8 reg_idx = ring->reg_idx; 5919 5920 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 5921 } 5922 5923 /* If the link is not up there shouldn't be much in the way of 5924 * pending transactions. Those that are left will be flushed out 5925 * when the reset logic goes through the flush sequence to clean out 5926 * the pending Tx transactions. 5927 */ 5928 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 5929 goto dma_engine_disable; 5930 5931 /* Determine our minimum delay interval. We will increase this value 5932 * with each subsequent test. This way if the device returns quickly 5933 * we should spend as little time as possible waiting, however as 5934 * the time increases we will wait for larger periods of time. 5935 * 5936 * The trick here is that we increase the interval using the 5937 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 5938 * of that wait is that it totals up to 100x whatever interval we 5939 * choose. Since our minimum wait is 100us we can just divide the 5940 * total timeout by 100 to get our minimum delay interval. 5941 */ 5942 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 5943 5944 wait_loop = IXGBE_MAX_RX_DESC_POLL; 5945 wait_delay = delay_interval; 5946 5947 while (wait_loop--) { 5948 usleep_range(wait_delay, wait_delay + 10); 5949 wait_delay += delay_interval * 2; 5950 txdctl = 0; 5951 5952 /* OR together the reading of all the active TXDCTL registers, 5953 * and then test the result. We need the disable to complete 5954 * before we start freeing the memory and invalidating the 5955 * DMA mappings. 5956 */ 5957 for (i = 0; i < adapter->num_tx_queues; i++) { 5958 struct ixgbe_ring *ring = adapter->tx_ring[i]; 5959 u8 reg_idx = ring->reg_idx; 5960 5961 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5962 } 5963 for (i = 0; i < adapter->num_xdp_queues; i++) { 5964 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 5965 u8 reg_idx = ring->reg_idx; 5966 5967 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 5968 } 5969 5970 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 5971 goto dma_engine_disable; 5972 } 5973 5974 e_err(drv, 5975 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 5976 5977dma_engine_disable: 5978 /* Disable the Tx DMA engine on 82599 and later MAC */ 5979 switch (hw->mac.type) { 5980 case ixgbe_mac_82599EB: 5981 case ixgbe_mac_X540: 5982 case ixgbe_mac_X550: 5983 case ixgbe_mac_X550EM_x: 5984 case ixgbe_mac_x550em_a: 5985 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 5986 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 5987 ~IXGBE_DMATXCTL_TE)); 5988 fallthrough; 5989 default: 5990 break; 5991 } 5992} 5993 5994void ixgbe_reset(struct ixgbe_adapter *adapter) 5995{ 5996 struct ixgbe_hw *hw = &adapter->hw; 5997 struct net_device *netdev = adapter->netdev; 5998 int err; 5999 6000 if (ixgbe_removed(hw->hw_addr)) 6001 return; 6002 /* lock SFP init bit to prevent race conditions with the watchdog */ 6003 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6004 usleep_range(1000, 2000); 6005 6006 /* clear all SFP and link config related flags while holding SFP_INIT */ 6007 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 6008 IXGBE_FLAG2_SFP_NEEDS_RESET); 6009 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6010 6011 err = hw->mac.ops.init_hw(hw); 6012 switch (err) { 6013 case 0: 6014 case -ENOENT: 6015 case -EOPNOTSUPP: 6016 break; 6017 case -EALREADY: 6018 e_dev_err("primary disable timed out\n"); 6019 break; 6020 case -EACCES: 6021 /* We are running on a pre-production device, log a warning */ 6022 e_dev_warn("This device is a pre-production adapter/LOM. " 6023 "Please be aware there may be issues associated with " 6024 "your hardware. If you are experiencing problems " 6025 "please contact your Intel or hardware " 6026 "representative who provided you with this " 6027 "hardware.\n"); 6028 break; 6029 default: 6030 e_dev_err("Hardware Error: %d\n", err); 6031 } 6032 6033 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6034 6035 /* flush entries out of MAC table */ 6036 ixgbe_flush_sw_mac_table(adapter); 6037 __dev_uc_unsync(netdev, NULL); 6038 6039 /* do not flush user set addresses */ 6040 ixgbe_mac_set_default_filter(adapter); 6041 6042 /* update SAN MAC vmdq pool selection */ 6043 if (hw->mac.san_mac_rar_index) 6044 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 6045 6046 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6047 ixgbe_ptp_reset(adapter); 6048 6049 if (hw->phy.ops.set_phy_power) { 6050 if (!netif_running(adapter->netdev) && !adapter->wol) 6051 hw->phy.ops.set_phy_power(hw, false); 6052 else 6053 hw->phy.ops.set_phy_power(hw, true); 6054 } 6055} 6056 6057/** 6058 * ixgbe_clean_tx_ring - Free Tx Buffers 6059 * @tx_ring: ring to be cleaned 6060 **/ 6061static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 6062{ 6063 u16 i = tx_ring->next_to_clean; 6064 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 6065 6066 if (tx_ring->xsk_pool) { 6067 ixgbe_xsk_clean_tx_ring(tx_ring); 6068 goto out; 6069 } 6070 6071 while (i != tx_ring->next_to_use) { 6072 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 6073 6074 /* Free all the Tx ring sk_buffs */ 6075 if (ring_is_xdp(tx_ring)) 6076 xdp_return_frame(tx_buffer->xdpf); 6077 else 6078 dev_kfree_skb_any(tx_buffer->skb); 6079 6080 /* unmap skb header data */ 6081 dma_unmap_single(tx_ring->dev, 6082 dma_unmap_addr(tx_buffer, dma), 6083 dma_unmap_len(tx_buffer, len), 6084 DMA_TO_DEVICE); 6085 6086 /* check for eop_desc to determine the end of the packet */ 6087 eop_desc = tx_buffer->next_to_watch; 6088 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6089 6090 /* unmap remaining buffers */ 6091 while (tx_desc != eop_desc) { 6092 tx_buffer++; 6093 tx_desc++; 6094 i++; 6095 if (unlikely(i == tx_ring->count)) { 6096 i = 0; 6097 tx_buffer = tx_ring->tx_buffer_info; 6098 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6099 } 6100 6101 /* unmap any remaining paged data */ 6102 if (dma_unmap_len(tx_buffer, len)) 6103 dma_unmap_page(tx_ring->dev, 6104 dma_unmap_addr(tx_buffer, dma), 6105 dma_unmap_len(tx_buffer, len), 6106 DMA_TO_DEVICE); 6107 } 6108 6109 /* move us one more past the eop_desc for start of next pkt */ 6110 tx_buffer++; 6111 i++; 6112 if (unlikely(i == tx_ring->count)) { 6113 i = 0; 6114 tx_buffer = tx_ring->tx_buffer_info; 6115 } 6116 } 6117 6118 /* reset BQL for queue */ 6119 if (!ring_is_xdp(tx_ring)) 6120 netdev_tx_reset_queue(txring_txq(tx_ring)); 6121 6122out: 6123 /* reset next_to_use and next_to_clean */ 6124 tx_ring->next_to_use = 0; 6125 tx_ring->next_to_clean = 0; 6126} 6127 6128/** 6129 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6130 * @adapter: board private structure 6131 **/ 6132static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6133{ 6134 int i; 6135 6136 for (i = 0; i < adapter->num_rx_queues; i++) 6137 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6138} 6139 6140/** 6141 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6142 * @adapter: board private structure 6143 **/ 6144static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6145{ 6146 int i; 6147 6148 for (i = 0; i < adapter->num_tx_queues; i++) 6149 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6150 for (i = 0; i < adapter->num_xdp_queues; i++) 6151 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6152} 6153 6154static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6155{ 6156 struct hlist_node *node2; 6157 struct ixgbe_fdir_filter *filter; 6158 6159 spin_lock(&adapter->fdir_perfect_lock); 6160 6161 hlist_for_each_entry_safe(filter, node2, 6162 &adapter->fdir_filter_list, fdir_node) { 6163 hlist_del(&filter->fdir_node); 6164 kfree(filter); 6165 } 6166 adapter->fdir_filter_count = 0; 6167 6168 spin_unlock(&adapter->fdir_perfect_lock); 6169} 6170 6171void ixgbe_down(struct ixgbe_adapter *adapter) 6172{ 6173 struct net_device *netdev = adapter->netdev; 6174 struct ixgbe_hw *hw = &adapter->hw; 6175 int i; 6176 6177 /* signal that we are down to the interrupt handler */ 6178 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6179 return; /* do nothing if already down */ 6180 6181 /* Shut off incoming Tx traffic */ 6182 netif_tx_stop_all_queues(netdev); 6183 6184 /* call carrier off first to avoid false dev_watchdog timeouts */ 6185 netif_carrier_off(netdev); 6186 netif_tx_disable(netdev); 6187 6188 /* Disable Rx */ 6189 ixgbe_disable_rx(adapter); 6190 6191 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6192 if (adapter->xdp_ring[0]) 6193 synchronize_rcu(); 6194 6195 ixgbe_irq_disable(adapter); 6196 6197 ixgbe_napi_disable_all(adapter); 6198 6199 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6200 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6201 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6202 6203 del_timer_sync(&adapter->service_timer); 6204 6205 if (adapter->num_vfs) { 6206 /* Clear EITR Select mapping */ 6207 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6208 6209 /* Mark all the VFs as inactive */ 6210 for (i = 0 ; i < adapter->num_vfs; i++) 6211 adapter->vfinfo[i].clear_to_send = false; 6212 6213 /* update setting rx tx for all active vfs */ 6214 ixgbe_set_all_vfs(adapter); 6215 } 6216 6217 /* disable transmits in the hardware now that interrupts are off */ 6218 ixgbe_disable_tx(adapter); 6219 6220 if (!pci_channel_offline(adapter->pdev)) 6221 ixgbe_reset(adapter); 6222 6223 /* power down the optics for 82599 SFP+ fiber */ 6224 if (hw->mac.ops.disable_tx_laser) 6225 hw->mac.ops.disable_tx_laser(hw); 6226 6227 ixgbe_clean_all_tx_rings(adapter); 6228 ixgbe_clean_all_rx_rings(adapter); 6229} 6230 6231/** 6232 * ixgbe_set_eee_capable - helper function to determine EEE support on X550 6233 * @adapter: board private structure 6234 */ 6235static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6236{ 6237 struct ixgbe_hw *hw = &adapter->hw; 6238 6239 switch (hw->device_id) { 6240 case IXGBE_DEV_ID_X550EM_A_1G_T: 6241 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6242 if (!hw->phy.eee_speeds_supported) 6243 break; 6244 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6245 if (!hw->phy.eee_speeds_advertised) 6246 break; 6247 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6248 break; 6249 default: 6250 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6251 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6252 break; 6253 } 6254} 6255 6256/** 6257 * ixgbe_tx_timeout - Respond to a Tx Hang 6258 * @netdev: network interface device structure 6259 * @txqueue: queue number that timed out 6260 **/ 6261static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6262{ 6263 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6264 6265 /* Do the reset outside of interrupt context */ 6266 ixgbe_tx_timeout_reset(adapter); 6267} 6268 6269#ifdef CONFIG_IXGBE_DCB 6270static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6271{ 6272 struct ixgbe_hw *hw = &adapter->hw; 6273 struct tc_configuration *tc; 6274 int j; 6275 6276 switch (hw->mac.type) { 6277 case ixgbe_mac_82598EB: 6278 case ixgbe_mac_82599EB: 6279 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6280 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6281 break; 6282 case ixgbe_mac_X540: 6283 case ixgbe_mac_X550: 6284 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6285 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6286 break; 6287 case ixgbe_mac_X550EM_x: 6288 case ixgbe_mac_x550em_a: 6289 default: 6290 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6291 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6292 break; 6293 } 6294 6295 /* Configure DCB traffic classes */ 6296 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6297 tc = &adapter->dcb_cfg.tc_config[j]; 6298 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6299 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6300 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6301 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6302 tc->dcb_pfc = pfc_disabled; 6303 } 6304 6305 /* Initialize default user to priority mapping, UPx->TC0 */ 6306 tc = &adapter->dcb_cfg.tc_config[0]; 6307 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6308 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6309 6310 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6311 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6312 adapter->dcb_cfg.pfc_mode_enable = false; 6313 adapter->dcb_set_bitmap = 0x00; 6314 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6315 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6316 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6317 sizeof(adapter->temp_dcb_cfg)); 6318} 6319#endif 6320 6321/** 6322 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6323 * @adapter: board private structure to initialize 6324 * @ii: pointer to ixgbe_info for device 6325 * 6326 * ixgbe_sw_init initializes the Adapter private data structure. 6327 * Fields are initialized based on PCI device information and 6328 * OS network device settings (MTU size). 6329 **/ 6330static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6331 const struct ixgbe_info *ii) 6332{ 6333 struct ixgbe_hw *hw = &adapter->hw; 6334 struct pci_dev *pdev = adapter->pdev; 6335 unsigned int rss, fdir; 6336 u32 fwsm; 6337 int i; 6338 6339 /* PCI config space info */ 6340 6341 hw->vendor_id = pdev->vendor; 6342 hw->device_id = pdev->device; 6343 hw->revision_id = pdev->revision; 6344 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6345 hw->subsystem_device_id = pdev->subsystem_device; 6346 6347 /* get_invariants needs the device IDs */ 6348 ii->get_invariants(hw); 6349 6350 /* Set common capability flags and settings */ 6351 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6352 adapter->ring_feature[RING_F_RSS].limit = rss; 6353 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6354 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6355 adapter->atr_sample_rate = 20; 6356 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6357 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6358 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6359 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6360#ifdef CONFIG_IXGBE_DCA 6361 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6362#endif 6363#ifdef CONFIG_IXGBE_DCB 6364 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6365 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6366#endif 6367#ifdef IXGBE_FCOE 6368 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6369 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6370#ifdef CONFIG_IXGBE_DCB 6371 /* Default traffic class to use for FCoE */ 6372 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6373#endif /* CONFIG_IXGBE_DCB */ 6374#endif /* IXGBE_FCOE */ 6375 6376 /* initialize static ixgbe jump table entries */ 6377 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), 6378 GFP_KERNEL); 6379 if (!adapter->jump_tables[0]) 6380 return -ENOMEM; 6381 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6382 6383 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6384 adapter->jump_tables[i] = NULL; 6385 6386 adapter->mac_table = kcalloc(hw->mac.num_rar_entries, 6387 sizeof(struct ixgbe_mac_addr), 6388 GFP_KERNEL); 6389 if (!adapter->mac_table) 6390 return -ENOMEM; 6391 6392 if (ixgbe_init_rss_key(adapter)) 6393 return -ENOMEM; 6394 6395 adapter->af_xdp_zc_qps = bitmap_zalloc(IXGBE_MAX_XDP_QS, GFP_KERNEL); 6396 if (!adapter->af_xdp_zc_qps) 6397 return -ENOMEM; 6398 6399 /* Set MAC specific capability flags and exceptions */ 6400 switch (hw->mac.type) { 6401 case ixgbe_mac_82598EB: 6402 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6403 6404 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6405 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6406 6407 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6408 adapter->ring_feature[RING_F_FDIR].limit = 0; 6409 adapter->atr_sample_rate = 0; 6410 adapter->fdir_pballoc = 0; 6411#ifdef IXGBE_FCOE 6412 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6413 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6414#ifdef CONFIG_IXGBE_DCB 6415 adapter->fcoe.up = 0; 6416#endif /* IXGBE_DCB */ 6417#endif /* IXGBE_FCOE */ 6418 break; 6419 case ixgbe_mac_82599EB: 6420 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6421 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6422 break; 6423 case ixgbe_mac_X540: 6424 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6425 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6426 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6427 break; 6428 case ixgbe_mac_x550em_a: 6429 switch (hw->device_id) { 6430 case IXGBE_DEV_ID_X550EM_A_1G_T: 6431 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6432 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6433 break; 6434 default: 6435 break; 6436 } 6437 fallthrough; 6438 case ixgbe_mac_X550EM_x: 6439#ifdef CONFIG_IXGBE_DCB 6440 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6441#endif 6442#ifdef IXGBE_FCOE 6443 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6444#ifdef CONFIG_IXGBE_DCB 6445 adapter->fcoe.up = 0; 6446#endif /* IXGBE_DCB */ 6447#endif /* IXGBE_FCOE */ 6448 fallthrough; 6449 case ixgbe_mac_X550: 6450 if (hw->mac.type == ixgbe_mac_X550) 6451 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6452#ifdef CONFIG_IXGBE_DCA 6453 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6454#endif 6455 break; 6456 default: 6457 break; 6458 } 6459 6460#ifdef IXGBE_FCOE 6461 /* FCoE support exists, always init the FCoE lock */ 6462 spin_lock_init(&adapter->fcoe.lock); 6463 6464#endif 6465 /* n-tuple support exists, always init our spinlock */ 6466 spin_lock_init(&adapter->fdir_perfect_lock); 6467 6468 /* init spinlock to avoid concurrency of VF resources */ 6469 spin_lock_init(&adapter->vfs_lock); 6470 6471#ifdef CONFIG_IXGBE_DCB 6472 ixgbe_init_dcb(adapter); 6473#endif 6474 ixgbe_init_ipsec_offload(adapter); 6475 6476 /* default flow control settings */ 6477 hw->fc.requested_mode = ixgbe_fc_full; 6478 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 6479 ixgbe_pbthresh_setup(adapter); 6480 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 6481 hw->fc.send_xon = true; 6482 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 6483 6484#ifdef CONFIG_PCI_IOV 6485 if (max_vfs > 0) 6486 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 6487 6488 /* assign number of SR-IOV VFs */ 6489 if (hw->mac.type != ixgbe_mac_82598EB) { 6490 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 6491 max_vfs = 0; 6492 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 6493 } 6494 } 6495#endif /* CONFIG_PCI_IOV */ 6496 6497 /* enable itr by default in dynamic mode */ 6498 adapter->rx_itr_setting = 1; 6499 adapter->tx_itr_setting = 1; 6500 6501 /* set default ring sizes */ 6502 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 6503 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 6504 6505 /* set default work limits */ 6506 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 6507 6508 /* initialize eeprom parameters */ 6509 if (ixgbe_init_eeprom_params_generic(hw)) { 6510 e_dev_err("EEPROM initialization failed\n"); 6511 return -EIO; 6512 } 6513 6514 /* PF holds first pool slot */ 6515 set_bit(0, adapter->fwd_bitmask); 6516 set_bit(__IXGBE_DOWN, &adapter->state); 6517 6518 /* enable locking for XDP_TX if we have more CPUs than queues */ 6519 if (nr_cpu_ids > IXGBE_MAX_XDP_QS) 6520 static_branch_enable(&ixgbe_xdp_locking_key); 6521 6522 return 0; 6523} 6524 6525/** 6526 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 6527 * @tx_ring: tx descriptor ring (for a specific queue) to setup 6528 * 6529 * Return 0 on success, negative on failure 6530 **/ 6531int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 6532{ 6533 struct device *dev = tx_ring->dev; 6534 int orig_node = dev_to_node(dev); 6535 int ring_node = NUMA_NO_NODE; 6536 int size; 6537 6538 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 6539 6540 if (tx_ring->q_vector) 6541 ring_node = tx_ring->q_vector->numa_node; 6542 6543 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 6544 if (!tx_ring->tx_buffer_info) 6545 tx_ring->tx_buffer_info = vmalloc(size); 6546 if (!tx_ring->tx_buffer_info) 6547 goto err; 6548 6549 /* round up to nearest 4K */ 6550 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 6551 tx_ring->size = ALIGN(tx_ring->size, 4096); 6552 6553 set_dev_node(dev, ring_node); 6554 tx_ring->desc = dma_alloc_coherent(dev, 6555 tx_ring->size, 6556 &tx_ring->dma, 6557 GFP_KERNEL); 6558 set_dev_node(dev, orig_node); 6559 if (!tx_ring->desc) 6560 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 6561 &tx_ring->dma, GFP_KERNEL); 6562 if (!tx_ring->desc) 6563 goto err; 6564 6565 tx_ring->next_to_use = 0; 6566 tx_ring->next_to_clean = 0; 6567 return 0; 6568 6569err: 6570 vfree(tx_ring->tx_buffer_info); 6571 tx_ring->tx_buffer_info = NULL; 6572 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 6573 return -ENOMEM; 6574} 6575 6576/** 6577 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 6578 * @adapter: board private structure 6579 * 6580 * If this function returns with an error, then it's possible one or 6581 * more of the rings is populated (while the rest are not). It is the 6582 * callers duty to clean those orphaned rings. 6583 * 6584 * Return 0 on success, negative on failure 6585 **/ 6586static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 6587{ 6588 int i, j = 0, err = 0; 6589 6590 for (i = 0; i < adapter->num_tx_queues; i++) { 6591 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 6592 if (!err) 6593 continue; 6594 6595 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 6596 goto err_setup_tx; 6597 } 6598 for (j = 0; j < adapter->num_xdp_queues; j++) { 6599 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 6600 if (!err) 6601 continue; 6602 6603 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 6604 goto err_setup_tx; 6605 } 6606 6607 return 0; 6608err_setup_tx: 6609 /* rewind the index freeing the rings as we go */ 6610 while (j--) 6611 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 6612 while (i--) 6613 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6614 return err; 6615} 6616 6617static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring) 6618{ 6619 struct ixgbe_q_vector *q_vector = rx_ring->q_vector; 6620 6621 return q_vector ? q_vector->napi.napi_id : 0; 6622} 6623 6624/** 6625 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 6626 * @adapter: pointer to ixgbe_adapter 6627 * @rx_ring: rx descriptor ring (for a specific queue) to setup 6628 * 6629 * Returns 0 on success, negative on failure 6630 **/ 6631int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 6632 struct ixgbe_ring *rx_ring) 6633{ 6634 struct device *dev = rx_ring->dev; 6635 int orig_node = dev_to_node(dev); 6636 int ring_node = NUMA_NO_NODE; 6637 int size; 6638 6639 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 6640 6641 if (rx_ring->q_vector) 6642 ring_node = rx_ring->q_vector->numa_node; 6643 6644 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 6645 if (!rx_ring->rx_buffer_info) 6646 rx_ring->rx_buffer_info = vmalloc(size); 6647 if (!rx_ring->rx_buffer_info) 6648 goto err; 6649 6650 /* Round up to nearest 4K */ 6651 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 6652 rx_ring->size = ALIGN(rx_ring->size, 4096); 6653 6654 set_dev_node(dev, ring_node); 6655 rx_ring->desc = dma_alloc_coherent(dev, 6656 rx_ring->size, 6657 &rx_ring->dma, 6658 GFP_KERNEL); 6659 set_dev_node(dev, orig_node); 6660 if (!rx_ring->desc) 6661 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 6662 &rx_ring->dma, GFP_KERNEL); 6663 if (!rx_ring->desc) 6664 goto err; 6665 6666 rx_ring->next_to_clean = 0; 6667 rx_ring->next_to_use = 0; 6668 6669 /* XDP RX-queue info */ 6670 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 6671 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0) 6672 goto err; 6673 6674 WRITE_ONCE(rx_ring->xdp_prog, adapter->xdp_prog); 6675 6676 return 0; 6677err: 6678 vfree(rx_ring->rx_buffer_info); 6679 rx_ring->rx_buffer_info = NULL; 6680 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 6681 return -ENOMEM; 6682} 6683 6684/** 6685 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 6686 * @adapter: board private structure 6687 * 6688 * If this function returns with an error, then it's possible one or 6689 * more of the rings is populated (while the rest are not). It is the 6690 * callers duty to clean those orphaned rings. 6691 * 6692 * Return 0 on success, negative on failure 6693 **/ 6694static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 6695{ 6696 int i, err = 0; 6697 6698 for (i = 0; i < adapter->num_rx_queues; i++) { 6699 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 6700 if (!err) 6701 continue; 6702 6703 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 6704 goto err_setup_rx; 6705 } 6706 6707#ifdef IXGBE_FCOE 6708 err = ixgbe_setup_fcoe_ddp_resources(adapter); 6709 if (!err) 6710#endif 6711 return 0; 6712err_setup_rx: 6713 /* rewind the index freeing the rings as we go */ 6714 while (i--) 6715 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6716 return err; 6717} 6718 6719/** 6720 * ixgbe_free_tx_resources - Free Tx Resources per Queue 6721 * @tx_ring: Tx descriptor ring for a specific queue 6722 * 6723 * Free all transmit software resources 6724 **/ 6725void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 6726{ 6727 ixgbe_clean_tx_ring(tx_ring); 6728 6729 vfree(tx_ring->tx_buffer_info); 6730 tx_ring->tx_buffer_info = NULL; 6731 6732 /* if not set, then don't free */ 6733 if (!tx_ring->desc) 6734 return; 6735 6736 dma_free_coherent(tx_ring->dev, tx_ring->size, 6737 tx_ring->desc, tx_ring->dma); 6738 6739 tx_ring->desc = NULL; 6740} 6741 6742/** 6743 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 6744 * @adapter: board private structure 6745 * 6746 * Free all transmit software resources 6747 **/ 6748static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 6749{ 6750 int i; 6751 6752 for (i = 0; i < adapter->num_tx_queues; i++) 6753 if (adapter->tx_ring[i]->desc) 6754 ixgbe_free_tx_resources(adapter->tx_ring[i]); 6755 for (i = 0; i < adapter->num_xdp_queues; i++) 6756 if (adapter->xdp_ring[i]->desc) 6757 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 6758} 6759 6760/** 6761 * ixgbe_free_rx_resources - Free Rx Resources 6762 * @rx_ring: ring to clean the resources from 6763 * 6764 * Free all receive software resources 6765 **/ 6766void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 6767{ 6768 ixgbe_clean_rx_ring(rx_ring); 6769 6770 rx_ring->xdp_prog = NULL; 6771 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 6772 vfree(rx_ring->rx_buffer_info); 6773 rx_ring->rx_buffer_info = NULL; 6774 6775 /* if not set, then don't free */ 6776 if (!rx_ring->desc) 6777 return; 6778 6779 dma_free_coherent(rx_ring->dev, rx_ring->size, 6780 rx_ring->desc, rx_ring->dma); 6781 6782 rx_ring->desc = NULL; 6783} 6784 6785/** 6786 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 6787 * @adapter: board private structure 6788 * 6789 * Free all receive software resources 6790 **/ 6791static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 6792{ 6793 int i; 6794 6795#ifdef IXGBE_FCOE 6796 ixgbe_free_fcoe_ddp_resources(adapter); 6797 6798#endif 6799 for (i = 0; i < adapter->num_rx_queues; i++) 6800 if (adapter->rx_ring[i]->desc) 6801 ixgbe_free_rx_resources(adapter->rx_ring[i]); 6802} 6803 6804/** 6805 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP 6806 * @adapter: device handle, pointer to adapter 6807 */ 6808static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter) 6809{ 6810 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 6811 return IXGBE_RXBUFFER_2K; 6812 else 6813 return IXGBE_RXBUFFER_3K; 6814} 6815 6816/** 6817 * ixgbe_change_mtu - Change the Maximum Transfer Unit 6818 * @netdev: network interface device structure 6819 * @new_mtu: new value for maximum frame size 6820 * 6821 * Returns 0 on success, negative on failure 6822 **/ 6823static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 6824{ 6825 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6826 6827 if (ixgbe_enabled_xdp_adapter(adapter)) { 6828 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD; 6829 6830 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) { 6831 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 6832 return -EINVAL; 6833 } 6834 } 6835 6836 /* 6837 * For 82599EB we cannot allow legacy VFs to enable their receive 6838 * paths when MTU greater than 1500 is configured. So display a 6839 * warning that legacy VFs will be disabled. 6840 */ 6841 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 6842 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 6843 (new_mtu > ETH_DATA_LEN)) 6844 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 6845 6846 netdev_dbg(netdev, "changing MTU from %d to %d\n", 6847 netdev->mtu, new_mtu); 6848 6849 /* must set new MTU before calling down or up */ 6850 netdev->mtu = new_mtu; 6851 6852 if (netif_running(netdev)) 6853 ixgbe_reinit_locked(adapter); 6854 6855 return 0; 6856} 6857 6858/** 6859 * ixgbe_open - Called when a network interface is made active 6860 * @netdev: network interface device structure 6861 * 6862 * Returns 0 on success, negative value on failure 6863 * 6864 * The open entry point is called when a network interface is made 6865 * active by the system (IFF_UP). At this point all resources needed 6866 * for transmit and receive operations are allocated, the interrupt 6867 * handler is registered with the OS, the watchdog timer is started, 6868 * and the stack is notified that the interface is ready. 6869 **/ 6870int ixgbe_open(struct net_device *netdev) 6871{ 6872 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6873 struct ixgbe_hw *hw = &adapter->hw; 6874 int err, queues; 6875 6876 /* disallow open during test */ 6877 if (test_bit(__IXGBE_TESTING, &adapter->state)) 6878 return -EBUSY; 6879 6880 netif_carrier_off(netdev); 6881 6882 /* allocate transmit descriptors */ 6883 err = ixgbe_setup_all_tx_resources(adapter); 6884 if (err) 6885 goto err_setup_tx; 6886 6887 /* allocate receive descriptors */ 6888 err = ixgbe_setup_all_rx_resources(adapter); 6889 if (err) 6890 goto err_setup_rx; 6891 6892 ixgbe_configure(adapter); 6893 6894 err = ixgbe_request_irq(adapter); 6895 if (err) 6896 goto err_req_irq; 6897 6898 /* Notify the stack of the actual queue counts. */ 6899 queues = adapter->num_tx_queues; 6900 err = netif_set_real_num_tx_queues(netdev, queues); 6901 if (err) 6902 goto err_set_queues; 6903 6904 queues = adapter->num_rx_queues; 6905 err = netif_set_real_num_rx_queues(netdev, queues); 6906 if (err) 6907 goto err_set_queues; 6908 6909 ixgbe_ptp_init(adapter); 6910 6911 ixgbe_up_complete(adapter); 6912 6913 udp_tunnel_nic_reset_ntf(netdev); 6914 6915 return 0; 6916 6917err_set_queues: 6918 ixgbe_free_irq(adapter); 6919err_req_irq: 6920 ixgbe_free_all_rx_resources(adapter); 6921 if (hw->phy.ops.set_phy_power && !adapter->wol) 6922 hw->phy.ops.set_phy_power(&adapter->hw, false); 6923err_setup_rx: 6924 ixgbe_free_all_tx_resources(adapter); 6925err_setup_tx: 6926 ixgbe_reset(adapter); 6927 6928 return err; 6929} 6930 6931static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 6932{ 6933 ixgbe_ptp_suspend(adapter); 6934 6935 if (adapter->hw.phy.ops.enter_lplu) { 6936 adapter->hw.phy.reset_disable = true; 6937 ixgbe_down(adapter); 6938 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 6939 adapter->hw.phy.reset_disable = false; 6940 } else { 6941 ixgbe_down(adapter); 6942 } 6943 6944 ixgbe_free_irq(adapter); 6945 6946 ixgbe_free_all_tx_resources(adapter); 6947 ixgbe_free_all_rx_resources(adapter); 6948} 6949 6950/** 6951 * ixgbe_close - Disables a network interface 6952 * @netdev: network interface device structure 6953 * 6954 * Returns 0, this is not allowed to fail 6955 * 6956 * The close entry point is called when an interface is de-activated 6957 * by the OS. The hardware is still under the drivers control, but 6958 * needs to be disabled. A global MAC reset is issued to stop the 6959 * hardware, and all transmit and receive resources are freed. 6960 **/ 6961int ixgbe_close(struct net_device *netdev) 6962{ 6963 struct ixgbe_adapter *adapter = netdev_priv(netdev); 6964 6965 ixgbe_ptp_stop(adapter); 6966 6967 if (netif_device_present(netdev)) 6968 ixgbe_close_suspend(adapter); 6969 6970 ixgbe_fdir_filter_exit(adapter); 6971 6972 ixgbe_release_hw_control(adapter); 6973 6974 return 0; 6975} 6976 6977static int __maybe_unused ixgbe_resume(struct device *dev_d) 6978{ 6979 struct pci_dev *pdev = to_pci_dev(dev_d); 6980 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 6981 struct net_device *netdev = adapter->netdev; 6982 u32 err; 6983 6984 adapter->hw.hw_addr = adapter->io_addr; 6985 6986 err = pci_enable_device_mem(pdev); 6987 if (err) { 6988 e_dev_err("Cannot enable PCI device from suspend\n"); 6989 return err; 6990 } 6991 smp_mb__before_atomic(); 6992 clear_bit(__IXGBE_DISABLED, &adapter->state); 6993 pci_set_master(pdev); 6994 6995 device_wakeup_disable(dev_d); 6996 6997 ixgbe_reset(adapter); 6998 6999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 7000 7001 rtnl_lock(); 7002 err = ixgbe_init_interrupt_scheme(adapter); 7003 if (!err && netif_running(netdev)) 7004 err = ixgbe_open(netdev); 7005 7006 7007 if (!err) 7008 netif_device_attach(netdev); 7009 rtnl_unlock(); 7010 7011 return err; 7012} 7013 7014static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 7015{ 7016 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7017 struct net_device *netdev = adapter->netdev; 7018 struct ixgbe_hw *hw = &adapter->hw; 7019 u32 ctrl; 7020 u32 wufc = adapter->wol; 7021 7022 rtnl_lock(); 7023 netif_device_detach(netdev); 7024 7025 if (netif_running(netdev)) 7026 ixgbe_close_suspend(adapter); 7027 7028 ixgbe_clear_interrupt_scheme(adapter); 7029 rtnl_unlock(); 7030 7031 if (hw->mac.ops.stop_link_on_d3) 7032 hw->mac.ops.stop_link_on_d3(hw); 7033 7034 if (wufc) { 7035 u32 fctrl; 7036 7037 ixgbe_set_rx_mode(netdev); 7038 7039 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 7040 if (hw->mac.ops.enable_tx_laser) 7041 hw->mac.ops.enable_tx_laser(hw); 7042 7043 /* enable the reception of multicast packets */ 7044 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7045 fctrl |= IXGBE_FCTRL_MPE; 7046 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 7047 7048 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 7049 ctrl |= IXGBE_CTRL_GIO_DIS; 7050 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 7051 7052 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 7053 } else { 7054 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 7055 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 7056 } 7057 7058 switch (hw->mac.type) { 7059 case ixgbe_mac_82598EB: 7060 pci_wake_from_d3(pdev, false); 7061 break; 7062 case ixgbe_mac_82599EB: 7063 case ixgbe_mac_X540: 7064 case ixgbe_mac_X550: 7065 case ixgbe_mac_X550EM_x: 7066 case ixgbe_mac_x550em_a: 7067 pci_wake_from_d3(pdev, !!wufc); 7068 break; 7069 default: 7070 break; 7071 } 7072 7073 *enable_wake = !!wufc; 7074 if (hw->phy.ops.set_phy_power && !*enable_wake) 7075 hw->phy.ops.set_phy_power(hw, false); 7076 7077 ixgbe_release_hw_control(adapter); 7078 7079 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 7080 pci_disable_device(pdev); 7081 7082 return 0; 7083} 7084 7085static int __maybe_unused ixgbe_suspend(struct device *dev_d) 7086{ 7087 struct pci_dev *pdev = to_pci_dev(dev_d); 7088 int retval; 7089 bool wake; 7090 7091 retval = __ixgbe_shutdown(pdev, &wake); 7092 7093 device_set_wakeup_enable(dev_d, wake); 7094 7095 return retval; 7096} 7097 7098static void ixgbe_shutdown(struct pci_dev *pdev) 7099{ 7100 bool wake; 7101 7102 __ixgbe_shutdown(pdev, &wake); 7103 7104 if (system_state == SYSTEM_POWER_OFF) { 7105 pci_wake_from_d3(pdev, wake); 7106 pci_set_power_state(pdev, PCI_D3hot); 7107 } 7108} 7109 7110/** 7111 * ixgbe_update_stats - Update the board statistics counters. 7112 * @adapter: board private structure 7113 **/ 7114void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7115{ 7116 struct net_device *netdev = adapter->netdev; 7117 struct ixgbe_hw *hw = &adapter->hw; 7118 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7119 u64 total_mpc = 0; 7120 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7121 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7122 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7123 u64 alloc_rx_page = 0; 7124 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7125 7126 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7127 test_bit(__IXGBE_RESETTING, &adapter->state)) 7128 return; 7129 7130 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7131 u64 rsc_count = 0; 7132 u64 rsc_flush = 0; 7133 for (i = 0; i < adapter->num_rx_queues; i++) { 7134 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7135 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7136 } 7137 adapter->rsc_total_count = rsc_count; 7138 adapter->rsc_total_flush = rsc_flush; 7139 } 7140 7141 for (i = 0; i < adapter->num_rx_queues; i++) { 7142 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7143 7144 if (!rx_ring) 7145 continue; 7146 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7147 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7148 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7149 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7150 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7151 bytes += rx_ring->stats.bytes; 7152 packets += rx_ring->stats.packets; 7153 } 7154 adapter->non_eop_descs = non_eop_descs; 7155 adapter->alloc_rx_page = alloc_rx_page; 7156 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7157 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7158 adapter->hw_csum_rx_error = hw_csum_rx_error; 7159 netdev->stats.rx_bytes = bytes; 7160 netdev->stats.rx_packets = packets; 7161 7162 bytes = 0; 7163 packets = 0; 7164 /* gather some stats to the adapter struct that are per queue */ 7165 for (i = 0; i < adapter->num_tx_queues; i++) { 7166 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7167 7168 if (!tx_ring) 7169 continue; 7170 restart_queue += tx_ring->tx_stats.restart_queue; 7171 tx_busy += tx_ring->tx_stats.tx_busy; 7172 bytes += tx_ring->stats.bytes; 7173 packets += tx_ring->stats.packets; 7174 } 7175 for (i = 0; i < adapter->num_xdp_queues; i++) { 7176 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7177 7178 if (!xdp_ring) 7179 continue; 7180 restart_queue += xdp_ring->tx_stats.restart_queue; 7181 tx_busy += xdp_ring->tx_stats.tx_busy; 7182 bytes += xdp_ring->stats.bytes; 7183 packets += xdp_ring->stats.packets; 7184 } 7185 adapter->restart_queue = restart_queue; 7186 adapter->tx_busy = tx_busy; 7187 netdev->stats.tx_bytes = bytes; 7188 netdev->stats.tx_packets = packets; 7189 7190 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7191 7192 /* 8 register reads */ 7193 for (i = 0; i < 8; i++) { 7194 /* for packet buffers not used, the register should read 0 */ 7195 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7196 missed_rx += mpc; 7197 hwstats->mpc[i] += mpc; 7198 total_mpc += hwstats->mpc[i]; 7199 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7200 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7201 switch (hw->mac.type) { 7202 case ixgbe_mac_82598EB: 7203 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7204 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7205 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7206 hwstats->pxonrxc[i] += 7207 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7208 break; 7209 case ixgbe_mac_82599EB: 7210 case ixgbe_mac_X540: 7211 case ixgbe_mac_X550: 7212 case ixgbe_mac_X550EM_x: 7213 case ixgbe_mac_x550em_a: 7214 hwstats->pxonrxc[i] += 7215 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7216 break; 7217 default: 7218 break; 7219 } 7220 } 7221 7222 /*16 register reads */ 7223 for (i = 0; i < 16; i++) { 7224 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7225 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7226 if ((hw->mac.type == ixgbe_mac_82599EB) || 7227 (hw->mac.type == ixgbe_mac_X540) || 7228 (hw->mac.type == ixgbe_mac_X550) || 7229 (hw->mac.type == ixgbe_mac_X550EM_x) || 7230 (hw->mac.type == ixgbe_mac_x550em_a)) { 7231 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7232 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7233 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7234 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7235 } 7236 } 7237 7238 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7239 /* work around hardware counting issue */ 7240 hwstats->gprc -= missed_rx; 7241 7242 ixgbe_update_xoff_received(adapter); 7243 7244 /* 82598 hardware only has a 32 bit counter in the high register */ 7245 switch (hw->mac.type) { 7246 case ixgbe_mac_82598EB: 7247 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7248 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7249 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7250 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7251 break; 7252 case ixgbe_mac_X540: 7253 case ixgbe_mac_X550: 7254 case ixgbe_mac_X550EM_x: 7255 case ixgbe_mac_x550em_a: 7256 /* OS2BMC stats are X540 and later */ 7257 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7258 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7259 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7260 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7261 fallthrough; 7262 case ixgbe_mac_82599EB: 7263 for (i = 0; i < 16; i++) 7264 adapter->hw_rx_no_dma_resources += 7265 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7266 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7267 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7268 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7269 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7270 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7271 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7272 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7273 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7274 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7275#ifdef IXGBE_FCOE 7276 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7277 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7278 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7279 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7280 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7281 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7282 /* Add up per cpu counters for total ddp aloc fail */ 7283 if (adapter->fcoe.ddp_pool) { 7284 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7285 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7286 unsigned int cpu; 7287 u64 noddp = 0, noddp_ext_buff = 0; 7288 for_each_possible_cpu(cpu) { 7289 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7290 noddp += ddp_pool->noddp; 7291 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7292 } 7293 hwstats->fcoe_noddp = noddp; 7294 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7295 } 7296#endif /* IXGBE_FCOE */ 7297 break; 7298 default: 7299 break; 7300 } 7301 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7302 hwstats->bprc += bprc; 7303 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7304 if (hw->mac.type == ixgbe_mac_82598EB) 7305 hwstats->mprc -= bprc; 7306 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7307 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7308 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7309 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7310 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7311 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7312 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7313 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7314 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7315 hwstats->lxontxc += lxon; 7316 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7317 hwstats->lxofftxc += lxoff; 7318 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7319 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7320 /* 7321 * 82598 errata - tx of flow control packets is included in tx counters 7322 */ 7323 xon_off_tot = lxon + lxoff; 7324 hwstats->gptc -= xon_off_tot; 7325 hwstats->mptc -= xon_off_tot; 7326 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7327 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7328 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7329 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7330 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7331 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7332 hwstats->ptc64 -= xon_off_tot; 7333 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7334 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7335 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7336 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7337 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7338 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7339 7340 /* Fill out the OS statistics structure */ 7341 netdev->stats.multicast = hwstats->mprc; 7342 7343 /* Rx Errors */ 7344 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7345 netdev->stats.rx_dropped = 0; 7346 netdev->stats.rx_length_errors = hwstats->rlec; 7347 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7348 netdev->stats.rx_missed_errors = total_mpc; 7349 7350 /* VF Stats Collection - skip while resetting because these 7351 * are not clear on read and otherwise you'll sometimes get 7352 * crazy values. 7353 */ 7354 if (!test_bit(__IXGBE_RESETTING, &adapter->state)) { 7355 for (i = 0; i < adapter->num_vfs; i++) { 7356 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i), 7357 adapter->vfinfo[i].last_vfstats.gprc, 7358 adapter->vfinfo[i].vfstats.gprc); 7359 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i), 7360 adapter->vfinfo[i].last_vfstats.gptc, 7361 adapter->vfinfo[i].vfstats.gptc); 7362 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i), 7363 IXGBE_PVFGORC_MSB(i), 7364 adapter->vfinfo[i].last_vfstats.gorc, 7365 adapter->vfinfo[i].vfstats.gorc); 7366 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i), 7367 IXGBE_PVFGOTC_MSB(i), 7368 adapter->vfinfo[i].last_vfstats.gotc, 7369 adapter->vfinfo[i].vfstats.gotc); 7370 UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i), 7371 adapter->vfinfo[i].last_vfstats.mprc, 7372 adapter->vfinfo[i].vfstats.mprc); 7373 } 7374 } 7375} 7376 7377/** 7378 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7379 * @adapter: pointer to the device adapter structure 7380 **/ 7381static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7382{ 7383 struct ixgbe_hw *hw = &adapter->hw; 7384 int i; 7385 7386 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7387 return; 7388 7389 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7390 7391 /* if interface is down do nothing */ 7392 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7393 return; 7394 7395 /* do nothing if we are not using signature filters */ 7396 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7397 return; 7398 7399 adapter->fdir_overflow++; 7400 7401 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7402 for (i = 0; i < adapter->num_tx_queues; i++) 7403 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7404 &(adapter->tx_ring[i]->state)); 7405 for (i = 0; i < adapter->num_xdp_queues; i++) 7406 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7407 &adapter->xdp_ring[i]->state); 7408 /* re-enable flow director interrupts */ 7409 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7410 } else { 7411 e_err(probe, "failed to finish FDIR re-initialization, " 7412 "ignored adding FDIR ATR filters\n"); 7413 } 7414} 7415 7416/** 7417 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7418 * @adapter: pointer to the device adapter structure 7419 * 7420 * This function serves two purposes. First it strobes the interrupt lines 7421 * in order to make certain interrupts are occurring. Secondly it sets the 7422 * bits needed to check for TX hangs. As a result we should immediately 7423 * determine if a hang has occurred. 7424 */ 7425static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7426{ 7427 struct ixgbe_hw *hw = &adapter->hw; 7428 u64 eics = 0; 7429 int i; 7430 7431 /* If we're down, removing or resetting, just bail */ 7432 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7433 test_bit(__IXGBE_REMOVING, &adapter->state) || 7434 test_bit(__IXGBE_RESETTING, &adapter->state)) 7435 return; 7436 7437 /* Force detection of hung controller */ 7438 if (netif_carrier_ok(adapter->netdev)) { 7439 for (i = 0; i < adapter->num_tx_queues; i++) 7440 set_check_for_tx_hang(adapter->tx_ring[i]); 7441 for (i = 0; i < adapter->num_xdp_queues; i++) 7442 set_check_for_tx_hang(adapter->xdp_ring[i]); 7443 } 7444 7445 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 7446 /* 7447 * for legacy and MSI interrupts don't set any bits 7448 * that are enabled for EIAM, because this operation 7449 * would set *both* EIMS and EICS for any bit in EIAM 7450 */ 7451 IXGBE_WRITE_REG(hw, IXGBE_EICS, 7452 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 7453 } else { 7454 /* get one bit for every active tx/rx interrupt vector */ 7455 for (i = 0; i < adapter->num_q_vectors; i++) { 7456 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 7457 if (qv->rx.ring || qv->tx.ring) 7458 eics |= BIT_ULL(i); 7459 } 7460 } 7461 7462 /* Cause software interrupt to ensure rings are cleaned */ 7463 ixgbe_irq_rearm_queues(adapter, eics); 7464} 7465 7466/** 7467 * ixgbe_watchdog_update_link - update the link status 7468 * @adapter: pointer to the device adapter structure 7469 **/ 7470static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 7471{ 7472 struct ixgbe_hw *hw = &adapter->hw; 7473 u32 link_speed = adapter->link_speed; 7474 bool link_up = adapter->link_up; 7475 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 7476 7477 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 7478 return; 7479 7480 if (hw->mac.ops.check_link) { 7481 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 7482 } else { 7483 /* always assume link is up, if no check link function */ 7484 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 7485 link_up = true; 7486 } 7487 7488 if (adapter->ixgbe_ieee_pfc) 7489 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 7490 7491 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 7492 hw->mac.ops.fc_enable(hw); 7493 ixgbe_set_rx_drop_en(adapter); 7494 } 7495 7496 if (link_up || 7497 time_after(jiffies, (adapter->link_check_timeout + 7498 IXGBE_TRY_LINK_TIMEOUT))) { 7499 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 7500 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 7501 IXGBE_WRITE_FLUSH(hw); 7502 } 7503 7504 adapter->link_up = link_up; 7505 adapter->link_speed = link_speed; 7506} 7507 7508static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 7509{ 7510#ifdef CONFIG_IXGBE_DCB 7511 struct net_device *netdev = adapter->netdev; 7512 struct dcb_app app = { 7513 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 7514 .protocol = 0, 7515 }; 7516 u8 up = 0; 7517 7518 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 7519 up = dcb_ieee_getapp_mask(netdev, &app); 7520 7521 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 7522#endif 7523} 7524 7525/** 7526 * ixgbe_watchdog_link_is_up - update netif_carrier status and 7527 * print link up message 7528 * @adapter: pointer to the device adapter structure 7529 **/ 7530static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 7531{ 7532 struct net_device *netdev = adapter->netdev; 7533 struct ixgbe_hw *hw = &adapter->hw; 7534 u32 link_speed = adapter->link_speed; 7535 const char *speed_str; 7536 bool flow_rx, flow_tx; 7537 7538 /* only continue if link was previously down */ 7539 if (netif_carrier_ok(netdev)) 7540 return; 7541 7542 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 7543 7544 switch (hw->mac.type) { 7545 case ixgbe_mac_82598EB: { 7546 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7547 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 7548 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 7549 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 7550 } 7551 break; 7552 case ixgbe_mac_X540: 7553 case ixgbe_mac_X550: 7554 case ixgbe_mac_X550EM_x: 7555 case ixgbe_mac_x550em_a: 7556 case ixgbe_mac_82599EB: { 7557 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 7558 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 7559 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 7560 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 7561 } 7562 break; 7563 default: 7564 flow_tx = false; 7565 flow_rx = false; 7566 break; 7567 } 7568 7569 adapter->last_rx_ptp_check = jiffies; 7570 7571 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7572 ixgbe_ptp_start_cyclecounter(adapter); 7573 7574 switch (link_speed) { 7575 case IXGBE_LINK_SPEED_10GB_FULL: 7576 speed_str = "10 Gbps"; 7577 break; 7578 case IXGBE_LINK_SPEED_5GB_FULL: 7579 speed_str = "5 Gbps"; 7580 break; 7581 case IXGBE_LINK_SPEED_2_5GB_FULL: 7582 speed_str = "2.5 Gbps"; 7583 break; 7584 case IXGBE_LINK_SPEED_1GB_FULL: 7585 speed_str = "1 Gbps"; 7586 break; 7587 case IXGBE_LINK_SPEED_100_FULL: 7588 speed_str = "100 Mbps"; 7589 break; 7590 case IXGBE_LINK_SPEED_10_FULL: 7591 speed_str = "10 Mbps"; 7592 break; 7593 default: 7594 speed_str = "unknown speed"; 7595 break; 7596 } 7597 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, 7598 ((flow_rx && flow_tx) ? "RX/TX" : 7599 (flow_rx ? "RX" : 7600 (flow_tx ? "TX" : "None")))); 7601 7602 netif_carrier_on(netdev); 7603 ixgbe_check_vf_rate_limit(adapter); 7604 7605 /* enable transmits */ 7606 netif_tx_wake_all_queues(adapter->netdev); 7607 7608 /* update the default user priority for VFs */ 7609 ixgbe_update_default_up(adapter); 7610 7611 /* ping all the active vfs to let them know link has changed */ 7612 ixgbe_ping_all_vfs(adapter); 7613} 7614 7615/** 7616 * ixgbe_watchdog_link_is_down - update netif_carrier status and 7617 * print link down message 7618 * @adapter: pointer to the adapter structure 7619 **/ 7620static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 7621{ 7622 struct net_device *netdev = adapter->netdev; 7623 struct ixgbe_hw *hw = &adapter->hw; 7624 7625 adapter->link_up = false; 7626 adapter->link_speed = 0; 7627 7628 /* only continue if link was up previously */ 7629 if (!netif_carrier_ok(netdev)) 7630 return; 7631 7632 /* poll for SFP+ cable when link is down */ 7633 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 7634 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 7635 7636 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 7637 ixgbe_ptp_start_cyclecounter(adapter); 7638 7639 e_info(drv, "NIC Link is Down\n"); 7640 netif_carrier_off(netdev); 7641 7642 /* ping all the active vfs to let them know link has changed */ 7643 ixgbe_ping_all_vfs(adapter); 7644} 7645 7646static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 7647{ 7648 int i; 7649 7650 for (i = 0; i < adapter->num_tx_queues; i++) { 7651 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 7652 7653 if (tx_ring->next_to_use != tx_ring->next_to_clean) 7654 return true; 7655 } 7656 7657 for (i = 0; i < adapter->num_xdp_queues; i++) { 7658 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 7659 7660 if (ring->next_to_use != ring->next_to_clean) 7661 return true; 7662 } 7663 7664 return false; 7665} 7666 7667static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 7668{ 7669 struct ixgbe_hw *hw = &adapter->hw; 7670 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 7671 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 7672 7673 int i, j; 7674 7675 if (!adapter->num_vfs) 7676 return false; 7677 7678 /* resetting the PF is only needed for MAC before X550 */ 7679 if (hw->mac.type >= ixgbe_mac_X550) 7680 return false; 7681 7682 for (i = 0; i < adapter->num_vfs; i++) { 7683 for (j = 0; j < q_per_pool; j++) { 7684 u32 h, t; 7685 7686 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 7687 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 7688 7689 if (h != t) 7690 return true; 7691 } 7692 } 7693 7694 return false; 7695} 7696 7697/** 7698 * ixgbe_watchdog_flush_tx - flush queues on link down 7699 * @adapter: pointer to the device adapter structure 7700 **/ 7701static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 7702{ 7703 if (!netif_carrier_ok(adapter->netdev)) { 7704 if (ixgbe_ring_tx_pending(adapter) || 7705 ixgbe_vf_tx_pending(adapter)) { 7706 /* We've lost link, so the controller stops DMA, 7707 * but we've got queued Tx work that's never going 7708 * to get done, so reset controller to flush Tx. 7709 * (Do the reset outside of interrupt context). 7710 */ 7711 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 7712 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 7713 } 7714 } 7715} 7716 7717#ifdef CONFIG_PCI_IOV 7718static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf) 7719{ 7720 struct ixgbe_hw *hw = &adapter->hw; 7721 7722 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 7723 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) { 7724 adapter->vfinfo[vf].primary_abort_count++; 7725 if (adapter->vfinfo[vf].primary_abort_count == 7726 IXGBE_PRIMARY_ABORT_LIMIT) { 7727 ixgbe_set_vf_link_state(adapter, vf, 7728 IFLA_VF_LINK_STATE_DISABLE); 7729 adapter->vfinfo[vf].primary_abort_count = 0; 7730 7731 e_info(drv, 7732 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on", 7733 hw->bus.func, vf, 7734 adapter->vfinfo[vf].vf_mac_addresses); 7735 } 7736 } 7737} 7738 7739static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 7740{ 7741 struct ixgbe_hw *hw = &adapter->hw; 7742 struct pci_dev *pdev = adapter->pdev; 7743 unsigned int vf; 7744 u32 gpc; 7745 7746 if (!(netif_carrier_ok(adapter->netdev))) 7747 return; 7748 7749 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 7750 if (gpc) /* If incrementing then no need for the check below */ 7751 return; 7752 /* Check to see if a bad DMA write target from an errant or 7753 * malicious VF has caused a PCIe error. If so then we can 7754 * issue a VFLR to the offending VF(s) and then resume without 7755 * requesting a full slot reset. 7756 */ 7757 7758 if (!pdev) 7759 return; 7760 7761 /* check status reg for all VFs owned by this PF */ 7762 for (vf = 0; vf < adapter->num_vfs; ++vf) { 7763 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 7764 u16 status_reg; 7765 7766 if (!vfdev) 7767 continue; 7768 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 7769 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 7770 status_reg & PCI_STATUS_REC_MASTER_ABORT) { 7771 ixgbe_bad_vf_abort(adapter, vf); 7772 pcie_flr(vfdev); 7773 } 7774 } 7775} 7776 7777static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 7778{ 7779 u32 ssvpc; 7780 7781 /* Do not perform spoof check for 82598 or if not in IOV mode */ 7782 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 7783 adapter->num_vfs == 0) 7784 return; 7785 7786 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 7787 7788 /* 7789 * ssvpc register is cleared on read, if zero then no 7790 * spoofed packets in the last interval. 7791 */ 7792 if (!ssvpc) 7793 return; 7794 7795 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 7796} 7797#else 7798static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 7799{ 7800} 7801 7802static void 7803ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 7804{ 7805} 7806#endif /* CONFIG_PCI_IOV */ 7807 7808 7809/** 7810 * ixgbe_watchdog_subtask - check and bring link up 7811 * @adapter: pointer to the device adapter structure 7812 **/ 7813static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 7814{ 7815 /* if interface is down, removing or resetting, do nothing */ 7816 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7817 test_bit(__IXGBE_REMOVING, &adapter->state) || 7818 test_bit(__IXGBE_RESETTING, &adapter->state)) 7819 return; 7820 7821 ixgbe_watchdog_update_link(adapter); 7822 7823 if (adapter->link_up) 7824 ixgbe_watchdog_link_is_up(adapter); 7825 else 7826 ixgbe_watchdog_link_is_down(adapter); 7827 7828 ixgbe_check_for_bad_vf(adapter); 7829 ixgbe_spoof_check(adapter); 7830 ixgbe_update_stats(adapter); 7831 7832 ixgbe_watchdog_flush_tx(adapter); 7833} 7834 7835/** 7836 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 7837 * @adapter: the ixgbe adapter structure 7838 **/ 7839static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 7840{ 7841 struct ixgbe_hw *hw = &adapter->hw; 7842 int err; 7843 7844 /* not searching for SFP so there is nothing to do here */ 7845 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 7846 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7847 return; 7848 7849 if (adapter->sfp_poll_time && 7850 time_after(adapter->sfp_poll_time, jiffies)) 7851 return; /* If not yet time to poll for SFP */ 7852 7853 /* someone else is in init, wait until next service event */ 7854 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7855 return; 7856 7857 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 7858 7859 err = hw->phy.ops.identify_sfp(hw); 7860 if (err == -EOPNOTSUPP) 7861 goto sfp_out; 7862 7863 if (err == -ENOENT) { 7864 /* If no cable is present, then we need to reset 7865 * the next time we find a good cable. */ 7866 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 7867 } 7868 7869 /* exit on error */ 7870 if (err) 7871 goto sfp_out; 7872 7873 /* exit if reset not needed */ 7874 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 7875 goto sfp_out; 7876 7877 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 7878 7879 /* 7880 * A module may be identified correctly, but the EEPROM may not have 7881 * support for that module. setup_sfp() will fail in that case, so 7882 * we should not allow that module to load. 7883 */ 7884 if (hw->mac.type == ixgbe_mac_82598EB) 7885 err = hw->phy.ops.reset(hw); 7886 else 7887 err = hw->mac.ops.setup_sfp(hw); 7888 7889 if (err == -EOPNOTSUPP) 7890 goto sfp_out; 7891 7892 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 7893 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 7894 7895sfp_out: 7896 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7897 7898 if (err == -EOPNOTSUPP && 7899 adapter->netdev->reg_state == NETREG_REGISTERED) { 7900 e_dev_err("failed to initialize because an unsupported " 7901 "SFP+ module type was detected.\n"); 7902 e_dev_err("Reload the driver after installing a " 7903 "supported module.\n"); 7904 unregister_netdev(adapter->netdev); 7905 } 7906} 7907 7908/** 7909 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 7910 * @adapter: the ixgbe adapter structure 7911 **/ 7912static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 7913{ 7914 struct ixgbe_hw *hw = &adapter->hw; 7915 u32 cap_speed; 7916 u32 speed; 7917 bool autoneg = false; 7918 7919 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 7920 return; 7921 7922 /* someone else is in init, wait until next service event */ 7923 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 7924 return; 7925 7926 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 7927 7928 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 7929 7930 /* advertise highest capable link speed */ 7931 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 7932 speed = IXGBE_LINK_SPEED_10GB_FULL; 7933 else 7934 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 7935 IXGBE_LINK_SPEED_1GB_FULL); 7936 7937 if (hw->mac.ops.setup_link) 7938 hw->mac.ops.setup_link(hw, speed, true); 7939 7940 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 7941 adapter->link_check_timeout = jiffies; 7942 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 7943} 7944 7945/** 7946 * ixgbe_service_timer - Timer Call-back 7947 * @t: pointer to timer_list structure 7948 **/ 7949static void ixgbe_service_timer(struct timer_list *t) 7950{ 7951 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer); 7952 unsigned long next_event_offset; 7953 7954 /* poll faster when waiting for link */ 7955 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 7956 next_event_offset = HZ / 10; 7957 else 7958 next_event_offset = HZ * 2; 7959 7960 /* Reset the timer */ 7961 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 7962 7963 ixgbe_service_event_schedule(adapter); 7964} 7965 7966static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 7967{ 7968 struct ixgbe_hw *hw = &adapter->hw; 7969 bool overtemp; 7970 7971 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 7972 return; 7973 7974 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 7975 7976 if (!hw->phy.ops.handle_lasi) 7977 return; 7978 7979 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp); 7980 if (overtemp) 7981 e_crit(drv, "%s\n", ixgbe_overheat_msg); 7982} 7983 7984static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 7985{ 7986 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 7987 return; 7988 7989 rtnl_lock(); 7990 /* If we're already down, removing or resetting, just bail */ 7991 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7992 test_bit(__IXGBE_REMOVING, &adapter->state) || 7993 test_bit(__IXGBE_RESETTING, &adapter->state)) { 7994 rtnl_unlock(); 7995 return; 7996 } 7997 7998 ixgbe_dump(adapter); 7999 netdev_err(adapter->netdev, "Reset adapter\n"); 8000 adapter->tx_timeout_count++; 8001 8002 ixgbe_reinit_locked(adapter); 8003 rtnl_unlock(); 8004} 8005 8006/** 8007 * ixgbe_check_fw_error - Check firmware for errors 8008 * @adapter: the adapter private structure 8009 * 8010 * Check firmware errors in register FWSM 8011 */ 8012static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 8013{ 8014 struct ixgbe_hw *hw = &adapter->hw; 8015 u32 fwsm; 8016 8017 /* read fwsm.ext_err_ind register and log errors */ 8018 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 8019 8020 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 8021 !(fwsm & IXGBE_FWSM_FW_VAL_BIT)) 8022 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 8023 fwsm); 8024 8025 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 8026 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 8027 return true; 8028 } 8029 8030 return false; 8031} 8032 8033/** 8034 * ixgbe_service_task - manages and runs subtasks 8035 * @work: pointer to work_struct containing our data 8036 **/ 8037static void ixgbe_service_task(struct work_struct *work) 8038{ 8039 struct ixgbe_adapter *adapter = container_of(work, 8040 struct ixgbe_adapter, 8041 service_task); 8042 if (ixgbe_removed(adapter->hw.hw_addr)) { 8043 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 8044 rtnl_lock(); 8045 ixgbe_down(adapter); 8046 rtnl_unlock(); 8047 } 8048 ixgbe_service_event_complete(adapter); 8049 return; 8050 } 8051 if (ixgbe_check_fw_error(adapter)) { 8052 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 8053 unregister_netdev(adapter->netdev); 8054 ixgbe_service_event_complete(adapter); 8055 return; 8056 } 8057 ixgbe_reset_subtask(adapter); 8058 ixgbe_phy_interrupt_subtask(adapter); 8059 ixgbe_sfp_detection_subtask(adapter); 8060 ixgbe_sfp_link_config_subtask(adapter); 8061 ixgbe_check_overtemp_subtask(adapter); 8062 ixgbe_watchdog_subtask(adapter); 8063 ixgbe_fdir_reinit_subtask(adapter); 8064 ixgbe_check_hang_subtask(adapter); 8065 8066 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 8067 ixgbe_ptp_overflow_check(adapter); 8068 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 8069 ixgbe_ptp_rx_hang(adapter); 8070 ixgbe_ptp_tx_hang(adapter); 8071 } 8072 8073 ixgbe_service_event_complete(adapter); 8074} 8075 8076static int ixgbe_tso(struct ixgbe_ring *tx_ring, 8077 struct ixgbe_tx_buffer *first, 8078 u8 *hdr_len, 8079 struct ixgbe_ipsec_tx_data *itd) 8080{ 8081 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 8082 struct sk_buff *skb = first->skb; 8083 union { 8084 struct iphdr *v4; 8085 struct ipv6hdr *v6; 8086 unsigned char *hdr; 8087 } ip; 8088 union { 8089 struct tcphdr *tcp; 8090 struct udphdr *udp; 8091 unsigned char *hdr; 8092 } l4; 8093 u32 paylen, l4_offset; 8094 u32 fceof_saidx = 0; 8095 int err; 8096 8097 if (skb->ip_summed != CHECKSUM_PARTIAL) 8098 return 0; 8099 8100 if (!skb_is_gso(skb)) 8101 return 0; 8102 8103 err = skb_cow_head(skb, 0); 8104 if (err < 0) 8105 return err; 8106 8107 if (eth_p_mpls(first->protocol)) 8108 ip.hdr = skb_inner_network_header(skb); 8109 else 8110 ip.hdr = skb_network_header(skb); 8111 l4.hdr = skb_checksum_start(skb); 8112 8113 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 8114 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 8115 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 8116 8117 /* initialize outer IP header fields */ 8118 if (ip.v4->version == 4) { 8119 unsigned char *csum_start = skb_checksum_start(skb); 8120 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 8121 int len = csum_start - trans_start; 8122 8123 /* IP header will have to cancel out any data that 8124 * is not a part of the outer IP header, so set to 8125 * a reverse csum if needed, else init check to 0. 8126 */ 8127 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 8128 csum_fold(csum_partial(trans_start, 8129 len, 0)) : 0; 8130 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 8131 8132 ip.v4->tot_len = 0; 8133 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8134 IXGBE_TX_FLAGS_CSUM | 8135 IXGBE_TX_FLAGS_IPV4; 8136 } else { 8137 ip.v6->payload_len = 0; 8138 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8139 IXGBE_TX_FLAGS_CSUM; 8140 } 8141 8142 /* determine offset of inner transport header */ 8143 l4_offset = l4.hdr - skb->data; 8144 8145 /* remove payload length from inner checksum */ 8146 paylen = skb->len - l4_offset; 8147 8148 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8149 /* compute length of segmentation header */ 8150 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8151 csum_replace_by_diff(&l4.tcp->check, 8152 (__force __wsum)htonl(paylen)); 8153 } else { 8154 /* compute length of segmentation header */ 8155 *hdr_len = sizeof(*l4.udp) + l4_offset; 8156 csum_replace_by_diff(&l4.udp->check, 8157 (__force __wsum)htonl(paylen)); 8158 } 8159 8160 /* update gso size and bytecount with header size */ 8161 first->gso_segs = skb_shinfo(skb)->gso_segs; 8162 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8163 8164 /* mss_l4len_id: use 0 as index for TSO */ 8165 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8166 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8167 8168 fceof_saidx |= itd->sa_idx; 8169 type_tucmd |= itd->flags | itd->trailer_len; 8170 8171 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8172 vlan_macip_lens = l4.hdr - ip.hdr; 8173 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8174 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8175 8176 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8177 mss_l4len_idx); 8178 8179 return 1; 8180} 8181 8182static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8183 struct ixgbe_tx_buffer *first, 8184 struct ixgbe_ipsec_tx_data *itd) 8185{ 8186 struct sk_buff *skb = first->skb; 8187 u32 vlan_macip_lens = 0; 8188 u32 fceof_saidx = 0; 8189 u32 type_tucmd = 0; 8190 8191 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8192csum_failed: 8193 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8194 IXGBE_TX_FLAGS_CC))) 8195 return; 8196 goto no_csum; 8197 } 8198 8199 switch (skb->csum_offset) { 8200 case offsetof(struct tcphdr, check): 8201 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8202 fallthrough; 8203 case offsetof(struct udphdr, check): 8204 break; 8205 case offsetof(struct sctphdr, checksum): 8206 /* validate that this is actually an SCTP request */ 8207 if (skb_csum_is_sctp(skb)) { 8208 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8209 break; 8210 } 8211 fallthrough; 8212 default: 8213 skb_checksum_help(skb); 8214 goto csum_failed; 8215 } 8216 8217 /* update TX checksum flag */ 8218 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8219 vlan_macip_lens = skb_checksum_start_offset(skb) - 8220 skb_network_offset(skb); 8221no_csum: 8222 /* vlan_macip_lens: MACLEN, VLAN tag */ 8223 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8224 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8225 8226 fceof_saidx |= itd->sa_idx; 8227 type_tucmd |= itd->flags | itd->trailer_len; 8228 8229 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8230} 8231 8232#define IXGBE_SET_FLAG(_input, _flag, _result) \ 8233 ((_flag <= _result) ? \ 8234 ((u32)(_input & _flag) * (_result / _flag)) : \ 8235 ((u32)(_input & _flag) / (_flag / _result))) 8236 8237static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8238{ 8239 /* set type for advanced descriptor with frame checksum insertion */ 8240 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8241 IXGBE_ADVTXD_DCMD_DEXT | 8242 IXGBE_ADVTXD_DCMD_IFCS; 8243 8244 /* set HW vlan bit if vlan is present */ 8245 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8246 IXGBE_ADVTXD_DCMD_VLE); 8247 8248 /* set segmentation enable bits for TSO/FSO */ 8249 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8250 IXGBE_ADVTXD_DCMD_TSE); 8251 8252 /* set timestamp bit if present */ 8253 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8254 IXGBE_ADVTXD_MAC_TSTAMP); 8255 8256 /* insert frame checksum */ 8257 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8258 8259 return cmd_type; 8260} 8261 8262static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8263 u32 tx_flags, unsigned int paylen) 8264{ 8265 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8266 8267 /* enable L4 checksum for TSO and TX checksum offload */ 8268 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8269 IXGBE_TX_FLAGS_CSUM, 8270 IXGBE_ADVTXD_POPTS_TXSM); 8271 8272 /* enable IPv4 checksum for TSO */ 8273 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8274 IXGBE_TX_FLAGS_IPV4, 8275 IXGBE_ADVTXD_POPTS_IXSM); 8276 8277 /* enable IPsec */ 8278 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8279 IXGBE_TX_FLAGS_IPSEC, 8280 IXGBE_ADVTXD_POPTS_IPSEC); 8281 8282 /* 8283 * Check Context must be set if Tx switch is enabled, which it 8284 * always is for case where virtual functions are running 8285 */ 8286 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8287 IXGBE_TX_FLAGS_CC, 8288 IXGBE_ADVTXD_CC); 8289 8290 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8291} 8292 8293static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8294{ 8295 if (!netif_subqueue_try_stop(tx_ring->netdev, tx_ring->queue_index, 8296 ixgbe_desc_unused(tx_ring), size)) 8297 return -EBUSY; 8298 8299 ++tx_ring->tx_stats.restart_queue; 8300 return 0; 8301} 8302 8303static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8304{ 8305 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8306 return 0; 8307 8308 return __ixgbe_maybe_stop_tx(tx_ring, size); 8309} 8310 8311static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8312 struct ixgbe_tx_buffer *first, 8313 const u8 hdr_len) 8314{ 8315 struct sk_buff *skb = first->skb; 8316 struct ixgbe_tx_buffer *tx_buffer; 8317 union ixgbe_adv_tx_desc *tx_desc; 8318 skb_frag_t *frag; 8319 dma_addr_t dma; 8320 unsigned int data_len, size; 8321 u32 tx_flags = first->tx_flags; 8322 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8323 u16 i = tx_ring->next_to_use; 8324 8325 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8326 8327 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8328 8329 size = skb_headlen(skb); 8330 data_len = skb->data_len; 8331 8332#ifdef IXGBE_FCOE 8333 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8334 if (data_len < sizeof(struct fcoe_crc_eof)) { 8335 size -= sizeof(struct fcoe_crc_eof) - data_len; 8336 data_len = 0; 8337 } else { 8338 data_len -= sizeof(struct fcoe_crc_eof); 8339 } 8340 } 8341 8342#endif 8343 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8344 8345 tx_buffer = first; 8346 8347 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 8348 if (dma_mapping_error(tx_ring->dev, dma)) 8349 goto dma_error; 8350 8351 /* record length, and DMA address */ 8352 dma_unmap_len_set(tx_buffer, len, size); 8353 dma_unmap_addr_set(tx_buffer, dma, dma); 8354 8355 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8356 8357 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 8358 tx_desc->read.cmd_type_len = 8359 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 8360 8361 i++; 8362 tx_desc++; 8363 if (i == tx_ring->count) { 8364 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8365 i = 0; 8366 } 8367 tx_desc->read.olinfo_status = 0; 8368 8369 dma += IXGBE_MAX_DATA_PER_TXD; 8370 size -= IXGBE_MAX_DATA_PER_TXD; 8371 8372 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8373 } 8374 8375 if (likely(!data_len)) 8376 break; 8377 8378 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 8379 8380 i++; 8381 tx_desc++; 8382 if (i == tx_ring->count) { 8383 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 8384 i = 0; 8385 } 8386 tx_desc->read.olinfo_status = 0; 8387 8388#ifdef IXGBE_FCOE 8389 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 8390#else 8391 size = skb_frag_size(frag); 8392#endif 8393 data_len -= size; 8394 8395 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 8396 DMA_TO_DEVICE); 8397 8398 tx_buffer = &tx_ring->tx_buffer_info[i]; 8399 } 8400 8401 /* write last descriptor with RS and EOP bits */ 8402 cmd_type |= size | IXGBE_TXD_CMD; 8403 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8404 8405 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 8406 8407 /* set the timestamp */ 8408 first->time_stamp = jiffies; 8409 8410 skb_tx_timestamp(skb); 8411 8412 /* 8413 * Force memory writes to complete before letting h/w know there 8414 * are new descriptors to fetch. (Only applicable for weak-ordered 8415 * memory model archs, such as IA-64). 8416 * 8417 * We also need this memory barrier to make certain all of the 8418 * status bits have been updated before next_to_watch is written. 8419 */ 8420 wmb(); 8421 8422 /* set next_to_watch value indicating a packet is present */ 8423 first->next_to_watch = tx_desc; 8424 8425 i++; 8426 if (i == tx_ring->count) 8427 i = 0; 8428 8429 tx_ring->next_to_use = i; 8430 8431 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 8432 8433 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 8434 writel(i, tx_ring->tail); 8435 } 8436 8437 return 0; 8438dma_error: 8439 dev_err(tx_ring->dev, "TX DMA map failed\n"); 8440 8441 /* clear dma mappings for failed tx_buffer_info map */ 8442 for (;;) { 8443 tx_buffer = &tx_ring->tx_buffer_info[i]; 8444 if (dma_unmap_len(tx_buffer, len)) 8445 dma_unmap_page(tx_ring->dev, 8446 dma_unmap_addr(tx_buffer, dma), 8447 dma_unmap_len(tx_buffer, len), 8448 DMA_TO_DEVICE); 8449 dma_unmap_len_set(tx_buffer, len, 0); 8450 if (tx_buffer == first) 8451 break; 8452 if (i == 0) 8453 i += tx_ring->count; 8454 i--; 8455 } 8456 8457 dev_kfree_skb_any(first->skb); 8458 first->skb = NULL; 8459 8460 tx_ring->next_to_use = i; 8461 8462 return -1; 8463} 8464 8465static void ixgbe_atr(struct ixgbe_ring *ring, 8466 struct ixgbe_tx_buffer *first) 8467{ 8468 struct ixgbe_q_vector *q_vector = ring->q_vector; 8469 union ixgbe_atr_hash_dword input = { .dword = 0 }; 8470 union ixgbe_atr_hash_dword common = { .dword = 0 }; 8471 union { 8472 unsigned char *network; 8473 struct iphdr *ipv4; 8474 struct ipv6hdr *ipv6; 8475 } hdr; 8476 struct tcphdr *th; 8477 unsigned int hlen; 8478 struct sk_buff *skb; 8479 __be16 vlan_id; 8480 int l4_proto; 8481 8482 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 8483 if (!q_vector) 8484 return; 8485 8486 /* do nothing if sampling is disabled */ 8487 if (!ring->atr_sample_rate) 8488 return; 8489 8490 ring->atr_count++; 8491 8492 /* currently only IPv4/IPv6 with TCP is supported */ 8493 if ((first->protocol != htons(ETH_P_IP)) && 8494 (first->protocol != htons(ETH_P_IPV6))) 8495 return; 8496 8497 /* snag network header to get L4 type and address */ 8498 skb = first->skb; 8499 hdr.network = skb_network_header(skb); 8500 if (unlikely(hdr.network <= skb->data)) 8501 return; 8502 if (skb->encapsulation && 8503 first->protocol == htons(ETH_P_IP) && 8504 hdr.ipv4->protocol == IPPROTO_UDP) { 8505 struct ixgbe_adapter *adapter = q_vector->adapter; 8506 8507 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8508 vxlan_headroom(0))) 8509 return; 8510 8511 /* verify the port is recognized as VXLAN */ 8512 if (adapter->vxlan_port && 8513 udp_hdr(skb)->dest == adapter->vxlan_port) 8514 hdr.network = skb_inner_network_header(skb); 8515 8516 if (adapter->geneve_port && 8517 udp_hdr(skb)->dest == adapter->geneve_port) 8518 hdr.network = skb_inner_network_header(skb); 8519 } 8520 8521 /* Make sure we have at least [minimum IPv4 header + TCP] 8522 * or [IPv6 header] bytes 8523 */ 8524 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 8525 return; 8526 8527 /* Currently only IPv4/IPv6 with TCP is supported */ 8528 switch (hdr.ipv4->version) { 8529 case IPVERSION: 8530 /* access ihl as u8 to avoid unaligned access on ia64 */ 8531 hlen = (hdr.network[0] & 0x0F) << 2; 8532 l4_proto = hdr.ipv4->protocol; 8533 break; 8534 case 6: 8535 hlen = hdr.network - skb->data; 8536 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 8537 hlen -= hdr.network - skb->data; 8538 break; 8539 default: 8540 return; 8541 } 8542 8543 if (l4_proto != IPPROTO_TCP) 8544 return; 8545 8546 if (unlikely(skb_tail_pointer(skb) < hdr.network + 8547 hlen + sizeof(struct tcphdr))) 8548 return; 8549 8550 th = (struct tcphdr *)(hdr.network + hlen); 8551 8552 /* skip this packet since the socket is closing */ 8553 if (th->fin) 8554 return; 8555 8556 /* sample on all syn packets or once every atr sample count */ 8557 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 8558 return; 8559 8560 /* reset sample count */ 8561 ring->atr_count = 0; 8562 8563 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 8564 8565 /* 8566 * src and dst are inverted, think how the receiver sees them 8567 * 8568 * The input is broken into two sections, a non-compressed section 8569 * containing vm_pool, vlan_id, and flow_type. The rest of the data 8570 * is XORed together and stored in the compressed dword. 8571 */ 8572 input.formatted.vlan_id = vlan_id; 8573 8574 /* 8575 * since src port and flex bytes occupy the same word XOR them together 8576 * and write the value to source port portion of compressed dword 8577 */ 8578 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 8579 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 8580 else 8581 common.port.src ^= th->dest ^ first->protocol; 8582 common.port.dst ^= th->source; 8583 8584 switch (hdr.ipv4->version) { 8585 case IPVERSION: 8586 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 8587 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 8588 break; 8589 case 6: 8590 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 8591 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 8592 hdr.ipv6->saddr.s6_addr32[1] ^ 8593 hdr.ipv6->saddr.s6_addr32[2] ^ 8594 hdr.ipv6->saddr.s6_addr32[3] ^ 8595 hdr.ipv6->daddr.s6_addr32[0] ^ 8596 hdr.ipv6->daddr.s6_addr32[1] ^ 8597 hdr.ipv6->daddr.s6_addr32[2] ^ 8598 hdr.ipv6->daddr.s6_addr32[3]; 8599 break; 8600 default: 8601 break; 8602 } 8603 8604 if (hdr.network != skb_network_header(skb)) 8605 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 8606 8607 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 8608 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 8609 input, common, ring->queue_index); 8610} 8611 8612#ifdef IXGBE_FCOE 8613static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 8614 struct net_device *sb_dev) 8615{ 8616 struct ixgbe_adapter *adapter; 8617 struct ixgbe_ring_feature *f; 8618 int txq; 8619 8620 if (sb_dev) { 8621 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 8622 struct net_device *vdev = sb_dev; 8623 8624 txq = vdev->tc_to_txq[tc].offset; 8625 txq += reciprocal_scale(skb_get_hash(skb), 8626 vdev->tc_to_txq[tc].count); 8627 8628 return txq; 8629 } 8630 8631 /* 8632 * only execute the code below if protocol is FCoE 8633 * or FIP and we have FCoE enabled on the adapter 8634 */ 8635 switch (vlan_get_protocol(skb)) { 8636 case htons(ETH_P_FCOE): 8637 case htons(ETH_P_FIP): 8638 adapter = netdev_priv(dev); 8639 8640 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 8641 break; 8642 fallthrough; 8643 default: 8644 return netdev_pick_tx(dev, skb, sb_dev); 8645 } 8646 8647 f = &adapter->ring_feature[RING_F_FCOE]; 8648 8649 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 8650 smp_processor_id(); 8651 8652 while (txq >= f->indices) 8653 txq -= f->indices; 8654 8655 return txq + f->offset; 8656} 8657 8658#endif 8659int ixgbe_xmit_xdp_ring(struct ixgbe_ring *ring, 8660 struct xdp_frame *xdpf) 8661{ 8662 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 8663 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 8664 u16 i = 0, index = ring->next_to_use; 8665 struct ixgbe_tx_buffer *tx_head = &ring->tx_buffer_info[index]; 8666 struct ixgbe_tx_buffer *tx_buff = tx_head; 8667 union ixgbe_adv_tx_desc *tx_desc = IXGBE_TX_DESC(ring, index); 8668 u32 cmd_type, len = xdpf->len; 8669 void *data = xdpf->data; 8670 8671 if (unlikely(ixgbe_desc_unused(ring) < 1 + nr_frags)) 8672 return IXGBE_XDP_CONSUMED; 8673 8674 tx_head->bytecount = xdp_get_frame_len(xdpf); 8675 tx_head->gso_segs = 1; 8676 tx_head->xdpf = xdpf; 8677 8678 tx_desc->read.olinfo_status = 8679 cpu_to_le32(tx_head->bytecount << IXGBE_ADVTXD_PAYLEN_SHIFT); 8680 8681 for (;;) { 8682 dma_addr_t dma; 8683 8684 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 8685 if (dma_mapping_error(ring->dev, dma)) 8686 goto unmap; 8687 8688 dma_unmap_len_set(tx_buff, len, len); 8689 dma_unmap_addr_set(tx_buff, dma, dma); 8690 8691 cmd_type = IXGBE_ADVTXD_DTYP_DATA | IXGBE_ADVTXD_DCMD_DEXT | 8692 IXGBE_ADVTXD_DCMD_IFCS | len; 8693 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 8694 tx_desc->read.buffer_addr = cpu_to_le64(dma); 8695 tx_buff->protocol = 0; 8696 8697 if (++index == ring->count) 8698 index = 0; 8699 8700 if (i == nr_frags) 8701 break; 8702 8703 tx_buff = &ring->tx_buffer_info[index]; 8704 tx_desc = IXGBE_TX_DESC(ring, index); 8705 tx_desc->read.olinfo_status = 0; 8706 8707 data = skb_frag_address(&sinfo->frags[i]); 8708 len = skb_frag_size(&sinfo->frags[i]); 8709 i++; 8710 } 8711 /* put descriptor type bits */ 8712 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); 8713 8714 /* Avoid any potential race with xdp_xmit and cleanup */ 8715 smp_wmb(); 8716 8717 tx_head->next_to_watch = tx_desc; 8718 ring->next_to_use = index; 8719 8720 return IXGBE_XDP_TX; 8721 8722unmap: 8723 for (;;) { 8724 tx_buff = &ring->tx_buffer_info[index]; 8725 if (dma_unmap_len(tx_buff, len)) 8726 dma_unmap_page(ring->dev, dma_unmap_addr(tx_buff, dma), 8727 dma_unmap_len(tx_buff, len), 8728 DMA_TO_DEVICE); 8729 dma_unmap_len_set(tx_buff, len, 0); 8730 if (tx_buff == tx_head) 8731 break; 8732 8733 if (!index) 8734 index += ring->count; 8735 index--; 8736 } 8737 8738 return IXGBE_XDP_CONSUMED; 8739} 8740 8741netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 8742 struct ixgbe_adapter *adapter, 8743 struct ixgbe_ring *tx_ring) 8744{ 8745 struct ixgbe_tx_buffer *first; 8746 int tso; 8747 u32 tx_flags = 0; 8748 unsigned short f; 8749 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 8750 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 8751 __be16 protocol = skb->protocol; 8752 u8 hdr_len = 0; 8753 8754 /* 8755 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 8756 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 8757 * + 2 desc gap to keep tail from touching head, 8758 * + 1 desc for context descriptor, 8759 * otherwise try next time 8760 */ 8761 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 8762 count += TXD_USE_COUNT(skb_frag_size( 8763 &skb_shinfo(skb)->frags[f])); 8764 8765 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 8766 tx_ring->tx_stats.tx_busy++; 8767 return NETDEV_TX_BUSY; 8768 } 8769 8770 /* record the location of the first descriptor for this packet */ 8771 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 8772 first->skb = skb; 8773 first->bytecount = skb->len; 8774 first->gso_segs = 1; 8775 8776 /* if we have a HW VLAN tag being added default to the HW one */ 8777 if (skb_vlan_tag_present(skb)) { 8778 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 8779 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8780 /* else if it is a SW VLAN check the next protocol and store the tag */ 8781 } else if (protocol == htons(ETH_P_8021Q)) { 8782 struct vlan_hdr *vhdr, _vhdr; 8783 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 8784 if (!vhdr) 8785 goto out_drop; 8786 8787 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 8788 IXGBE_TX_FLAGS_VLAN_SHIFT; 8789 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 8790 } 8791 protocol = vlan_get_protocol(skb); 8792 8793 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 8794 adapter->ptp_clock) { 8795 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 8796 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 8797 &adapter->state)) { 8798 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 8799 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 8800 8801 /* schedule check for Tx timestamp */ 8802 adapter->ptp_tx_skb = skb_get(skb); 8803 adapter->ptp_tx_start = jiffies; 8804 schedule_work(&adapter->ptp_tx_work); 8805 } else { 8806 adapter->tx_hwtstamp_skipped++; 8807 } 8808 } 8809 8810#ifdef CONFIG_PCI_IOV 8811 /* 8812 * Use the l2switch_enable flag - would be false if the DMA 8813 * Tx switch had been disabled. 8814 */ 8815 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 8816 tx_flags |= IXGBE_TX_FLAGS_CC; 8817 8818#endif 8819 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 8820 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 8821 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 8822 (skb->priority != TC_PRIO_CONTROL))) { 8823 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 8824 tx_flags |= (skb->priority & 0x7) << 8825 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 8826 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 8827 struct vlan_ethhdr *vhdr; 8828 8829 if (skb_cow_head(skb, 0)) 8830 goto out_drop; 8831 vhdr = skb_vlan_eth_hdr(skb); 8832 vhdr->h_vlan_TCI = htons(tx_flags >> 8833 IXGBE_TX_FLAGS_VLAN_SHIFT); 8834 } else { 8835 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 8836 } 8837 } 8838 8839 /* record initial flags and protocol */ 8840 first->tx_flags = tx_flags; 8841 first->protocol = protocol; 8842 8843#ifdef IXGBE_FCOE 8844 /* setup tx offload for FCoE */ 8845 if ((protocol == htons(ETH_P_FCOE)) && 8846 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 8847 tso = ixgbe_fso(tx_ring, first, &hdr_len); 8848 if (tso < 0) 8849 goto out_drop; 8850 8851 goto xmit_fcoe; 8852 } 8853 8854#endif /* IXGBE_FCOE */ 8855 8856#ifdef CONFIG_IXGBE_IPSEC 8857 if (xfrm_offload(skb) && 8858 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 8859 goto out_drop; 8860#endif 8861 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 8862 if (tso < 0) 8863 goto out_drop; 8864 else if (!tso) 8865 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 8866 8867 /* add the ATR filter if ATR is on */ 8868 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) 8869 ixgbe_atr(tx_ring, first); 8870 8871#ifdef IXGBE_FCOE 8872xmit_fcoe: 8873#endif /* IXGBE_FCOE */ 8874 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 8875 goto cleanup_tx_timestamp; 8876 8877 return NETDEV_TX_OK; 8878 8879out_drop: 8880 dev_kfree_skb_any(first->skb); 8881 first->skb = NULL; 8882cleanup_tx_timestamp: 8883 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 8884 dev_kfree_skb_any(adapter->ptp_tx_skb); 8885 adapter->ptp_tx_skb = NULL; 8886 cancel_work_sync(&adapter->ptp_tx_work); 8887 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 8888 } 8889 8890 return NETDEV_TX_OK; 8891} 8892 8893static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 8894 struct net_device *netdev, 8895 struct ixgbe_ring *ring) 8896{ 8897 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8898 struct ixgbe_ring *tx_ring; 8899 8900 /* 8901 * The minimum packet size for olinfo paylen is 17 so pad the skb 8902 * in order to meet this minimum size requirement. 8903 */ 8904 if (skb_put_padto(skb, 17)) 8905 return NETDEV_TX_OK; 8906 8907 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 8908 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state))) 8909 return NETDEV_TX_BUSY; 8910 8911 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 8912} 8913 8914static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 8915 struct net_device *netdev) 8916{ 8917 return __ixgbe_xmit_frame(skb, netdev, NULL); 8918} 8919 8920/** 8921 * ixgbe_set_mac - Change the Ethernet Address of the NIC 8922 * @netdev: network interface device structure 8923 * @p: pointer to an address structure 8924 * 8925 * Returns 0 on success, negative on failure 8926 **/ 8927static int ixgbe_set_mac(struct net_device *netdev, void *p) 8928{ 8929 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8930 struct ixgbe_hw *hw = &adapter->hw; 8931 struct sockaddr *addr = p; 8932 8933 if (!is_valid_ether_addr(addr->sa_data)) 8934 return -EADDRNOTAVAIL; 8935 8936 eth_hw_addr_set(netdev, addr->sa_data); 8937 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 8938 8939 ixgbe_mac_set_default_filter(adapter); 8940 8941 return 0; 8942} 8943 8944static int 8945ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 8946{ 8947 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8948 struct ixgbe_hw *hw = &adapter->hw; 8949 u16 value; 8950 int rc; 8951 8952 if (adapter->mii_bus) { 8953 int regnum = addr; 8954 8955 if (devad != MDIO_DEVAD_NONE) 8956 return mdiobus_c45_read(adapter->mii_bus, prtad, 8957 devad, regnum); 8958 8959 return mdiobus_read(adapter->mii_bus, prtad, regnum); 8960 } 8961 8962 if (prtad != hw->phy.mdio.prtad) 8963 return -EINVAL; 8964 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 8965 if (!rc) 8966 rc = value; 8967 return rc; 8968} 8969 8970static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 8971 u16 addr, u16 value) 8972{ 8973 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8974 struct ixgbe_hw *hw = &adapter->hw; 8975 8976 if (adapter->mii_bus) { 8977 int regnum = addr; 8978 8979 if (devad != MDIO_DEVAD_NONE) 8980 return mdiobus_c45_write(adapter->mii_bus, prtad, devad, 8981 regnum, value); 8982 8983 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 8984 } 8985 8986 if (prtad != hw->phy.mdio.prtad) 8987 return -EINVAL; 8988 return hw->phy.ops.write_reg(hw, addr, devad, value); 8989} 8990 8991static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 8992{ 8993 struct ixgbe_adapter *adapter = netdev_priv(netdev); 8994 8995 switch (cmd) { 8996 case SIOCSHWTSTAMP: 8997 return ixgbe_ptp_set_ts_config(adapter, req); 8998 case SIOCGHWTSTAMP: 8999 return ixgbe_ptp_get_ts_config(adapter, req); 9000 case SIOCGMIIPHY: 9001 if (!adapter->hw.phy.ops.read_reg) 9002 return -EOPNOTSUPP; 9003 fallthrough; 9004 default: 9005 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 9006 } 9007} 9008 9009/** 9010 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 9011 * netdev->dev_addrs 9012 * @dev: network interface device structure 9013 * 9014 * Returns non-zero on failure 9015 **/ 9016static int ixgbe_add_sanmac_netdev(struct net_device *dev) 9017{ 9018 int err = 0; 9019 struct ixgbe_adapter *adapter = netdev_priv(dev); 9020 struct ixgbe_hw *hw = &adapter->hw; 9021 9022 if (is_valid_ether_addr(hw->mac.san_addr)) { 9023 rtnl_lock(); 9024 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 9025 rtnl_unlock(); 9026 9027 /* update SAN MAC vmdq pool selection */ 9028 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 9029 } 9030 return err; 9031} 9032 9033/** 9034 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 9035 * netdev->dev_addrs 9036 * @dev: network interface device structure 9037 * 9038 * Returns non-zero on failure 9039 **/ 9040static int ixgbe_del_sanmac_netdev(struct net_device *dev) 9041{ 9042 int err = 0; 9043 struct ixgbe_adapter *adapter = netdev_priv(dev); 9044 struct ixgbe_mac_info *mac = &adapter->hw.mac; 9045 9046 if (is_valid_ether_addr(mac->san_addr)) { 9047 rtnl_lock(); 9048 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 9049 rtnl_unlock(); 9050 } 9051 return err; 9052} 9053 9054static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 9055 struct ixgbe_ring *ring) 9056{ 9057 u64 bytes, packets; 9058 unsigned int start; 9059 9060 if (ring) { 9061 do { 9062 start = u64_stats_fetch_begin(&ring->syncp); 9063 packets = ring->stats.packets; 9064 bytes = ring->stats.bytes; 9065 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9066 stats->tx_packets += packets; 9067 stats->tx_bytes += bytes; 9068 } 9069} 9070 9071static void ixgbe_get_stats64(struct net_device *netdev, 9072 struct rtnl_link_stats64 *stats) 9073{ 9074 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9075 int i; 9076 9077 rcu_read_lock(); 9078 for (i = 0; i < adapter->num_rx_queues; i++) { 9079 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 9080 u64 bytes, packets; 9081 unsigned int start; 9082 9083 if (ring) { 9084 do { 9085 start = u64_stats_fetch_begin(&ring->syncp); 9086 packets = ring->stats.packets; 9087 bytes = ring->stats.bytes; 9088 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9089 stats->rx_packets += packets; 9090 stats->rx_bytes += bytes; 9091 } 9092 } 9093 9094 for (i = 0; i < adapter->num_tx_queues; i++) { 9095 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 9096 9097 ixgbe_get_ring_stats64(stats, ring); 9098 } 9099 for (i = 0; i < adapter->num_xdp_queues; i++) { 9100 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 9101 9102 ixgbe_get_ring_stats64(stats, ring); 9103 } 9104 rcu_read_unlock(); 9105 9106 /* following stats updated by ixgbe_watchdog_task() */ 9107 stats->multicast = netdev->stats.multicast; 9108 stats->rx_errors = netdev->stats.rx_errors; 9109 stats->rx_length_errors = netdev->stats.rx_length_errors; 9110 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 9111 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 9112} 9113 9114static int ixgbe_ndo_get_vf_stats(struct net_device *netdev, int vf, 9115 struct ifla_vf_stats *vf_stats) 9116{ 9117 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9118 9119 if (vf < 0 || vf >= adapter->num_vfs) 9120 return -EINVAL; 9121 9122 vf_stats->rx_packets = adapter->vfinfo[vf].vfstats.gprc; 9123 vf_stats->rx_bytes = adapter->vfinfo[vf].vfstats.gorc; 9124 vf_stats->tx_packets = adapter->vfinfo[vf].vfstats.gptc; 9125 vf_stats->tx_bytes = adapter->vfinfo[vf].vfstats.gotc; 9126 vf_stats->multicast = adapter->vfinfo[vf].vfstats.mprc; 9127 9128 return 0; 9129} 9130 9131#ifdef CONFIG_IXGBE_DCB 9132/** 9133 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 9134 * @adapter: pointer to ixgbe_adapter 9135 * @tc: number of traffic classes currently enabled 9136 * 9137 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 9138 * 802.1Q priority maps to a packet buffer that exists. 9139 */ 9140static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 9141{ 9142 struct ixgbe_hw *hw = &adapter->hw; 9143 u32 reg, rsave; 9144 int i; 9145 9146 /* 82598 have a static priority to TC mapping that can not 9147 * be changed so no validation is needed. 9148 */ 9149 if (hw->mac.type == ixgbe_mac_82598EB) 9150 return; 9151 9152 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 9153 rsave = reg; 9154 9155 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 9156 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9157 9158 /* If up2tc is out of bounds default to zero */ 9159 if (up2tc > tc) 9160 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9161 } 9162 9163 if (reg != rsave) 9164 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9165 9166 return; 9167} 9168 9169/** 9170 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9171 * @adapter: Pointer to adapter struct 9172 * 9173 * Populate the netdev user priority to tc map 9174 */ 9175static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9176{ 9177 struct net_device *dev = adapter->netdev; 9178 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9179 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9180 u8 prio; 9181 9182 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9183 u8 tc = 0; 9184 9185 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9186 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9187 else if (ets) 9188 tc = ets->prio_tc[prio]; 9189 9190 netdev_set_prio_tc_map(dev, prio, tc); 9191 } 9192} 9193 9194#endif /* CONFIG_IXGBE_DCB */ 9195static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9196 struct netdev_nested_priv *priv) 9197{ 9198 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9199 struct ixgbe_fwd_adapter *accel; 9200 int pool; 9201 9202 /* we only care about macvlans... */ 9203 if (!netif_is_macvlan(vdev)) 9204 return 0; 9205 9206 /* that have hardware offload enabled... */ 9207 accel = macvlan_accel_priv(vdev); 9208 if (!accel) 9209 return 0; 9210 9211 /* If we can relocate to a different bit do so */ 9212 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9213 if (pool < adapter->num_rx_pools) { 9214 set_bit(pool, adapter->fwd_bitmask); 9215 accel->pool = pool; 9216 return 0; 9217 } 9218 9219 /* if we cannot find a free pool then disable the offload */ 9220 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9221 macvlan_release_l2fw_offload(vdev); 9222 9223 /* unbind the queues and drop the subordinate channel config */ 9224 netdev_unbind_sb_channel(adapter->netdev, vdev); 9225 netdev_set_sb_channel(vdev, 0); 9226 9227 kfree(accel); 9228 9229 return 0; 9230} 9231 9232static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9233{ 9234 struct ixgbe_adapter *adapter = netdev_priv(dev); 9235 struct netdev_nested_priv priv = { 9236 .data = (void *)adapter, 9237 }; 9238 9239 /* flush any stale bits out of the fwd bitmask */ 9240 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9241 9242 /* walk through upper devices reassigning pools */ 9243 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9244 &priv); 9245} 9246 9247/** 9248 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9249 * 9250 * @dev: net device to configure 9251 * @tc: number of traffic classes to enable 9252 */ 9253int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9254{ 9255 struct ixgbe_adapter *adapter = netdev_priv(dev); 9256 struct ixgbe_hw *hw = &adapter->hw; 9257 9258 /* Hardware supports up to 8 traffic classes */ 9259 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9260 return -EINVAL; 9261 9262 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9263 return -EINVAL; 9264 9265 /* Hardware has to reinitialize queues and interrupts to 9266 * match packet buffer alignment. Unfortunately, the 9267 * hardware is not flexible enough to do this dynamically. 9268 */ 9269 if (netif_running(dev)) 9270 ixgbe_close(dev); 9271 else 9272 ixgbe_reset(adapter); 9273 9274 ixgbe_clear_interrupt_scheme(adapter); 9275 9276#ifdef CONFIG_IXGBE_DCB 9277 if (tc) { 9278 if (adapter->xdp_prog) { 9279 e_warn(probe, "DCB is not supported with XDP\n"); 9280 9281 ixgbe_init_interrupt_scheme(adapter); 9282 if (netif_running(dev)) 9283 ixgbe_open(dev); 9284 return -EINVAL; 9285 } 9286 9287 netdev_set_num_tc(dev, tc); 9288 ixgbe_set_prio_tc_map(adapter); 9289 9290 adapter->hw_tcs = tc; 9291 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9292 9293 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9294 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9295 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9296 } 9297 } else { 9298 netdev_reset_tc(dev); 9299 9300 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9301 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9302 9303 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9304 adapter->hw_tcs = tc; 9305 9306 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9307 adapter->dcb_cfg.pfc_mode_enable = false; 9308 } 9309 9310 ixgbe_validate_rtr(adapter, tc); 9311 9312#endif /* CONFIG_IXGBE_DCB */ 9313 ixgbe_init_interrupt_scheme(adapter); 9314 9315 ixgbe_defrag_macvlan_pools(dev); 9316 9317 if (netif_running(dev)) 9318 return ixgbe_open(dev); 9319 9320 return 0; 9321} 9322 9323static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9324 struct tc_cls_u32_offload *cls) 9325{ 9326 u32 hdl = cls->knode.handle; 9327 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9328 u32 loc = cls->knode.handle & 0xfffff; 9329 int err = 0, i, j; 9330 struct ixgbe_jump_table *jump = NULL; 9331 9332 if (loc > IXGBE_MAX_HW_ENTRIES) 9333 return -EINVAL; 9334 9335 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9336 return -EINVAL; 9337 9338 /* Clear this filter in the link data it is associated with */ 9339 if (uhtid != 0x800) { 9340 jump = adapter->jump_tables[uhtid]; 9341 if (!jump) 9342 return -EINVAL; 9343 if (!test_bit(loc - 1, jump->child_loc_map)) 9344 return -EINVAL; 9345 clear_bit(loc - 1, jump->child_loc_map); 9346 } 9347 9348 /* Check if the filter being deleted is a link */ 9349 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9350 jump = adapter->jump_tables[i]; 9351 if (jump && jump->link_hdl == hdl) { 9352 /* Delete filters in the hardware in the child hash 9353 * table associated with this link 9354 */ 9355 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 9356 if (!test_bit(j, jump->child_loc_map)) 9357 continue; 9358 spin_lock(&adapter->fdir_perfect_lock); 9359 err = ixgbe_update_ethtool_fdir_entry(adapter, 9360 NULL, 9361 j + 1); 9362 spin_unlock(&adapter->fdir_perfect_lock); 9363 clear_bit(j, jump->child_loc_map); 9364 } 9365 /* Remove resources for this link */ 9366 kfree(jump->input); 9367 kfree(jump->mask); 9368 kfree(jump); 9369 adapter->jump_tables[i] = NULL; 9370 return err; 9371 } 9372 } 9373 9374 spin_lock(&adapter->fdir_perfect_lock); 9375 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 9376 spin_unlock(&adapter->fdir_perfect_lock); 9377 return err; 9378} 9379 9380static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 9381 struct tc_cls_u32_offload *cls) 9382{ 9383 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9384 9385 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9386 return -EINVAL; 9387 9388 /* This ixgbe devices do not support hash tables at the moment 9389 * so abort when given hash tables. 9390 */ 9391 if (cls->hnode.divisor > 0) 9392 return -EINVAL; 9393 9394 set_bit(uhtid - 1, &adapter->tables); 9395 return 0; 9396} 9397 9398static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 9399 struct tc_cls_u32_offload *cls) 9400{ 9401 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 9402 9403 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9404 return -EINVAL; 9405 9406 clear_bit(uhtid - 1, &adapter->tables); 9407 return 0; 9408} 9409 9410#ifdef CONFIG_NET_CLS_ACT 9411struct upper_walk_data { 9412 struct ixgbe_adapter *adapter; 9413 u64 action; 9414 int ifindex; 9415 u8 queue; 9416}; 9417 9418static int get_macvlan_queue(struct net_device *upper, 9419 struct netdev_nested_priv *priv) 9420{ 9421 if (netif_is_macvlan(upper)) { 9422 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 9423 struct ixgbe_adapter *adapter; 9424 struct upper_walk_data *data; 9425 int ifindex; 9426 9427 data = (struct upper_walk_data *)priv->data; 9428 ifindex = data->ifindex; 9429 adapter = data->adapter; 9430 if (vadapter && upper->ifindex == ifindex) { 9431 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 9432 data->action = data->queue; 9433 return 1; 9434 } 9435 } 9436 9437 return 0; 9438} 9439 9440static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 9441 u8 *queue, u64 *action) 9442{ 9443 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 9444 unsigned int num_vfs = adapter->num_vfs, vf; 9445 struct netdev_nested_priv priv; 9446 struct upper_walk_data data; 9447 struct net_device *upper; 9448 9449 /* redirect to a SRIOV VF */ 9450 for (vf = 0; vf < num_vfs; ++vf) { 9451 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 9452 if (upper->ifindex == ifindex) { 9453 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 9454 *action = vf + 1; 9455 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 9456 return 0; 9457 } 9458 } 9459 9460 /* redirect to a offloaded macvlan netdev */ 9461 data.adapter = adapter; 9462 data.ifindex = ifindex; 9463 data.action = 0; 9464 data.queue = 0; 9465 priv.data = (void *)&data; 9466 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 9467 get_macvlan_queue, &priv)) { 9468 *action = data.action; 9469 *queue = data.queue; 9470 9471 return 0; 9472 } 9473 9474 return -EINVAL; 9475} 9476 9477static int parse_tc_actions(struct ixgbe_adapter *adapter, 9478 struct tcf_exts *exts, u64 *action, u8 *queue) 9479{ 9480 const struct tc_action *a; 9481 int i; 9482 9483 if (!tcf_exts_has_actions(exts)) 9484 return -EINVAL; 9485 9486 tcf_exts_for_each_action(i, a, exts) { 9487 /* Drop action */ 9488 if (is_tcf_gact_shot(a)) { 9489 *action = IXGBE_FDIR_DROP_QUEUE; 9490 *queue = IXGBE_FDIR_DROP_QUEUE; 9491 return 0; 9492 } 9493 9494 /* Redirect to a VF or a offloaded macvlan */ 9495 if (is_tcf_mirred_egress_redirect(a)) { 9496 struct net_device *dev = tcf_mirred_dev(a); 9497 9498 if (!dev) 9499 return -EINVAL; 9500 return handle_redirect_action(adapter, dev->ifindex, 9501 queue, action); 9502 } 9503 9504 return -EINVAL; 9505 } 9506 9507 return -EINVAL; 9508} 9509#else 9510static int parse_tc_actions(struct ixgbe_adapter *adapter, 9511 struct tcf_exts *exts, u64 *action, u8 *queue) 9512{ 9513 return -EINVAL; 9514} 9515#endif /* CONFIG_NET_CLS_ACT */ 9516 9517static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 9518 union ixgbe_atr_input *mask, 9519 struct tc_cls_u32_offload *cls, 9520 struct ixgbe_mat_field *field_ptr, 9521 struct ixgbe_nexthdr *nexthdr) 9522{ 9523 int i, j, off; 9524 __be32 val, m; 9525 bool found_entry = false, found_jump_field = false; 9526 9527 for (i = 0; i < cls->knode.sel->nkeys; i++) { 9528 off = cls->knode.sel->keys[i].off; 9529 val = cls->knode.sel->keys[i].val; 9530 m = cls->knode.sel->keys[i].mask; 9531 9532 for (j = 0; field_ptr[j].val; j++) { 9533 if (field_ptr[j].off == off) { 9534 field_ptr[j].val(input, mask, (__force u32)val, 9535 (__force u32)m); 9536 input->filter.formatted.flow_type |= 9537 field_ptr[j].type; 9538 found_entry = true; 9539 break; 9540 } 9541 } 9542 if (nexthdr) { 9543 if (nexthdr->off == cls->knode.sel->keys[i].off && 9544 nexthdr->val == 9545 (__force u32)cls->knode.sel->keys[i].val && 9546 nexthdr->mask == 9547 (__force u32)cls->knode.sel->keys[i].mask) 9548 found_jump_field = true; 9549 else 9550 continue; 9551 } 9552 } 9553 9554 if (nexthdr && !found_jump_field) 9555 return -EINVAL; 9556 9557 if (!found_entry) 9558 return 0; 9559 9560 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 9561 IXGBE_ATR_L4TYPE_MASK; 9562 9563 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 9564 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 9565 9566 return 0; 9567} 9568 9569static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 9570 struct tc_cls_u32_offload *cls) 9571{ 9572 __be16 protocol = cls->common.protocol; 9573 u32 loc = cls->knode.handle & 0xfffff; 9574 struct ixgbe_hw *hw = &adapter->hw; 9575 struct ixgbe_mat_field *field_ptr; 9576 struct ixgbe_fdir_filter *input = NULL; 9577 union ixgbe_atr_input *mask = NULL; 9578 struct ixgbe_jump_table *jump = NULL; 9579 int i, err = -EINVAL; 9580 u8 queue; 9581 u32 uhtid, link_uhtid; 9582 9583 uhtid = TC_U32_USERHTID(cls->knode.handle); 9584 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 9585 9586 /* At the moment cls_u32 jumps to network layer and skips past 9587 * L2 headers. The canonical method to match L2 frames is to use 9588 * negative values. However this is error prone at best but really 9589 * just broken because there is no way to "know" what sort of hdr 9590 * is in front of the network layer. Fix cls_u32 to support L2 9591 * headers when needed. 9592 */ 9593 if (protocol != htons(ETH_P_IP)) 9594 return err; 9595 9596 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 9597 e_err(drv, "Location out of range\n"); 9598 return err; 9599 } 9600 9601 /* cls u32 is a graph starting at root node 0x800. The driver tracks 9602 * links and also the fields used to advance the parser across each 9603 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 9604 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 9605 * To add support for new nodes update ixgbe_model.h parse structures 9606 * this function _should_ be generic try not to hardcode values here. 9607 */ 9608 if (uhtid == 0x800) { 9609 field_ptr = (adapter->jump_tables[0])->mat; 9610 } else { 9611 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 9612 return err; 9613 if (!adapter->jump_tables[uhtid]) 9614 return err; 9615 field_ptr = (adapter->jump_tables[uhtid])->mat; 9616 } 9617 9618 if (!field_ptr) 9619 return err; 9620 9621 /* At this point we know the field_ptr is valid and need to either 9622 * build cls_u32 link or attach filter. Because adding a link to 9623 * a handle that does not exist is invalid and the same for adding 9624 * rules to handles that don't exist. 9625 */ 9626 9627 if (link_uhtid) { 9628 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 9629 9630 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 9631 return err; 9632 9633 if (!test_bit(link_uhtid - 1, &adapter->tables)) 9634 return err; 9635 9636 /* Multiple filters as links to the same hash table are not 9637 * supported. To add a new filter with the same next header 9638 * but different match/jump conditions, create a new hash table 9639 * and link to it. 9640 */ 9641 if (adapter->jump_tables[link_uhtid] && 9642 (adapter->jump_tables[link_uhtid])->link_hdl) { 9643 e_err(drv, "Link filter exists for link: %x\n", 9644 link_uhtid); 9645 return err; 9646 } 9647 9648 for (i = 0; nexthdr[i].jump; i++) { 9649 if (nexthdr[i].o != cls->knode.sel->offoff || 9650 nexthdr[i].s != cls->knode.sel->offshift || 9651 nexthdr[i].m != 9652 (__force u32)cls->knode.sel->offmask) 9653 return err; 9654 9655 jump = kzalloc(sizeof(*jump), GFP_KERNEL); 9656 if (!jump) 9657 return -ENOMEM; 9658 input = kzalloc(sizeof(*input), GFP_KERNEL); 9659 if (!input) { 9660 err = -ENOMEM; 9661 goto free_jump; 9662 } 9663 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9664 if (!mask) { 9665 err = -ENOMEM; 9666 goto free_input; 9667 } 9668 jump->input = input; 9669 jump->mask = mask; 9670 jump->link_hdl = cls->knode.handle; 9671 9672 err = ixgbe_clsu32_build_input(input, mask, cls, 9673 field_ptr, &nexthdr[i]); 9674 if (!err) { 9675 jump->mat = nexthdr[i].jump; 9676 adapter->jump_tables[link_uhtid] = jump; 9677 break; 9678 } else { 9679 kfree(mask); 9680 kfree(input); 9681 kfree(jump); 9682 } 9683 } 9684 return 0; 9685 } 9686 9687 input = kzalloc(sizeof(*input), GFP_KERNEL); 9688 if (!input) 9689 return -ENOMEM; 9690 mask = kzalloc(sizeof(*mask), GFP_KERNEL); 9691 if (!mask) { 9692 err = -ENOMEM; 9693 goto free_input; 9694 } 9695 9696 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 9697 if ((adapter->jump_tables[uhtid])->input) 9698 memcpy(input, (adapter->jump_tables[uhtid])->input, 9699 sizeof(*input)); 9700 if ((adapter->jump_tables[uhtid])->mask) 9701 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 9702 sizeof(*mask)); 9703 9704 /* Lookup in all child hash tables if this location is already 9705 * filled with a filter 9706 */ 9707 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9708 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 9709 9710 if (link && (test_bit(loc - 1, link->child_loc_map))) { 9711 e_err(drv, "Filter exists in location: %x\n", 9712 loc); 9713 err = -EINVAL; 9714 goto err_out; 9715 } 9716 } 9717 } 9718 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 9719 if (err) 9720 goto err_out; 9721 9722 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 9723 &queue); 9724 if (err < 0) 9725 goto err_out; 9726 9727 input->sw_idx = loc; 9728 9729 spin_lock(&adapter->fdir_perfect_lock); 9730 9731 if (hlist_empty(&adapter->fdir_filter_list)) { 9732 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 9733 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 9734 if (err) 9735 goto err_out_w_lock; 9736 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 9737 err = -EINVAL; 9738 goto err_out_w_lock; 9739 } 9740 9741 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 9742 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 9743 input->sw_idx, queue); 9744 if (err) 9745 goto err_out_w_lock; 9746 9747 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 9748 spin_unlock(&adapter->fdir_perfect_lock); 9749 9750 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 9751 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 9752 9753 kfree(mask); 9754 return err; 9755err_out_w_lock: 9756 spin_unlock(&adapter->fdir_perfect_lock); 9757err_out: 9758 kfree(mask); 9759free_input: 9760 kfree(input); 9761free_jump: 9762 kfree(jump); 9763 return err; 9764} 9765 9766static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 9767 struct tc_cls_u32_offload *cls_u32) 9768{ 9769 switch (cls_u32->command) { 9770 case TC_CLSU32_NEW_KNODE: 9771 case TC_CLSU32_REPLACE_KNODE: 9772 return ixgbe_configure_clsu32(adapter, cls_u32); 9773 case TC_CLSU32_DELETE_KNODE: 9774 return ixgbe_delete_clsu32(adapter, cls_u32); 9775 case TC_CLSU32_NEW_HNODE: 9776 case TC_CLSU32_REPLACE_HNODE: 9777 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 9778 case TC_CLSU32_DELETE_HNODE: 9779 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 9780 default: 9781 return -EOPNOTSUPP; 9782 } 9783} 9784 9785static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 9786 void *cb_priv) 9787{ 9788 struct ixgbe_adapter *adapter = cb_priv; 9789 9790 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 9791 return -EOPNOTSUPP; 9792 9793 switch (type) { 9794 case TC_SETUP_CLSU32: 9795 return ixgbe_setup_tc_cls_u32(adapter, type_data); 9796 default: 9797 return -EOPNOTSUPP; 9798 } 9799} 9800 9801static int ixgbe_setup_tc_mqprio(struct net_device *dev, 9802 struct tc_mqprio_qopt *mqprio) 9803{ 9804 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 9805 return ixgbe_setup_tc(dev, mqprio->num_tc); 9806} 9807 9808static LIST_HEAD(ixgbe_block_cb_list); 9809 9810static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 9811 void *type_data) 9812{ 9813 struct ixgbe_adapter *adapter = netdev_priv(dev); 9814 9815 switch (type) { 9816 case TC_SETUP_BLOCK: 9817 return flow_block_cb_setup_simple(type_data, 9818 &ixgbe_block_cb_list, 9819 ixgbe_setup_tc_block_cb, 9820 adapter, adapter, true); 9821 case TC_SETUP_QDISC_MQPRIO: 9822 return ixgbe_setup_tc_mqprio(dev, type_data); 9823 default: 9824 return -EOPNOTSUPP; 9825 } 9826} 9827 9828#ifdef CONFIG_PCI_IOV 9829void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 9830{ 9831 struct net_device *netdev = adapter->netdev; 9832 9833 rtnl_lock(); 9834 ixgbe_setup_tc(netdev, adapter->hw_tcs); 9835 rtnl_unlock(); 9836} 9837 9838#endif 9839void ixgbe_do_reset(struct net_device *netdev) 9840{ 9841 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9842 9843 if (netif_running(netdev)) 9844 ixgbe_reinit_locked(adapter); 9845 else 9846 ixgbe_reset(adapter); 9847} 9848 9849static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 9850 netdev_features_t features) 9851{ 9852 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9853 9854 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 9855 if (!(features & NETIF_F_RXCSUM)) 9856 features &= ~NETIF_F_LRO; 9857 9858 /* Turn off LRO if not RSC capable */ 9859 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 9860 features &= ~NETIF_F_LRO; 9861 9862 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 9863 e_dev_err("LRO is not supported with XDP\n"); 9864 features &= ~NETIF_F_LRO; 9865 } 9866 9867 return features; 9868} 9869 9870static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 9871{ 9872 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 9873 num_online_cpus()); 9874 9875 /* go back to full RSS if we're not running SR-IOV */ 9876 if (!adapter->ring_feature[RING_F_VMDQ].offset) 9877 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 9878 IXGBE_FLAG_SRIOV_ENABLED); 9879 9880 adapter->ring_feature[RING_F_RSS].limit = rss; 9881 adapter->ring_feature[RING_F_VMDQ].limit = 1; 9882 9883 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 9884} 9885 9886static int ixgbe_set_features(struct net_device *netdev, 9887 netdev_features_t features) 9888{ 9889 struct ixgbe_adapter *adapter = netdev_priv(netdev); 9890 netdev_features_t changed = netdev->features ^ features; 9891 bool need_reset = false; 9892 9893 /* Make sure RSC matches LRO, reset if change */ 9894 if (!(features & NETIF_F_LRO)) { 9895 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 9896 need_reset = true; 9897 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 9898 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 9899 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 9900 if (adapter->rx_itr_setting == 1 || 9901 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 9902 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 9903 need_reset = true; 9904 } else if ((changed ^ features) & NETIF_F_LRO) { 9905 e_info(probe, "rx-usecs set too low, " 9906 "disabling RSC\n"); 9907 } 9908 } 9909 9910 /* 9911 * Check if Flow Director n-tuple support or hw_tc support was 9912 * enabled or disabled. If the state changed, we need to reset. 9913 */ 9914 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 9915 /* turn off ATR, enable perfect filters and reset */ 9916 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 9917 need_reset = true; 9918 9919 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 9920 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9921 } else { 9922 /* turn off perfect filters, enable ATR and reset */ 9923 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 9924 need_reset = true; 9925 9926 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 9927 9928 /* We cannot enable ATR if SR-IOV is enabled */ 9929 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 9930 /* We cannot enable ATR if we have 2 or more tcs */ 9931 (adapter->hw_tcs > 1) || 9932 /* We cannot enable ATR if RSS is disabled */ 9933 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 9934 /* A sample rate of 0 indicates ATR disabled */ 9935 (!adapter->atr_sample_rate)) 9936 ; /* do nothing not supported */ 9937 else /* otherwise supported and set the flag */ 9938 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 9939 } 9940 9941 if (changed & NETIF_F_RXALL) 9942 need_reset = true; 9943 9944 netdev->features = features; 9945 9946 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 9947 ixgbe_reset_l2fw_offload(adapter); 9948 else if (need_reset) 9949 ixgbe_do_reset(netdev); 9950 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 9951 NETIF_F_HW_VLAN_CTAG_FILTER)) 9952 ixgbe_set_rx_mode(netdev); 9953 9954 return 1; 9955} 9956 9957static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 9958 struct net_device *dev, 9959 const unsigned char *addr, u16 vid, 9960 u16 flags, 9961 struct netlink_ext_ack *extack) 9962{ 9963 /* guarantee we can provide a unique filter for the unicast address */ 9964 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 9965 struct ixgbe_adapter *adapter = netdev_priv(dev); 9966 u16 pool = VMDQ_P(0); 9967 9968 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 9969 return -ENOMEM; 9970 } 9971 9972 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 9973} 9974 9975/** 9976 * ixgbe_configure_bridge_mode - set various bridge modes 9977 * @adapter: the private structure 9978 * @mode: requested bridge mode 9979 * 9980 * Configure some settings require for various bridge modes. 9981 **/ 9982static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 9983 __u16 mode) 9984{ 9985 struct ixgbe_hw *hw = &adapter->hw; 9986 unsigned int p, num_pools; 9987 u32 vmdctl; 9988 9989 switch (mode) { 9990 case BRIDGE_MODE_VEPA: 9991 /* disable Tx loopback, rely on switch hairpin mode */ 9992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 9993 9994 /* must enable Rx switching replication to allow multicast 9995 * packet reception on all VFs, and to enable source address 9996 * pruning. 9997 */ 9998 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 9999 vmdctl |= IXGBE_VT_CTL_REPLEN; 10000 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10001 10002 /* enable Rx source address pruning. Note, this requires 10003 * replication to be enabled or else it does nothing. 10004 */ 10005 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10006 for (p = 0; p < num_pools; p++) { 10007 if (hw->mac.ops.set_source_address_pruning) 10008 hw->mac.ops.set_source_address_pruning(hw, 10009 true, 10010 p); 10011 } 10012 break; 10013 case BRIDGE_MODE_VEB: 10014 /* enable Tx loopback for internal VF/PF communication */ 10015 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 10016 IXGBE_PFDTXGSWC_VT_LBEN); 10017 10018 /* disable Rx switching replication unless we have SR-IOV 10019 * virtual functions 10020 */ 10021 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10022 if (!adapter->num_vfs) 10023 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 10024 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10025 10026 /* disable Rx source address pruning, since we don't expect to 10027 * be receiving external loopback of our transmitted frames. 10028 */ 10029 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10030 for (p = 0; p < num_pools; p++) { 10031 if (hw->mac.ops.set_source_address_pruning) 10032 hw->mac.ops.set_source_address_pruning(hw, 10033 false, 10034 p); 10035 } 10036 break; 10037 default: 10038 return -EINVAL; 10039 } 10040 10041 adapter->bridge_mode = mode; 10042 10043 e_info(drv, "enabling bridge mode: %s\n", 10044 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10045 10046 return 0; 10047} 10048 10049static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10050 struct nlmsghdr *nlh, u16 flags, 10051 struct netlink_ext_ack *extack) 10052{ 10053 struct ixgbe_adapter *adapter = netdev_priv(dev); 10054 struct nlattr *attr, *br_spec; 10055 int rem; 10056 10057 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10058 return -EOPNOTSUPP; 10059 10060 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10061 if (!br_spec) 10062 return -EINVAL; 10063 10064 nla_for_each_nested(attr, br_spec, rem) { 10065 int status; 10066 __u16 mode; 10067 10068 if (nla_type(attr) != IFLA_BRIDGE_MODE) 10069 continue; 10070 10071 mode = nla_get_u16(attr); 10072 status = ixgbe_configure_bridge_mode(adapter, mode); 10073 if (status) 10074 return status; 10075 10076 break; 10077 } 10078 10079 return 0; 10080} 10081 10082static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10083 struct net_device *dev, 10084 u32 filter_mask, int nlflags) 10085{ 10086 struct ixgbe_adapter *adapter = netdev_priv(dev); 10087 10088 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10089 return 0; 10090 10091 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10092 adapter->bridge_mode, 0, 0, nlflags, 10093 filter_mask, NULL); 10094} 10095 10096static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10097{ 10098 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10099 struct ixgbe_fwd_adapter *accel; 10100 int tcs = adapter->hw_tcs ? : 1; 10101 int pool, err; 10102 10103 if (adapter->xdp_prog) { 10104 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10105 return ERR_PTR(-EINVAL); 10106 } 10107 10108 /* The hardware supported by ixgbe only filters on the destination MAC 10109 * address. In order to avoid issues we only support offloading modes 10110 * where the hardware can actually provide the functionality. 10111 */ 10112 if (!macvlan_supports_dest_filter(vdev)) 10113 return ERR_PTR(-EMEDIUMTYPE); 10114 10115 /* We need to lock down the macvlan to be a single queue device so that 10116 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10117 * the queue mapping to our netdev. 10118 */ 10119 if (netif_is_multiqueue(vdev)) 10120 return ERR_PTR(-ERANGE); 10121 10122 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10123 if (pool == adapter->num_rx_pools) { 10124 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10125 u16 reserved_pools; 10126 10127 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10128 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10129 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10130 return ERR_PTR(-EBUSY); 10131 10132 /* Hardware has a limited number of available pools. Each VF, 10133 * and the PF require a pool. Check to ensure we don't 10134 * attempt to use more then the available number of pools. 10135 */ 10136 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10137 return ERR_PTR(-EBUSY); 10138 10139 /* Enable VMDq flag so device will be set in VM mode */ 10140 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10141 IXGBE_FLAG_SRIOV_ENABLED; 10142 10143 /* Try to reserve as many queues per pool as possible, 10144 * we start with the configurations that support 4 queues 10145 * per pools, followed by 2, and then by just 1 per pool. 10146 */ 10147 if (used_pools < 32 && adapter->num_rx_pools < 16) 10148 reserved_pools = min_t(u16, 10149 32 - used_pools, 10150 16 - adapter->num_rx_pools); 10151 else if (adapter->num_rx_pools < 32) 10152 reserved_pools = min_t(u16, 10153 64 - used_pools, 10154 32 - adapter->num_rx_pools); 10155 else 10156 reserved_pools = 64 - used_pools; 10157 10158 10159 if (!reserved_pools) 10160 return ERR_PTR(-EBUSY); 10161 10162 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10163 10164 /* Force reinit of ring allocation with VMDQ enabled */ 10165 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10166 if (err) 10167 return ERR_PTR(err); 10168 10169 if (pool >= adapter->num_rx_pools) 10170 return ERR_PTR(-ENOMEM); 10171 } 10172 10173 accel = kzalloc(sizeof(*accel), GFP_KERNEL); 10174 if (!accel) 10175 return ERR_PTR(-ENOMEM); 10176 10177 set_bit(pool, adapter->fwd_bitmask); 10178 netdev_set_sb_channel(vdev, pool); 10179 accel->pool = pool; 10180 accel->netdev = vdev; 10181 10182 if (!netif_running(pdev)) 10183 return accel; 10184 10185 err = ixgbe_fwd_ring_up(adapter, accel); 10186 if (err) 10187 return ERR_PTR(err); 10188 10189 return accel; 10190} 10191 10192static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10193{ 10194 struct ixgbe_fwd_adapter *accel = priv; 10195 struct ixgbe_adapter *adapter = netdev_priv(pdev); 10196 unsigned int rxbase = accel->rx_base_queue; 10197 unsigned int i; 10198 10199 /* delete unicast filter associated with offloaded interface */ 10200 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10201 VMDQ_P(accel->pool)); 10202 10203 /* Allow remaining Rx packets to get flushed out of the 10204 * Rx FIFO before we drop the netdev for the ring. 10205 */ 10206 usleep_range(10000, 20000); 10207 10208 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10209 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10210 struct ixgbe_q_vector *qv = ring->q_vector; 10211 10212 /* Make sure we aren't processing any packets and clear 10213 * netdev to shut down the ring. 10214 */ 10215 if (netif_running(adapter->netdev)) 10216 napi_synchronize(&qv->napi); 10217 ring->netdev = NULL; 10218 } 10219 10220 /* unbind the queues and drop the subordinate channel config */ 10221 netdev_unbind_sb_channel(pdev, accel->netdev); 10222 netdev_set_sb_channel(accel->netdev, 0); 10223 10224 clear_bit(accel->pool, adapter->fwd_bitmask); 10225 kfree(accel); 10226} 10227 10228#define IXGBE_MAX_MAC_HDR_LEN 127 10229#define IXGBE_MAX_NETWORK_HDR_LEN 511 10230 10231static netdev_features_t 10232ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10233 netdev_features_t features) 10234{ 10235 unsigned int network_hdr_len, mac_hdr_len; 10236 10237 /* Make certain the headers can be described by a context descriptor */ 10238 mac_hdr_len = skb_network_offset(skb); 10239 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10240 return features & ~(NETIF_F_HW_CSUM | 10241 NETIF_F_SCTP_CRC | 10242 NETIF_F_GSO_UDP_L4 | 10243 NETIF_F_HW_VLAN_CTAG_TX | 10244 NETIF_F_TSO | 10245 NETIF_F_TSO6); 10246 10247 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10248 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10249 return features & ~(NETIF_F_HW_CSUM | 10250 NETIF_F_SCTP_CRC | 10251 NETIF_F_GSO_UDP_L4 | 10252 NETIF_F_TSO | 10253 NETIF_F_TSO6); 10254 10255 /* We can only support IPV4 TSO in tunnels if we can mangle the 10256 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10257 * IPsec offoad sets skb->encapsulation but still can handle 10258 * the TSO, so it's the exception. 10259 */ 10260 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10261#ifdef CONFIG_IXGBE_IPSEC 10262 if (!secpath_exists(skb)) 10263#endif 10264 features &= ~NETIF_F_TSO; 10265 } 10266 10267 return features; 10268} 10269 10270static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10271{ 10272 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10273 struct ixgbe_adapter *adapter = netdev_priv(dev); 10274 struct bpf_prog *old_prog; 10275 bool need_reset; 10276 int num_queues; 10277 10278 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10279 return -EINVAL; 10280 10281 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10282 return -EINVAL; 10283 10284 /* verify ixgbe ring attributes are sufficient for XDP */ 10285 for (i = 0; i < adapter->num_rx_queues; i++) { 10286 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10287 10288 if (ring_is_rsc_enabled(ring)) 10289 return -EINVAL; 10290 10291 if (frame_size > ixgbe_rx_bufsz(ring)) 10292 return -EINVAL; 10293 } 10294 10295 /* if the number of cpus is much larger than the maximum of queues, 10296 * we should stop it and then return with ENOMEM like before. 10297 */ 10298 if (nr_cpu_ids > IXGBE_MAX_XDP_QS * 2) 10299 return -ENOMEM; 10300 10301 old_prog = xchg(&adapter->xdp_prog, prog); 10302 need_reset = (!!prog != !!old_prog); 10303 10304 /* If transitioning XDP modes reconfigure rings */ 10305 if (need_reset) { 10306 int err; 10307 10308 if (!prog) 10309 /* Wait until ndo_xsk_wakeup completes. */ 10310 synchronize_rcu(); 10311 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10312 10313 if (err) 10314 return -EINVAL; 10315 if (!prog) 10316 xdp_features_clear_redirect_target(dev); 10317 } else { 10318 for (i = 0; i < adapter->num_rx_queues; i++) { 10319 WRITE_ONCE(adapter->rx_ring[i]->xdp_prog, 10320 adapter->xdp_prog); 10321 } 10322 } 10323 10324 if (old_prog) 10325 bpf_prog_put(old_prog); 10326 10327 /* Kick start the NAPI context if there is an AF_XDP socket open 10328 * on that queue id. This so that receiving will start. 10329 */ 10330 if (need_reset && prog) { 10331 num_queues = min_t(int, adapter->num_rx_queues, 10332 adapter->num_xdp_queues); 10333 for (i = 0; i < num_queues; i++) 10334 if (adapter->xdp_ring[i]->xsk_pool) 10335 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10336 XDP_WAKEUP_RX); 10337 xdp_features_set_redirect_target(dev, true); 10338 } 10339 10340 return 0; 10341} 10342 10343static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10344{ 10345 struct ixgbe_adapter *adapter = netdev_priv(dev); 10346 10347 switch (xdp->command) { 10348 case XDP_SETUP_PROG: 10349 return ixgbe_xdp_setup(dev, xdp->prog); 10350 case XDP_SETUP_XSK_POOL: 10351 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10352 xdp->xsk.queue_id); 10353 10354 default: 10355 return -EINVAL; 10356 } 10357} 10358 10359void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 10360{ 10361 /* Force memory writes to complete before letting h/w know there 10362 * are new descriptors to fetch. 10363 */ 10364 wmb(); 10365 writel(ring->next_to_use, ring->tail); 10366} 10367 10368void ixgbe_xdp_ring_update_tail_locked(struct ixgbe_ring *ring) 10369{ 10370 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10371 spin_lock(&ring->tx_lock); 10372 ixgbe_xdp_ring_update_tail(ring); 10373 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10374 spin_unlock(&ring->tx_lock); 10375} 10376 10377static int ixgbe_xdp_xmit(struct net_device *dev, int n, 10378 struct xdp_frame **frames, u32 flags) 10379{ 10380 struct ixgbe_adapter *adapter = netdev_priv(dev); 10381 struct ixgbe_ring *ring; 10382 int nxmit = 0; 10383 int i; 10384 10385 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 10386 return -ENETDOWN; 10387 10388 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 10389 return -EINVAL; 10390 10391 /* During program transitions its possible adapter->xdp_prog is assigned 10392 * but ring has not been configured yet. In this case simply abort xmit. 10393 */ 10394 ring = adapter->xdp_prog ? ixgbe_determine_xdp_ring(adapter) : NULL; 10395 if (unlikely(!ring)) 10396 return -ENXIO; 10397 10398 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state))) 10399 return -ENXIO; 10400 10401 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10402 spin_lock(&ring->tx_lock); 10403 10404 for (i = 0; i < n; i++) { 10405 struct xdp_frame *xdpf = frames[i]; 10406 int err; 10407 10408 err = ixgbe_xmit_xdp_ring(ring, xdpf); 10409 if (err != IXGBE_XDP_TX) 10410 break; 10411 nxmit++; 10412 } 10413 10414 if (unlikely(flags & XDP_XMIT_FLUSH)) 10415 ixgbe_xdp_ring_update_tail(ring); 10416 10417 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 10418 spin_unlock(&ring->tx_lock); 10419 10420 return nxmit; 10421} 10422 10423static const struct net_device_ops ixgbe_netdev_ops = { 10424 .ndo_open = ixgbe_open, 10425 .ndo_stop = ixgbe_close, 10426 .ndo_start_xmit = ixgbe_xmit_frame, 10427 .ndo_set_rx_mode = ixgbe_set_rx_mode, 10428 .ndo_validate_addr = eth_validate_addr, 10429 .ndo_set_mac_address = ixgbe_set_mac, 10430 .ndo_change_mtu = ixgbe_change_mtu, 10431 .ndo_tx_timeout = ixgbe_tx_timeout, 10432 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 10433 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 10434 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 10435 .ndo_eth_ioctl = ixgbe_ioctl, 10436 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 10437 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 10438 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 10439 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 10440 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state, 10441 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 10442 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 10443 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 10444 .ndo_get_vf_stats = ixgbe_ndo_get_vf_stats, 10445 .ndo_get_stats64 = ixgbe_get_stats64, 10446 .ndo_setup_tc = __ixgbe_setup_tc, 10447#ifdef IXGBE_FCOE 10448 .ndo_select_queue = ixgbe_select_queue, 10449 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 10450 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 10451 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 10452 .ndo_fcoe_enable = ixgbe_fcoe_enable, 10453 .ndo_fcoe_disable = ixgbe_fcoe_disable, 10454 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 10455 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 10456#endif /* IXGBE_FCOE */ 10457 .ndo_set_features = ixgbe_set_features, 10458 .ndo_fix_features = ixgbe_fix_features, 10459 .ndo_fdb_add = ixgbe_ndo_fdb_add, 10460 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 10461 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 10462 .ndo_dfwd_add_station = ixgbe_fwd_add, 10463 .ndo_dfwd_del_station = ixgbe_fwd_del, 10464 .ndo_features_check = ixgbe_features_check, 10465 .ndo_bpf = ixgbe_xdp, 10466 .ndo_xdp_xmit = ixgbe_xdp_xmit, 10467 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 10468}; 10469 10470static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 10471 struct ixgbe_ring *tx_ring) 10472{ 10473 unsigned long wait_delay, delay_interval; 10474 struct ixgbe_hw *hw = &adapter->hw; 10475 u8 reg_idx = tx_ring->reg_idx; 10476 int wait_loop; 10477 u32 txdctl; 10478 10479 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 10480 10481 /* delay mechanism from ixgbe_disable_tx */ 10482 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10483 10484 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10485 wait_delay = delay_interval; 10486 10487 while (wait_loop--) { 10488 usleep_range(wait_delay, wait_delay + 10); 10489 wait_delay += delay_interval * 2; 10490 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 10491 10492 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 10493 return; 10494 } 10495 10496 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 10497} 10498 10499static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 10500 struct ixgbe_ring *tx_ring) 10501{ 10502 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10503 ixgbe_disable_txr_hw(adapter, tx_ring); 10504} 10505 10506static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 10507 struct ixgbe_ring *rx_ring) 10508{ 10509 unsigned long wait_delay, delay_interval; 10510 struct ixgbe_hw *hw = &adapter->hw; 10511 u8 reg_idx = rx_ring->reg_idx; 10512 int wait_loop; 10513 u32 rxdctl; 10514 10515 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10516 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 10517 rxdctl |= IXGBE_RXDCTL_SWFLSH; 10518 10519 /* write value back with RXDCTL.ENABLE bit cleared */ 10520 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 10521 10522 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 10523 if (hw->mac.type == ixgbe_mac_82598EB && 10524 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 10525 return; 10526 10527 /* delay mechanism from ixgbe_disable_rx */ 10528 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 10529 10530 wait_loop = IXGBE_MAX_RX_DESC_POLL; 10531 wait_delay = delay_interval; 10532 10533 while (wait_loop--) { 10534 usleep_range(wait_delay, wait_delay + 10); 10535 wait_delay += delay_interval * 2; 10536 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 10537 10538 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 10539 return; 10540 } 10541 10542 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 10543} 10544 10545static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 10546{ 10547 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 10548 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 10549} 10550 10551static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 10552{ 10553 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 10554 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 10555} 10556 10557/** 10558 * ixgbe_irq_disable_single - Disable single IRQ vector 10559 * @adapter: adapter structure 10560 * @ring: ring index 10561 **/ 10562static void ixgbe_irq_disable_single(struct ixgbe_adapter *adapter, u32 ring) 10563{ 10564 struct ixgbe_hw *hw = &adapter->hw; 10565 u64 qmask = BIT_ULL(ring); 10566 u32 mask; 10567 10568 switch (adapter->hw.mac.type) { 10569 case ixgbe_mac_82598EB: 10570 mask = qmask & IXGBE_EIMC_RTX_QUEUE; 10571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); 10572 break; 10573 case ixgbe_mac_82599EB: 10574 case ixgbe_mac_X540: 10575 case ixgbe_mac_X550: 10576 case ixgbe_mac_X550EM_x: 10577 case ixgbe_mac_x550em_a: 10578 mask = (qmask & 0xFFFFFFFF); 10579 if (mask) 10580 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 10581 mask = (qmask >> 32); 10582 if (mask) 10583 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 10584 break; 10585 default: 10586 break; 10587 } 10588 IXGBE_WRITE_FLUSH(&adapter->hw); 10589 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 10590 synchronize_irq(adapter->msix_entries[ring].vector); 10591 else 10592 synchronize_irq(adapter->pdev->irq); 10593} 10594 10595/** 10596 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 10597 * @adapter: adapter structure 10598 * @ring: ring index 10599 * 10600 * This function disables a certain Rx/Tx/XDP Tx ring. The function 10601 * assumes that the netdev is running. 10602 **/ 10603void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 10604{ 10605 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10606 10607 rx_ring = adapter->rx_ring[ring]; 10608 tx_ring = adapter->tx_ring[ring]; 10609 xdp_ring = adapter->xdp_ring[ring]; 10610 10611 ixgbe_irq_disable_single(adapter, ring); 10612 10613 /* Rx/Tx/XDP Tx share the same napi context. */ 10614 napi_disable(&rx_ring->q_vector->napi); 10615 10616 ixgbe_disable_txr(adapter, tx_ring); 10617 if (xdp_ring) 10618 ixgbe_disable_txr(adapter, xdp_ring); 10619 ixgbe_disable_rxr_hw(adapter, rx_ring); 10620 10621 if (xdp_ring) 10622 synchronize_rcu(); 10623 10624 ixgbe_clean_tx_ring(tx_ring); 10625 if (xdp_ring) 10626 ixgbe_clean_tx_ring(xdp_ring); 10627 ixgbe_clean_rx_ring(rx_ring); 10628 10629 ixgbe_reset_txr_stats(tx_ring); 10630 if (xdp_ring) 10631 ixgbe_reset_txr_stats(xdp_ring); 10632 ixgbe_reset_rxr_stats(rx_ring); 10633} 10634 10635/** 10636 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 10637 * @adapter: adapter structure 10638 * @ring: ring index 10639 * 10640 * This function enables a certain Rx/Tx/XDP Tx ring. The function 10641 * assumes that the netdev is running. 10642 **/ 10643void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 10644{ 10645 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 10646 10647 rx_ring = adapter->rx_ring[ring]; 10648 tx_ring = adapter->tx_ring[ring]; 10649 xdp_ring = adapter->xdp_ring[ring]; 10650 10651 ixgbe_configure_tx_ring(adapter, tx_ring); 10652 if (xdp_ring) 10653 ixgbe_configure_tx_ring(adapter, xdp_ring); 10654 ixgbe_configure_rx_ring(adapter, rx_ring); 10655 10656 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state); 10657 if (xdp_ring) 10658 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state); 10659 10660 /* Rx/Tx/XDP Tx share the same napi context. */ 10661 napi_enable(&rx_ring->q_vector->napi); 10662 ixgbe_irq_enable_queues(adapter, BIT_ULL(ring)); 10663 IXGBE_WRITE_FLUSH(&adapter->hw); 10664} 10665 10666/** 10667 * ixgbe_enumerate_functions - Get the number of ports this device has 10668 * @adapter: adapter structure 10669 * 10670 * This function enumerates the phsyical functions co-located on a single slot, 10671 * in order to determine how many ports a device has. This is most useful in 10672 * determining the required GT/s of PCIe bandwidth necessary for optimal 10673 * performance. 10674 **/ 10675static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 10676{ 10677 struct pci_dev *entry, *pdev = adapter->pdev; 10678 int physfns = 0; 10679 10680 /* Some cards can not use the generic count PCIe functions method, 10681 * because they are behind a parent switch, so we hardcode these with 10682 * the correct number of functions. 10683 */ 10684 if (ixgbe_pcie_from_parent(&adapter->hw)) 10685 physfns = 4; 10686 10687 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 10688 /* don't count virtual functions */ 10689 if (entry->is_virtfn) 10690 continue; 10691 10692 /* When the devices on the bus don't all match our device ID, 10693 * we can't reliably determine the correct number of 10694 * functions. This can occur if a function has been direct 10695 * attached to a virtual machine using VT-d, for example. In 10696 * this case, simply return -1 to indicate this. 10697 */ 10698 if ((entry->vendor != pdev->vendor) || 10699 (entry->device != pdev->device)) 10700 return -1; 10701 10702 physfns++; 10703 } 10704 10705 return physfns; 10706} 10707 10708/** 10709 * ixgbe_wol_supported - Check whether device supports WoL 10710 * @adapter: the adapter private structure 10711 * @device_id: the device ID 10712 * @subdevice_id: the subsystem device ID 10713 * 10714 * This function is used by probe and ethtool to determine 10715 * which devices have WoL support 10716 * 10717 **/ 10718bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 10719 u16 subdevice_id) 10720{ 10721 struct ixgbe_hw *hw = &adapter->hw; 10722 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 10723 10724 /* WOL not supported on 82598 */ 10725 if (hw->mac.type == ixgbe_mac_82598EB) 10726 return false; 10727 10728 /* check eeprom to see if WOL is enabled for X540 and newer */ 10729 if (hw->mac.type >= ixgbe_mac_X540) { 10730 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 10731 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 10732 (hw->bus.func == 0))) 10733 return true; 10734 } 10735 10736 /* WOL is determined based on device IDs for 82599 MACs */ 10737 switch (device_id) { 10738 case IXGBE_DEV_ID_82599_SFP: 10739 /* Only these subdevices could supports WOL */ 10740 switch (subdevice_id) { 10741 case IXGBE_SUBDEV_ID_82599_560FLR: 10742 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 10743 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 10744 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 10745 /* only support first port */ 10746 if (hw->bus.func != 0) 10747 break; 10748 fallthrough; 10749 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 10750 case IXGBE_SUBDEV_ID_82599_SFP: 10751 case IXGBE_SUBDEV_ID_82599_RNDC: 10752 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 10753 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 10754 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 10755 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 10756 return true; 10757 } 10758 break; 10759 case IXGBE_DEV_ID_82599EN_SFP: 10760 /* Only these subdevices support WOL */ 10761 switch (subdevice_id) { 10762 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 10763 return true; 10764 } 10765 break; 10766 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 10767 /* All except this subdevice support WOL */ 10768 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 10769 return true; 10770 break; 10771 case IXGBE_DEV_ID_82599_KX4: 10772 return true; 10773 default: 10774 break; 10775 } 10776 10777 return false; 10778} 10779 10780/** 10781 * ixgbe_set_fw_version - Set FW version 10782 * @adapter: the adapter private structure 10783 * 10784 * This function is used by probe and ethtool to determine the FW version to 10785 * format to display. The FW version is taken from the EEPROM/NVM. 10786 */ 10787static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 10788{ 10789 struct ixgbe_hw *hw = &adapter->hw; 10790 struct ixgbe_nvm_version nvm_ver; 10791 10792 ixgbe_get_oem_prod_version(hw, &nvm_ver); 10793 if (nvm_ver.oem_valid) { 10794 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10795 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 10796 nvm_ver.oem_release); 10797 return; 10798 } 10799 10800 ixgbe_get_etk_id(hw, &nvm_ver); 10801 ixgbe_get_orom_version(hw, &nvm_ver); 10802 10803 if (nvm_ver.or_valid) { 10804 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10805 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 10806 nvm_ver.or_build, nvm_ver.or_patch); 10807 return; 10808 } 10809 10810 /* Set ETrack ID format */ 10811 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 10812 "0x%08x", nvm_ver.etk_id); 10813} 10814 10815/** 10816 * ixgbe_probe - Device Initialization Routine 10817 * @pdev: PCI device information struct 10818 * @ent: entry in ixgbe_pci_tbl 10819 * 10820 * Returns 0 on success, negative on failure 10821 * 10822 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 10823 * The OS initialization, configuring of the adapter private structure, 10824 * and a hardware reset occur. 10825 **/ 10826static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 10827{ 10828 struct net_device *netdev; 10829 struct ixgbe_adapter *adapter = NULL; 10830 struct ixgbe_hw *hw; 10831 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 10832 unsigned int indices = MAX_TX_QUEUES; 10833 u8 part_str[IXGBE_PBANUM_LENGTH]; 10834 int i, err, expected_gts; 10835 bool disable_dev = false; 10836#ifdef IXGBE_FCOE 10837 u16 device_caps; 10838#endif 10839 u32 eec; 10840 10841 /* Catch broken hardware that put the wrong VF device ID in 10842 * the PCIe SR-IOV capability. 10843 */ 10844 if (pdev->is_virtfn) { 10845 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 10846 pci_name(pdev), pdev->vendor, pdev->device); 10847 return -EINVAL; 10848 } 10849 10850 err = pci_enable_device_mem(pdev); 10851 if (err) 10852 return err; 10853 10854 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 10855 if (err) { 10856 dev_err(&pdev->dev, 10857 "No usable DMA configuration, aborting\n"); 10858 goto err_dma; 10859 } 10860 10861 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 10862 if (err) { 10863 dev_err(&pdev->dev, 10864 "pci_request_selected_regions failed 0x%x\n", err); 10865 goto err_pci_reg; 10866 } 10867 10868 pci_set_master(pdev); 10869 pci_save_state(pdev); 10870 10871 if (ii->mac == ixgbe_mac_82598EB) { 10872#ifdef CONFIG_IXGBE_DCB 10873 /* 8 TC w/ 4 queues per TC */ 10874 indices = 4 * MAX_TRAFFIC_CLASS; 10875#else 10876 indices = IXGBE_MAX_RSS_INDICES; 10877#endif 10878 } 10879 10880 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); 10881 if (!netdev) { 10882 err = -ENOMEM; 10883 goto err_alloc_etherdev; 10884 } 10885 10886 SET_NETDEV_DEV(netdev, &pdev->dev); 10887 10888 adapter = netdev_priv(netdev); 10889 10890 adapter->netdev = netdev; 10891 adapter->pdev = pdev; 10892 hw = &adapter->hw; 10893 hw->back = adapter; 10894 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 10895 10896 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 10897 pci_resource_len(pdev, 0)); 10898 adapter->io_addr = hw->hw_addr; 10899 if (!hw->hw_addr) { 10900 err = -EIO; 10901 goto err_ioremap; 10902 } 10903 10904 netdev->netdev_ops = &ixgbe_netdev_ops; 10905 ixgbe_set_ethtool_ops(netdev); 10906 netdev->watchdog_timeo = 5 * HZ; 10907 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 10908 10909 /* Setup hw api */ 10910 hw->mac.ops = *ii->mac_ops; 10911 hw->mac.type = ii->mac; 10912 hw->mvals = ii->mvals; 10913 if (ii->link_ops) 10914 hw->link.ops = *ii->link_ops; 10915 10916 /* EEPROM */ 10917 hw->eeprom.ops = *ii->eeprom_ops; 10918 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 10919 if (ixgbe_removed(hw->hw_addr)) { 10920 err = -EIO; 10921 goto err_ioremap; 10922 } 10923 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 10924 if (!(eec & BIT(8))) 10925 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 10926 10927 /* PHY */ 10928 hw->phy.ops = *ii->phy_ops; 10929 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 10930 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 10931 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 10932 hw->phy.mdio.mmds = 0; 10933 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 10934 hw->phy.mdio.dev = netdev; 10935 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 10936 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 10937 10938 /* setup the private structure */ 10939 err = ixgbe_sw_init(adapter, ii); 10940 if (err) 10941 goto err_sw_init; 10942 10943 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 10944 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 10945 10946 switch (adapter->hw.mac.type) { 10947 case ixgbe_mac_X550: 10948 case ixgbe_mac_X550EM_x: 10949 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 10950 break; 10951 case ixgbe_mac_x550em_a: 10952 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 10953 break; 10954 default: 10955 break; 10956 } 10957 10958 /* Make sure the SWFW semaphore is in a valid state */ 10959 if (hw->mac.ops.init_swfw_sync) 10960 hw->mac.ops.init_swfw_sync(hw); 10961 10962 /* Make it possible the adapter to be woken up via WOL */ 10963 switch (adapter->hw.mac.type) { 10964 case ixgbe_mac_82599EB: 10965 case ixgbe_mac_X540: 10966 case ixgbe_mac_X550: 10967 case ixgbe_mac_X550EM_x: 10968 case ixgbe_mac_x550em_a: 10969 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 10970 break; 10971 default: 10972 break; 10973 } 10974 10975 /* 10976 * If there is a fan on this device and it has failed log the 10977 * failure. 10978 */ 10979 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 10980 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 10981 if (esdp & IXGBE_ESDP_SDP1) 10982 e_crit(probe, "Fan has stopped, replace the adapter\n"); 10983 } 10984 10985 if (allow_unsupported_sfp) 10986 hw->allow_unsupported_sfp = allow_unsupported_sfp; 10987 10988 /* reset_hw fills in the perm_addr as well */ 10989 hw->phy.reset_if_overtemp = true; 10990 err = hw->mac.ops.reset_hw(hw); 10991 hw->phy.reset_if_overtemp = false; 10992 ixgbe_set_eee_capable(adapter); 10993 if (err == -ENOENT) { 10994 err = 0; 10995 } else if (err == -EOPNOTSUPP) { 10996 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 10997 e_dev_err("Reload the driver after installing a supported module.\n"); 10998 goto err_sw_init; 10999 } else if (err) { 11000 e_dev_err("HW Init failed: %d\n", err); 11001 goto err_sw_init; 11002 } 11003 11004#ifdef CONFIG_PCI_IOV 11005 /* SR-IOV not supported on the 82598 */ 11006 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 11007 goto skip_sriov; 11008 /* Mailbox */ 11009 ixgbe_init_mbx_params_pf(hw); 11010 hw->mbx.ops = ii->mbx_ops; 11011 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 11012 ixgbe_enable_sriov(adapter, max_vfs); 11013skip_sriov: 11014 11015#endif 11016 netdev->features = NETIF_F_SG | 11017 NETIF_F_TSO | 11018 NETIF_F_TSO6 | 11019 NETIF_F_RXHASH | 11020 NETIF_F_RXCSUM | 11021 NETIF_F_HW_CSUM; 11022 11023#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 11024 NETIF_F_GSO_GRE_CSUM | \ 11025 NETIF_F_GSO_IPXIP4 | \ 11026 NETIF_F_GSO_IPXIP6 | \ 11027 NETIF_F_GSO_UDP_TUNNEL | \ 11028 NETIF_F_GSO_UDP_TUNNEL_CSUM) 11029 11030 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 11031 netdev->features |= NETIF_F_GSO_PARTIAL | 11032 IXGBE_GSO_PARTIAL_FEATURES; 11033 11034 if (hw->mac.type >= ixgbe_mac_82599EB) 11035 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 11036 11037#ifdef CONFIG_IXGBE_IPSEC 11038#define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 11039 NETIF_F_HW_ESP_TX_CSUM | \ 11040 NETIF_F_GSO_ESP) 11041 11042 if (adapter->ipsec) 11043 netdev->features |= IXGBE_ESP_FEATURES; 11044#endif 11045 /* copy netdev features into list of user selectable features */ 11046 netdev->hw_features |= netdev->features | 11047 NETIF_F_HW_VLAN_CTAG_FILTER | 11048 NETIF_F_HW_VLAN_CTAG_RX | 11049 NETIF_F_HW_VLAN_CTAG_TX | 11050 NETIF_F_RXALL | 11051 NETIF_F_HW_L2FW_DOFFLOAD; 11052 11053 if (hw->mac.type >= ixgbe_mac_82599EB) 11054 netdev->hw_features |= NETIF_F_NTUPLE | 11055 NETIF_F_HW_TC; 11056 11057 netdev->features |= NETIF_F_HIGHDMA; 11058 11059 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 11060 netdev->hw_enc_features |= netdev->vlan_features; 11061 netdev->mpls_features |= NETIF_F_SG | 11062 NETIF_F_TSO | 11063 NETIF_F_TSO6 | 11064 NETIF_F_HW_CSUM; 11065 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 11066 11067 /* set this bit last since it cannot be part of vlan_features */ 11068 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 11069 NETIF_F_HW_VLAN_CTAG_RX | 11070 NETIF_F_HW_VLAN_CTAG_TX; 11071 11072 netdev->priv_flags |= IFF_UNICAST_FLT; 11073 netdev->priv_flags |= IFF_SUPP_NOFCS; 11074 11075 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 11076 NETDEV_XDP_ACT_XSK_ZEROCOPY; 11077 11078 /* MTU range: 68 - 9710 */ 11079 netdev->min_mtu = ETH_MIN_MTU; 11080 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 11081 11082#ifdef CONFIG_IXGBE_DCB 11083 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 11084 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 11085#endif 11086 11087#ifdef IXGBE_FCOE 11088 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 11089 unsigned int fcoe_l; 11090 11091 if (hw->mac.ops.get_device_caps) { 11092 hw->mac.ops.get_device_caps(hw, &device_caps); 11093 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 11094 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 11095 } 11096 11097 11098 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 11099 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 11100 11101 netdev->features |= NETIF_F_FSO | 11102 NETIF_F_FCOE_CRC; 11103 11104 netdev->vlan_features |= NETIF_F_FSO | 11105 NETIF_F_FCOE_CRC | 11106 NETIF_F_FCOE_MTU; 11107 } 11108#endif /* IXGBE_FCOE */ 11109 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 11110 netdev->hw_features |= NETIF_F_LRO; 11111 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 11112 netdev->features |= NETIF_F_LRO; 11113 11114 if (ixgbe_check_fw_error(adapter)) { 11115 err = -EIO; 11116 goto err_sw_init; 11117 } 11118 11119 /* make sure the EEPROM is good */ 11120 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11121 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11122 err = -EIO; 11123 goto err_sw_init; 11124 } 11125 11126 eth_platform_get_mac_address(&adapter->pdev->dev, 11127 adapter->hw.mac.perm_addr); 11128 11129 eth_hw_addr_set(netdev, hw->mac.perm_addr); 11130 11131 if (!is_valid_ether_addr(netdev->dev_addr)) { 11132 e_dev_err("invalid MAC address\n"); 11133 err = -EIO; 11134 goto err_sw_init; 11135 } 11136 11137 /* Set hw->mac.addr to permanent MAC address */ 11138 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11139 ixgbe_mac_set_default_filter(adapter); 11140 11141 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11142 11143 if (ixgbe_removed(hw->hw_addr)) { 11144 err = -EIO; 11145 goto err_sw_init; 11146 } 11147 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11148 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11149 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11150 11151 err = ixgbe_init_interrupt_scheme(adapter); 11152 if (err) 11153 goto err_sw_init; 11154 11155 for (i = 0; i < adapter->num_rx_queues; i++) 11156 u64_stats_init(&adapter->rx_ring[i]->syncp); 11157 for (i = 0; i < adapter->num_tx_queues; i++) 11158 u64_stats_init(&adapter->tx_ring[i]->syncp); 11159 for (i = 0; i < adapter->num_xdp_queues; i++) 11160 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11161 11162 /* WOL not supported for all devices */ 11163 adapter->wol = 0; 11164 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11165 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11166 pdev->subsystem_device); 11167 if (hw->wol_enabled) 11168 adapter->wol = IXGBE_WUFC_MAG; 11169 11170 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11171 11172 /* save off EEPROM version number */ 11173 ixgbe_set_fw_version(adapter); 11174 11175 /* pick up the PCI bus settings for reporting later */ 11176 if (ixgbe_pcie_from_parent(hw)) 11177 ixgbe_get_parent_bus_info(adapter); 11178 else 11179 hw->mac.ops.get_bus_info(hw); 11180 11181 /* calculate the expected PCIe bandwidth required for optimal 11182 * performance. Note that some older parts will never have enough 11183 * bandwidth due to being older generation PCIe parts. We clamp these 11184 * parts to ensure no warning is displayed if it can't be fixed. 11185 */ 11186 switch (hw->mac.type) { 11187 case ixgbe_mac_82598EB: 11188 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11189 break; 11190 default: 11191 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11192 break; 11193 } 11194 11195 /* don't check link if we failed to enumerate functions */ 11196 if (expected_gts > 0) 11197 ixgbe_check_minimum_link(adapter, expected_gts); 11198 11199 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); 11200 if (err) 11201 strscpy(part_str, "Unknown", sizeof(part_str)); 11202 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11203 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11204 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11205 part_str); 11206 else 11207 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11208 hw->mac.type, hw->phy.type, part_str); 11209 11210 e_dev_info("%pM\n", netdev->dev_addr); 11211 11212 /* reset the hardware with the new settings */ 11213 err = hw->mac.ops.start_hw(hw); 11214 if (err == -EACCES) { 11215 /* We are running on a pre-production device, log a warning */ 11216 e_dev_warn("This device is a pre-production adapter/LOM. " 11217 "Please be aware there may be issues associated " 11218 "with your hardware. If you are experiencing " 11219 "problems please contact your Intel or hardware " 11220 "representative who provided you with this " 11221 "hardware.\n"); 11222 } 11223 strcpy(netdev->name, "eth%d"); 11224 pci_set_drvdata(pdev, adapter); 11225 err = register_netdev(netdev); 11226 if (err) 11227 goto err_register; 11228 11229 11230 /* power down the optics for 82599 SFP+ fiber */ 11231 if (hw->mac.ops.disable_tx_laser) 11232 hw->mac.ops.disable_tx_laser(hw); 11233 11234 /* carrier off reporting is important to ethtool even BEFORE open */ 11235 netif_carrier_off(netdev); 11236 11237#ifdef CONFIG_IXGBE_DCA 11238 if (dca_add_requester(&pdev->dev) == 0) { 11239 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11240 ixgbe_setup_dca(adapter); 11241 } 11242#endif 11243 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11244 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11245 for (i = 0; i < adapter->num_vfs; i++) 11246 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11247 } 11248 11249 /* firmware requires driver version to be 0xFFFFFFFF 11250 * since os does not support feature 11251 */ 11252 if (hw->mac.ops.set_fw_drv_ver) 11253 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 11254 sizeof(UTS_RELEASE) - 1, 11255 UTS_RELEASE); 11256 11257 /* add san mac addr to netdev */ 11258 ixgbe_add_sanmac_netdev(netdev); 11259 11260 e_dev_info("%s\n", ixgbe_default_device_descr); 11261 11262#ifdef CONFIG_IXGBE_HWMON 11263 if (ixgbe_sysfs_init(adapter)) 11264 e_err(probe, "failed to allocate sysfs resources\n"); 11265#endif /* CONFIG_IXGBE_HWMON */ 11266 11267 ixgbe_dbg_adapter_init(adapter); 11268 11269 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 11270 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 11271 hw->mac.ops.setup_link(hw, 11272 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 11273 true); 11274 11275 err = ixgbe_mii_bus_init(hw); 11276 if (err) 11277 goto err_netdev; 11278 11279 return 0; 11280 11281err_netdev: 11282 unregister_netdev(netdev); 11283err_register: 11284 ixgbe_release_hw_control(adapter); 11285 ixgbe_clear_interrupt_scheme(adapter); 11286err_sw_init: 11287 ixgbe_disable_sriov(adapter); 11288 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 11289 iounmap(adapter->io_addr); 11290 kfree(adapter->jump_tables[0]); 11291 kfree(adapter->mac_table); 11292 kfree(adapter->rss_key); 11293 bitmap_free(adapter->af_xdp_zc_qps); 11294err_ioremap: 11295 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11296 free_netdev(netdev); 11297err_alloc_etherdev: 11298 pci_release_mem_regions(pdev); 11299err_pci_reg: 11300err_dma: 11301 if (!adapter || disable_dev) 11302 pci_disable_device(pdev); 11303 return err; 11304} 11305 11306/** 11307 * ixgbe_remove - Device Removal Routine 11308 * @pdev: PCI device information struct 11309 * 11310 * ixgbe_remove is called by the PCI subsystem to alert the driver 11311 * that it should release a PCI device. The could be caused by a 11312 * Hot-Plug event, or because the driver is going to be removed from 11313 * memory. 11314 **/ 11315static void ixgbe_remove(struct pci_dev *pdev) 11316{ 11317 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11318 struct net_device *netdev; 11319 bool disable_dev; 11320 int i; 11321 11322 /* if !adapter then we already cleaned up in probe */ 11323 if (!adapter) 11324 return; 11325 11326 netdev = adapter->netdev; 11327 ixgbe_dbg_adapter_exit(adapter); 11328 11329 set_bit(__IXGBE_REMOVING, &adapter->state); 11330 cancel_work_sync(&adapter->service_task); 11331 11332 if (adapter->mii_bus) 11333 mdiobus_unregister(adapter->mii_bus); 11334 11335#ifdef CONFIG_IXGBE_DCA 11336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 11337 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 11338 dca_remove_requester(&pdev->dev); 11339 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 11340 IXGBE_DCA_CTRL_DCA_DISABLE); 11341 } 11342 11343#endif 11344#ifdef CONFIG_IXGBE_HWMON 11345 ixgbe_sysfs_exit(adapter); 11346#endif /* CONFIG_IXGBE_HWMON */ 11347 11348 /* remove the added san mac */ 11349 ixgbe_del_sanmac_netdev(netdev); 11350 11351#ifdef CONFIG_PCI_IOV 11352 ixgbe_disable_sriov(adapter); 11353#endif 11354 if (netdev->reg_state == NETREG_REGISTERED) 11355 unregister_netdev(netdev); 11356 11357 ixgbe_stop_ipsec_offload(adapter); 11358 ixgbe_clear_interrupt_scheme(adapter); 11359 11360 ixgbe_release_hw_control(adapter); 11361 11362#ifdef CONFIG_DCB 11363 kfree(adapter->ixgbe_ieee_pfc); 11364 kfree(adapter->ixgbe_ieee_ets); 11365 11366#endif 11367 iounmap(adapter->io_addr); 11368 pci_release_mem_regions(pdev); 11369 11370 e_dev_info("complete\n"); 11371 11372 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 11373 if (adapter->jump_tables[i]) { 11374 kfree(adapter->jump_tables[i]->input); 11375 kfree(adapter->jump_tables[i]->mask); 11376 } 11377 kfree(adapter->jump_tables[i]); 11378 } 11379 11380 kfree(adapter->mac_table); 11381 kfree(adapter->rss_key); 11382 bitmap_free(adapter->af_xdp_zc_qps); 11383 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 11384 free_netdev(netdev); 11385 11386 if (disable_dev) 11387 pci_disable_device(pdev); 11388} 11389 11390/** 11391 * ixgbe_io_error_detected - called when PCI error is detected 11392 * @pdev: Pointer to PCI device 11393 * @state: The current pci connection state 11394 * 11395 * This function is called after a PCI bus error affecting 11396 * this device has been detected. 11397 */ 11398static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 11399 pci_channel_state_t state) 11400{ 11401 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11402 struct net_device *netdev = adapter->netdev; 11403 11404#ifdef CONFIG_PCI_IOV 11405 struct ixgbe_hw *hw = &adapter->hw; 11406 struct pci_dev *bdev, *vfdev; 11407 u32 dw0, dw1, dw2, dw3; 11408 int vf, pos; 11409 u16 req_id, pf_func; 11410 11411 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 11412 adapter->num_vfs == 0) 11413 goto skip_bad_vf_detection; 11414 11415 bdev = pdev->bus->self; 11416 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 11417 bdev = bdev->bus->self; 11418 11419 if (!bdev) 11420 goto skip_bad_vf_detection; 11421 11422 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 11423 if (!pos) 11424 goto skip_bad_vf_detection; 11425 11426 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 11427 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 11428 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 11429 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 11430 if (ixgbe_removed(hw->hw_addr)) 11431 goto skip_bad_vf_detection; 11432 11433 req_id = dw1 >> 16; 11434 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 11435 if (!(req_id & 0x0080)) 11436 goto skip_bad_vf_detection; 11437 11438 pf_func = req_id & 0x01; 11439 if ((pf_func & 1) == (pdev->devfn & 1)) { 11440 unsigned int device_id; 11441 11442 vf = FIELD_GET(0x7F, req_id); 11443 e_dev_err("VF %d has caused a PCIe error\n", vf); 11444 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 11445 "%8.8x\tdw3: %8.8x\n", 11446 dw0, dw1, dw2, dw3); 11447 switch (adapter->hw.mac.type) { 11448 case ixgbe_mac_82599EB: 11449 device_id = IXGBE_82599_VF_DEVICE_ID; 11450 break; 11451 case ixgbe_mac_X540: 11452 device_id = IXGBE_X540_VF_DEVICE_ID; 11453 break; 11454 case ixgbe_mac_X550: 11455 device_id = IXGBE_DEV_ID_X550_VF; 11456 break; 11457 case ixgbe_mac_X550EM_x: 11458 device_id = IXGBE_DEV_ID_X550EM_X_VF; 11459 break; 11460 case ixgbe_mac_x550em_a: 11461 device_id = IXGBE_DEV_ID_X550EM_A_VF; 11462 break; 11463 default: 11464 device_id = 0; 11465 break; 11466 } 11467 11468 /* Find the pci device of the offending VF */ 11469 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 11470 while (vfdev) { 11471 if (vfdev->devfn == (req_id & 0xFF)) 11472 break; 11473 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 11474 device_id, vfdev); 11475 } 11476 /* 11477 * There's a slim chance the VF could have been hot plugged, 11478 * so if it is no longer present we don't need to issue the 11479 * VFLR. Just clean up the AER in that case. 11480 */ 11481 if (vfdev) { 11482 pcie_flr(vfdev); 11483 /* Free device reference count */ 11484 pci_dev_put(vfdev); 11485 } 11486 } 11487 11488 /* 11489 * Even though the error may have occurred on the other port 11490 * we still need to increment the vf error reference count for 11491 * both ports because the I/O resume function will be called 11492 * for both of them. 11493 */ 11494 adapter->vferr_refcount++; 11495 11496 return PCI_ERS_RESULT_RECOVERED; 11497 11498skip_bad_vf_detection: 11499#endif /* CONFIG_PCI_IOV */ 11500 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 11501 return PCI_ERS_RESULT_DISCONNECT; 11502 11503 if (!netif_device_present(netdev)) 11504 return PCI_ERS_RESULT_DISCONNECT; 11505 11506 rtnl_lock(); 11507 netif_device_detach(netdev); 11508 11509 if (netif_running(netdev)) 11510 ixgbe_close_suspend(adapter); 11511 11512 if (state == pci_channel_io_perm_failure) { 11513 rtnl_unlock(); 11514 return PCI_ERS_RESULT_DISCONNECT; 11515 } 11516 11517 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 11518 pci_disable_device(pdev); 11519 rtnl_unlock(); 11520 11521 /* Request a slot reset. */ 11522 return PCI_ERS_RESULT_NEED_RESET; 11523} 11524 11525/** 11526 * ixgbe_io_slot_reset - called after the pci bus has been reset. 11527 * @pdev: Pointer to PCI device 11528 * 11529 * Restart the card from scratch, as if from a cold-boot. 11530 */ 11531static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 11532{ 11533 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11534 pci_ers_result_t result; 11535 11536 if (pci_enable_device_mem(pdev)) { 11537 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 11538 result = PCI_ERS_RESULT_DISCONNECT; 11539 } else { 11540 smp_mb__before_atomic(); 11541 clear_bit(__IXGBE_DISABLED, &adapter->state); 11542 adapter->hw.hw_addr = adapter->io_addr; 11543 pci_set_master(pdev); 11544 pci_restore_state(pdev); 11545 pci_save_state(pdev); 11546 11547 pci_wake_from_d3(pdev, false); 11548 11549 ixgbe_reset(adapter); 11550 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11551 result = PCI_ERS_RESULT_RECOVERED; 11552 } 11553 11554 return result; 11555} 11556 11557/** 11558 * ixgbe_io_resume - called when traffic can start flowing again. 11559 * @pdev: Pointer to PCI device 11560 * 11561 * This callback is called when the error recovery driver tells us that 11562 * its OK to resume normal operation. 11563 */ 11564static void ixgbe_io_resume(struct pci_dev *pdev) 11565{ 11566 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 11567 struct net_device *netdev = adapter->netdev; 11568 11569#ifdef CONFIG_PCI_IOV 11570 if (adapter->vferr_refcount) { 11571 e_info(drv, "Resuming after VF err\n"); 11572 adapter->vferr_refcount--; 11573 return; 11574 } 11575 11576#endif 11577 rtnl_lock(); 11578 if (netif_running(netdev)) 11579 ixgbe_open(netdev); 11580 11581 netif_device_attach(netdev); 11582 rtnl_unlock(); 11583} 11584 11585static const struct pci_error_handlers ixgbe_err_handler = { 11586 .error_detected = ixgbe_io_error_detected, 11587 .slot_reset = ixgbe_io_slot_reset, 11588 .resume = ixgbe_io_resume, 11589}; 11590 11591static SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 11592 11593static struct pci_driver ixgbe_driver = { 11594 .name = ixgbe_driver_name, 11595 .id_table = ixgbe_pci_tbl, 11596 .probe = ixgbe_probe, 11597 .remove = ixgbe_remove, 11598 .driver.pm = &ixgbe_pm_ops, 11599 .shutdown = ixgbe_shutdown, 11600 .sriov_configure = ixgbe_pci_sriov_configure, 11601 .err_handler = &ixgbe_err_handler 11602}; 11603 11604/** 11605 * ixgbe_init_module - Driver Registration Routine 11606 * 11607 * ixgbe_init_module is the first routine called when the driver is 11608 * loaded. All it does is register with the PCI subsystem. 11609 **/ 11610static int __init ixgbe_init_module(void) 11611{ 11612 int ret; 11613 pr_info("%s\n", ixgbe_driver_string); 11614 pr_info("%s\n", ixgbe_copyright); 11615 11616 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 11617 if (!ixgbe_wq) { 11618 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 11619 return -ENOMEM; 11620 } 11621 11622 ixgbe_dbg_init(); 11623 11624 ret = pci_register_driver(&ixgbe_driver); 11625 if (ret) { 11626 destroy_workqueue(ixgbe_wq); 11627 ixgbe_dbg_exit(); 11628 return ret; 11629 } 11630 11631#ifdef CONFIG_IXGBE_DCA 11632 dca_register_notify(&dca_notifier); 11633#endif 11634 11635 return 0; 11636} 11637 11638module_init(ixgbe_init_module); 11639 11640/** 11641 * ixgbe_exit_module - Driver Exit Cleanup Routine 11642 * 11643 * ixgbe_exit_module is called just before the driver is removed 11644 * from memory. 11645 **/ 11646static void __exit ixgbe_exit_module(void) 11647{ 11648#ifdef CONFIG_IXGBE_DCA 11649 dca_unregister_notify(&dca_notifier); 11650#endif 11651 pci_unregister_driver(&ixgbe_driver); 11652 11653 ixgbe_dbg_exit(); 11654 if (ixgbe_wq) { 11655 destroy_workqueue(ixgbe_wq); 11656 ixgbe_wq = NULL; 11657 } 11658} 11659 11660#ifdef CONFIG_IXGBE_DCA 11661static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 11662 void *p) 11663{ 11664 int ret_val; 11665 11666 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 11667 __ixgbe_notify_dca); 11668 11669 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 11670} 11671 11672#endif /* CONFIG_IXGBE_DCA */ 11673 11674module_exit(ixgbe_exit_module); 11675 11676/* ixgbe_main.c */ 11677