1/* bnx2x_main.c: QLogic Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * Copyright (c) 2014 QLogic Corporation 5 * All rights reserved 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com> 12 * Written by: Eliezer Tamir 13 * Based on code from Michael Chan's bnx2 driver 14 * UDP CSUM errata workaround by Arik Gendelman 15 * Slowpath and fastpath rework by Vladislav Zolotarov 16 * Statistics and Link management by Yitchak Gertner 17 * 18 */ 19 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22#include <linux/module.h> 23#include <linux/moduleparam.h> 24#include <linux/kernel.h> 25#include <linux/device.h> /* for dev_info() */ 26#include <linux/timer.h> 27#include <linux/errno.h> 28#include <linux/ioport.h> 29#include <linux/slab.h> 30#include <linux/interrupt.h> 31#include <linux/pci.h> 32#include <linux/init.h> 33#include <linux/netdevice.h> 34#include <linux/etherdevice.h> 35#include <linux/skbuff.h> 36#include <linux/dma-mapping.h> 37#include <linux/bitops.h> 38#include <linux/irq.h> 39#include <linux/delay.h> 40#include <asm/byteorder.h> 41#include <linux/time.h> 42#include <linux/ethtool.h> 43#include <linux/mii.h> 44#include <linux/if_vlan.h> 45#include <linux/crash_dump.h> 46#include <net/ip.h> 47#include <net/ipv6.h> 48#include <net/tcp.h> 49#include <net/vxlan.h> 50#include <net/checksum.h> 51#include <net/ip6_checksum.h> 52#include <linux/workqueue.h> 53#include <linux/crc32.h> 54#include <linux/crc32c.h> 55#include <linux/prefetch.h> 56#include <linux/zlib.h> 57#include <linux/io.h> 58#include <linux/semaphore.h> 59#include <linux/stringify.h> 60#include <linux/vmalloc.h> 61#include "bnx2x.h" 62#include "bnx2x_init.h" 63#include "bnx2x_init_ops.h" 64#include "bnx2x_cmn.h" 65#include "bnx2x_vfpf.h" 66#include "bnx2x_dcb.h" 67#include "bnx2x_sp.h" 68#include <linux/firmware.h> 69#include "bnx2x_fw_file_hdr.h" 70/* FW files */ 71#define FW_FILE_VERSION \ 72 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 73 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 74 __stringify(BCM_5710_FW_REVISION_VERSION) "." \ 75 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 76 77#define FW_FILE_VERSION_V15 \ 78 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \ 79 __stringify(BCM_5710_FW_MINOR_VERSION) "." \ 80 __stringify(BCM_5710_FW_REVISION_VERSION_V15) "." \ 81 __stringify(BCM_5710_FW_ENGINEERING_VERSION) 82 83#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw" 84#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw" 85#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw" 86#define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw" 87#define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw" 88#define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw" 89 90/* Time in jiffies before concluding the transmitter is hung */ 91#define TX_TIMEOUT (5*HZ) 92 93MODULE_AUTHOR("Eliezer Tamir"); 94MODULE_DESCRIPTION("QLogic " 95 "BCM57710/57711/57711E/" 96 "57712/57712_MF/57800/57800_MF/57810/57810_MF/" 97 "57840/57840_MF Driver"); 98MODULE_LICENSE("GPL"); 99MODULE_FIRMWARE(FW_FILE_NAME_E1); 100MODULE_FIRMWARE(FW_FILE_NAME_E1H); 101MODULE_FIRMWARE(FW_FILE_NAME_E2); 102MODULE_FIRMWARE(FW_FILE_NAME_E1_V15); 103MODULE_FIRMWARE(FW_FILE_NAME_E1H_V15); 104MODULE_FIRMWARE(FW_FILE_NAME_E2_V15); 105 106int bnx2x_num_queues; 107module_param_named(num_queues, bnx2x_num_queues, int, 0444); 108MODULE_PARM_DESC(num_queues, 109 " Set number of queues (default is as a number of CPUs)"); 110 111static int disable_tpa; 112module_param(disable_tpa, int, 0444); 113MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature"); 114 115static int int_mode; 116module_param(int_mode, int, 0444); 117MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " 118 "(1 INT#x; 2 MSI)"); 119 120static int dropless_fc; 121module_param(dropless_fc, int, 0444); 122MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring"); 123 124static int mrrs = -1; 125module_param(mrrs, int, 0444); 126MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)"); 127 128static int debug; 129module_param(debug, int, 0444); 130MODULE_PARM_DESC(debug, " Default debug msglevel"); 131 132static struct workqueue_struct *bnx2x_wq; 133struct workqueue_struct *bnx2x_iov_wq; 134 135struct bnx2x_mac_vals { 136 u32 xmac_addr; 137 u32 xmac_val; 138 u32 emac_addr; 139 u32 emac_val; 140 u32 umac_addr[2]; 141 u32 umac_val[2]; 142 u32 bmac_addr; 143 u32 bmac_val[2]; 144}; 145 146enum bnx2x_board_type { 147 BCM57710 = 0, 148 BCM57711, 149 BCM57711E, 150 BCM57712, 151 BCM57712_MF, 152 BCM57712_VF, 153 BCM57800, 154 BCM57800_MF, 155 BCM57800_VF, 156 BCM57810, 157 BCM57810_MF, 158 BCM57810_VF, 159 BCM57840_4_10, 160 BCM57840_2_20, 161 BCM57840_MF, 162 BCM57840_VF, 163 BCM57811, 164 BCM57811_MF, 165 BCM57840_O, 166 BCM57840_MFO, 167 BCM57811_VF 168}; 169 170/* indexed by board_type, above */ 171static struct { 172 char *name; 173} board_info[] = { 174 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" }, 175 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" }, 176 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" }, 177 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" }, 178 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" }, 179 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" }, 180 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" }, 181 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" }, 182 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" }, 183 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" }, 184 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" }, 185 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" }, 186 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" }, 187 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" }, 188 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, 189 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }, 190 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" }, 191 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" }, 192 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" }, 193 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" }, 194 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" } 195}; 196 197#ifndef PCI_DEVICE_ID_NX2_57710 198#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710 199#endif 200#ifndef PCI_DEVICE_ID_NX2_57711 201#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711 202#endif 203#ifndef PCI_DEVICE_ID_NX2_57711E 204#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E 205#endif 206#ifndef PCI_DEVICE_ID_NX2_57712 207#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712 208#endif 209#ifndef PCI_DEVICE_ID_NX2_57712_MF 210#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF 211#endif 212#ifndef PCI_DEVICE_ID_NX2_57712_VF 213#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF 214#endif 215#ifndef PCI_DEVICE_ID_NX2_57800 216#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800 217#endif 218#ifndef PCI_DEVICE_ID_NX2_57800_MF 219#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF 220#endif 221#ifndef PCI_DEVICE_ID_NX2_57800_VF 222#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF 223#endif 224#ifndef PCI_DEVICE_ID_NX2_57810 225#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810 226#endif 227#ifndef PCI_DEVICE_ID_NX2_57810_MF 228#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF 229#endif 230#ifndef PCI_DEVICE_ID_NX2_57840_O 231#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE 232#endif 233#ifndef PCI_DEVICE_ID_NX2_57810_VF 234#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF 235#endif 236#ifndef PCI_DEVICE_ID_NX2_57840_4_10 237#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10 238#endif 239#ifndef PCI_DEVICE_ID_NX2_57840_2_20 240#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20 241#endif 242#ifndef PCI_DEVICE_ID_NX2_57840_MFO 243#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE 244#endif 245#ifndef PCI_DEVICE_ID_NX2_57840_MF 246#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF 247#endif 248#ifndef PCI_DEVICE_ID_NX2_57840_VF 249#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF 250#endif 251#ifndef PCI_DEVICE_ID_NX2_57811 252#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811 253#endif 254#ifndef PCI_DEVICE_ID_NX2_57811_MF 255#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF 256#endif 257#ifndef PCI_DEVICE_ID_NX2_57811_VF 258#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF 259#endif 260 261static const struct pci_device_id bnx2x_pci_tbl[] = { 262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 }, 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 }, 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E }, 265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 }, 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF }, 267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF }, 268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 }, 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF }, 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF }, 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 }, 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF }, 273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O }, 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 275 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 }, 276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 }, 277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF }, 278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO }, 279 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 280 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF }, 281 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 282 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF }, 283 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 }, 284 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF }, 285 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF }, 286 { 0 } 287}; 288 289MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); 290 291const u32 dmae_reg_go_c[] = { 292 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 293 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 294 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 295 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 296}; 297 298/* Global resources for unloading a previously loaded device */ 299#define BNX2X_PREV_WAIT_NEEDED 1 300static DEFINE_SEMAPHORE(bnx2x_prev_sem, 1); 301static LIST_HEAD(bnx2x_prev_list); 302 303/* Forward declaration */ 304static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev); 305static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp); 306static int bnx2x_set_storm_rx_mode(struct bnx2x *bp); 307 308/**************************************************************************** 309* General service functions 310****************************************************************************/ 311 312static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr); 313 314static void __storm_memset_dma_mapping(struct bnx2x *bp, 315 u32 addr, dma_addr_t mapping) 316{ 317 REG_WR(bp, addr, U64_LO(mapping)); 318 REG_WR(bp, addr + 4, U64_HI(mapping)); 319} 320 321static void storm_memset_spq_addr(struct bnx2x *bp, 322 dma_addr_t mapping, u16 abs_fid) 323{ 324 u32 addr = XSEM_REG_FAST_MEMORY + 325 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid); 326 327 __storm_memset_dma_mapping(bp, addr, mapping); 328} 329 330static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, 331 u16 pf_id) 332{ 333 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), 334 pf_id); 335 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), 336 pf_id); 337 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), 338 pf_id); 339 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), 340 pf_id); 341} 342 343static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, 344 u8 enable) 345{ 346 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), 347 enable); 348 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), 349 enable); 350 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), 351 enable); 352 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), 353 enable); 354} 355 356static void storm_memset_eq_data(struct bnx2x *bp, 357 struct event_ring_data *eq_data, 358 u16 pfid) 359{ 360 size_t size = sizeof(struct event_ring_data); 361 362 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid); 363 364 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); 365} 366 367static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, 368 u16 pfid) 369{ 370 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid); 371 REG_WR16(bp, addr, eq_prod); 372} 373 374/* used only at init 375 * locking is done by mcp 376 */ 377static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) 378{ 379 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 380 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); 381 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 382 PCICFG_VENDOR_ID_OFFSET); 383} 384 385static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 386{ 387 u32 val; 388 389 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); 390 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); 391 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 392 PCICFG_VENDOR_ID_OFFSET); 393 394 return val; 395} 396 397#define DMAE_DP_SRC_GRC "grc src_addr [%08x]" 398#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]" 399#define DMAE_DP_DST_GRC "grc dst_addr [%08x]" 400#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]" 401#define DMAE_DP_DST_NONE "dst_addr [none]" 402 403static void bnx2x_dp_dmae(struct bnx2x *bp, 404 struct dmae_command *dmae, int msglvl) 405{ 406 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC; 407 int i; 408 409 switch (dmae->opcode & DMAE_COMMAND_DST) { 410 case DMAE_CMD_DST_PCI: 411 if (src_type == DMAE_CMD_SRC_PCI) 412 DP(msglvl, "DMAE: opcode 0x%08x\n" 413 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 414 "comp_addr [%x:%08x], comp_val 0x%08x\n", 415 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 416 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 417 dmae->comp_addr_hi, dmae->comp_addr_lo, 418 dmae->comp_val); 419 else 420 DP(msglvl, "DMAE: opcode 0x%08x\n" 421 "src [%08x], len [%d*4], dst [%x:%08x]\n" 422 "comp_addr [%x:%08x], comp_val 0x%08x\n", 423 dmae->opcode, dmae->src_addr_lo >> 2, 424 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 425 dmae->comp_addr_hi, dmae->comp_addr_lo, 426 dmae->comp_val); 427 break; 428 case DMAE_CMD_DST_GRC: 429 if (src_type == DMAE_CMD_SRC_PCI) 430 DP(msglvl, "DMAE: opcode 0x%08x\n" 431 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 432 "comp_addr [%x:%08x], comp_val 0x%08x\n", 433 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 434 dmae->len, dmae->dst_addr_lo >> 2, 435 dmae->comp_addr_hi, dmae->comp_addr_lo, 436 dmae->comp_val); 437 else 438 DP(msglvl, "DMAE: opcode 0x%08x\n" 439 "src [%08x], len [%d*4], dst [%08x]\n" 440 "comp_addr [%x:%08x], comp_val 0x%08x\n", 441 dmae->opcode, dmae->src_addr_lo >> 2, 442 dmae->len, dmae->dst_addr_lo >> 2, 443 dmae->comp_addr_hi, dmae->comp_addr_lo, 444 dmae->comp_val); 445 break; 446 default: 447 if (src_type == DMAE_CMD_SRC_PCI) 448 DP(msglvl, "DMAE: opcode 0x%08x\n" 449 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 450 "comp_addr [%x:%08x] comp_val 0x%08x\n", 451 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 452 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 453 dmae->comp_val); 454 else 455 DP(msglvl, "DMAE: opcode 0x%08x\n" 456 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 457 "comp_addr [%x:%08x] comp_val 0x%08x\n", 458 dmae->opcode, dmae->src_addr_lo >> 2, 459 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 460 dmae->comp_val); 461 break; 462 } 463 464 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) 465 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n", 466 i, *(((u32 *)dmae) + i)); 467} 468 469/* copy command into DMAE command memory and set DMAE command go */ 470void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) 471{ 472 u32 cmd_offset; 473 int i; 474 475 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 476 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 477 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 478 } 479 REG_WR(bp, dmae_reg_go_c[idx], 1); 480} 481 482u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type) 483{ 484 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 485 DMAE_CMD_C_ENABLE); 486} 487 488u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode) 489{ 490 return opcode & ~DMAE_CMD_SRC_RESET; 491} 492 493u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 494 bool with_comp, u8 comp_type) 495{ 496 u32 opcode = 0; 497 498 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 499 (dst_type << DMAE_COMMAND_DST_SHIFT)); 500 501 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 502 503 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 504 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | 505 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 506 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 507 508#ifdef __BIG_ENDIAN 509 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 510#else 511 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 512#endif 513 if (with_comp) 514 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type); 515 return opcode; 516} 517 518void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, 519 struct dmae_command *dmae, 520 u8 src_type, u8 dst_type) 521{ 522 memset(dmae, 0, sizeof(struct dmae_command)); 523 524 /* set the opcode */ 525 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, 526 true, DMAE_COMP_PCI); 527 528 /* fill in the completion parameters */ 529 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 530 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 531 dmae->comp_val = DMAE_COMP_VAL; 532} 533 534/* issue a dmae command over the init-channel and wait for completion */ 535int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 536 u32 *comp) 537{ 538 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 539 int rc = 0; 540 541 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); 542 543 /* Lock the dmae channel. Disable BHs to prevent a dead-lock 544 * as long as this code is called both from syscall context and 545 * from ndo_set_rx_mode() flow that may be called from BH. 546 */ 547 548 spin_lock_bh(&bp->dmae_lock); 549 550 /* reset completion */ 551 *comp = 0; 552 553 /* post the command on the channel used for initializations */ 554 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); 555 556 /* wait for completion */ 557 udelay(5); 558 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 559 560 if (!cnt || 561 (bp->recovery_state != BNX2X_RECOVERY_DONE && 562 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 563 BNX2X_ERR("DMAE timeout!\n"); 564 rc = DMAE_TIMEOUT; 565 goto unlock; 566 } 567 cnt--; 568 udelay(50); 569 } 570 if (*comp & DMAE_PCI_ERR_FLAG) { 571 BNX2X_ERR("DMAE PCI error!\n"); 572 rc = DMAE_PCI_ERROR; 573 } 574 575unlock: 576 577 spin_unlock_bh(&bp->dmae_lock); 578 579 return rc; 580} 581 582void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 583 u32 len32) 584{ 585 int rc; 586 struct dmae_command dmae; 587 588 if (!bp->dmae_ready) { 589 u32 *data = bnx2x_sp(bp, wb_data[0]); 590 591 if (CHIP_IS_E1(bp)) 592 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 593 else 594 bnx2x_init_str_wr(bp, dst_addr, data, len32); 595 return; 596 } 597 598 /* set opcode and fixed command fields */ 599 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 600 601 /* fill in addresses and len */ 602 dmae.src_addr_lo = U64_LO(dma_addr); 603 dmae.src_addr_hi = U64_HI(dma_addr); 604 dmae.dst_addr_lo = dst_addr >> 2; 605 dmae.dst_addr_hi = 0; 606 dmae.len = len32; 607 608 /* issue the command and wait for completion */ 609 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); 610 if (rc) { 611 BNX2X_ERR("DMAE returned failure %d\n", rc); 612#ifdef BNX2X_STOP_ON_ERROR 613 bnx2x_panic(); 614#endif 615 } 616} 617 618void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 619{ 620 int rc; 621 struct dmae_command dmae; 622 623 if (!bp->dmae_ready) { 624 u32 *data = bnx2x_sp(bp, wb_data[0]); 625 int i; 626 627 if (CHIP_IS_E1(bp)) 628 for (i = 0; i < len32; i++) 629 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 630 else 631 for (i = 0; i < len32; i++) 632 data[i] = REG_RD(bp, src_addr + i*4); 633 634 return; 635 } 636 637 /* set opcode and fixed command fields */ 638 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 639 640 /* fill in addresses and len */ 641 dmae.src_addr_lo = src_addr >> 2; 642 dmae.src_addr_hi = 0; 643 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 644 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); 645 dmae.len = len32; 646 647 /* issue the command and wait for completion */ 648 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); 649 if (rc) { 650 BNX2X_ERR("DMAE returned failure %d\n", rc); 651#ifdef BNX2X_STOP_ON_ERROR 652 bnx2x_panic(); 653#endif 654 } 655} 656 657static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, 658 u32 addr, u32 len) 659{ 660 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); 661 int offset = 0; 662 663 while (len > dmae_wr_max) { 664 bnx2x_write_dmae(bp, phys_addr + offset, 665 addr + offset, dmae_wr_max); 666 offset += dmae_wr_max * 4; 667 len -= dmae_wr_max; 668 } 669 670 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); 671} 672 673enum storms { 674 XSTORM, 675 TSTORM, 676 CSTORM, 677 USTORM, 678 MAX_STORMS 679}; 680 681#define STORMS_NUM 4 682#define REGS_IN_ENTRY 4 683 684static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, 685 enum storms storm, 686 int entry) 687{ 688 switch (storm) { 689 case XSTORM: 690 return XSTORM_ASSERT_LIST_OFFSET(entry); 691 case TSTORM: 692 return TSTORM_ASSERT_LIST_OFFSET(entry); 693 case CSTORM: 694 return CSTORM_ASSERT_LIST_OFFSET(entry); 695 case USTORM: 696 return USTORM_ASSERT_LIST_OFFSET(entry); 697 case MAX_STORMS: 698 default: 699 BNX2X_ERR("unknown storm\n"); 700 } 701 return -EINVAL; 702} 703 704static int bnx2x_mc_assert(struct bnx2x *bp) 705{ 706 char last_idx; 707 int i, j, rc = 0; 708 enum storms storm; 709 u32 regs[REGS_IN_ENTRY]; 710 u32 bar_storm_intmem[STORMS_NUM] = { 711 BAR_XSTRORM_INTMEM, 712 BAR_TSTRORM_INTMEM, 713 BAR_CSTRORM_INTMEM, 714 BAR_USTRORM_INTMEM 715 }; 716 u32 storm_assert_list_index[STORMS_NUM] = { 717 XSTORM_ASSERT_LIST_INDEX_OFFSET, 718 TSTORM_ASSERT_LIST_INDEX_OFFSET, 719 CSTORM_ASSERT_LIST_INDEX_OFFSET, 720 USTORM_ASSERT_LIST_INDEX_OFFSET 721 }; 722 char *storms_string[STORMS_NUM] = { 723 "XSTORM", 724 "TSTORM", 725 "CSTORM", 726 "USTORM" 727 }; 728 729 for (storm = XSTORM; storm < MAX_STORMS; storm++) { 730 last_idx = REG_RD8(bp, bar_storm_intmem[storm] + 731 storm_assert_list_index[storm]); 732 if (last_idx) 733 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n", 734 storms_string[storm], last_idx); 735 736 /* print the asserts */ 737 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) { 738 /* read a single assert entry */ 739 for (j = 0; j < REGS_IN_ENTRY; j++) 740 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + 741 bnx2x_get_assert_list_entry(bp, 742 storm, 743 i) + 744 sizeof(u32) * j); 745 746 /* log entry if it contains a valid assert */ 747 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) { 748 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 749 storms_string[storm], i, regs[3], 750 regs[2], regs[1], regs[0]); 751 rc++; 752 } else { 753 break; 754 } 755 } 756 } 757 758 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n", 759 CHIP_IS_E1(bp) ? "everest1" : 760 CHIP_IS_E1H(bp) ? "everest1h" : 761 CHIP_IS_E2(bp) ? "everest2" : "everest3", 762 bp->fw_major, bp->fw_minor, bp->fw_rev); 763 764 return rc; 765} 766 767#define MCPR_TRACE_BUFFER_SIZE (0x800) 768#define SCRATCH_BUFFER_SIZE(bp) \ 769 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000)) 770 771void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) 772{ 773 u32 addr, val; 774 u32 mark, offset; 775 __be32 data[9]; 776 int word; 777 u32 trace_shmem_base; 778 if (BP_NOMCP(bp)) { 779 BNX2X_ERR("NO MCP - can not dump\n"); 780 return; 781 } 782 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", 783 (bp->common.bc_ver & 0xff0000) >> 16, 784 (bp->common.bc_ver & 0xff00) >> 8, 785 (bp->common.bc_ver & 0xff)); 786 787 if (pci_channel_offline(bp->pdev)) { 788 BNX2X_ERR("Cannot dump MCP info while in PCI error\n"); 789 return; 790 } 791 792 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 793 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 794 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val); 795 796 if (BP_PATH(bp) == 0) 797 trace_shmem_base = bp->common.shmem_base; 798 else 799 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); 800 801 /* sanity */ 802 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || 803 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + 804 SCRATCH_BUFFER_SIZE(bp)) { 805 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n", 806 trace_shmem_base); 807 return; 808 } 809 810 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE; 811 812 /* validate TRCB signature */ 813 mark = REG_RD(bp, addr); 814 if (mark != MFW_TRACE_SIGNATURE) { 815 BNX2X_ERR("Trace buffer signature is missing."); 816 return ; 817 } 818 819 /* read cyclic buffer pointer */ 820 addr += 4; 821 mark = REG_RD(bp, addr); 822 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; 823 if (mark >= trace_shmem_base || mark < addr + 4) { 824 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n"); 825 return; 826 } 827 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark); 828 829 printk("%s", lvl); 830 831 /* dump buffer after the mark */ 832 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) { 833 for (word = 0; word < 8; word++) 834 data[word] = htonl(REG_RD(bp, offset + 4*word)); 835 data[8] = 0x0; 836 pr_cont("%s", (char *)data); 837 } 838 839 /* dump buffer before the mark */ 840 for (offset = addr + 4; offset <= mark; offset += 0x8*4) { 841 for (word = 0; word < 8; word++) 842 data[word] = htonl(REG_RD(bp, offset + 4*word)); 843 data[8] = 0x0; 844 pr_cont("%s", (char *)data); 845 } 846 printk("%s" "end of fw dump\n", lvl); 847} 848 849static void bnx2x_fw_dump(struct bnx2x *bp) 850{ 851 bnx2x_fw_dump_lvl(bp, KERN_ERR); 852} 853 854static void bnx2x_hc_int_disable(struct bnx2x *bp) 855{ 856 int port = BP_PORT(bp); 857 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 858 u32 val = REG_RD(bp, addr); 859 860 /* in E1 we must use only PCI configuration space to disable 861 * MSI/MSIX capability 862 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block 863 */ 864 if (CHIP_IS_E1(bp)) { 865 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on 866 * Use mask register to prevent from HC sending interrupts 867 * after we exit the function 868 */ 869 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); 870 871 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 872 HC_CONFIG_0_REG_INT_LINE_EN_0 | 873 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 874 } else 875 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 876 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 877 HC_CONFIG_0_REG_INT_LINE_EN_0 | 878 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 879 880 DP(NETIF_MSG_IFDOWN, 881 "write %x to HC %d (addr 0x%x)\n", 882 val, port, addr); 883 884 REG_WR(bp, addr, val); 885 if (REG_RD(bp, addr) != val) 886 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 887} 888 889static void bnx2x_igu_int_disable(struct bnx2x *bp) 890{ 891 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 892 893 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 894 IGU_PF_CONF_INT_LINE_EN | 895 IGU_PF_CONF_ATTN_BIT_EN); 896 897 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val); 898 899 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 900 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) 901 BNX2X_ERR("BUG! Proper val not read from IGU!\n"); 902} 903 904static void bnx2x_int_disable(struct bnx2x *bp) 905{ 906 if (bp->common.int_block == INT_BLOCK_HC) 907 bnx2x_hc_int_disable(bp); 908 else 909 bnx2x_igu_int_disable(bp); 910} 911 912void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) 913{ 914 int i; 915 u16 j; 916 struct hc_sp_status_block_data sp_sb_data; 917 int func = BP_FUNC(bp); 918#ifdef BNX2X_STOP_ON_ERROR 919 u16 start = 0, end = 0; 920 u8 cos; 921#endif 922 if (IS_PF(bp) && disable_int) 923 bnx2x_int_disable(bp); 924 925 bp->stats_state = STATS_STATE_DISABLED; 926 bp->eth_stats.unrecoverable_error++; 927 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n"); 928 929 BNX2X_ERR("begin crash dump -----------------\n"); 930 931 /* Indices */ 932 /* Common */ 933 if (IS_PF(bp)) { 934 struct host_sp_status_block *def_sb = bp->def_status_blk; 935 int data_size, cstorm_offset; 936 937 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n", 938 bp->def_idx, bp->def_att_idx, bp->attn_state, 939 bp->spq_prod_idx, bp->stats_counter); 940 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 941 def_sb->atten_status_block.attn_bits, 942 def_sb->atten_status_block.attn_bits_ack, 943 def_sb->atten_status_block.status_block_id, 944 def_sb->atten_status_block.attn_bits_index); 945 BNX2X_ERR(" def ("); 946 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++) 947 pr_cont("0x%x%s", 948 def_sb->sp_sb.index_values[i], 949 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " "); 950 951 data_size = sizeof(struct hc_sp_status_block_data) / 952 sizeof(u32); 953 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func); 954 for (i = 0; i < data_size; i++) 955 *((u32 *)&sp_sb_data + i) = 956 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + 957 i * sizeof(u32)); 958 959 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n", 960 sp_sb_data.igu_sb_id, 961 sp_sb_data.igu_seg_id, 962 sp_sb_data.p_func.pf_id, 963 sp_sb_data.p_func.vnic_id, 964 sp_sb_data.p_func.vf_id, 965 sp_sb_data.p_func.vf_valid, 966 sp_sb_data.state); 967 } 968 969 for_each_eth_queue(bp, i) { 970 struct bnx2x_fastpath *fp = &bp->fp[i]; 971 int loop; 972 struct hc_status_block_data_e2 sb_data_e2; 973 struct hc_status_block_data_e1x sb_data_e1x; 974 struct hc_status_block_sm *hc_sm_p = 975 CHIP_IS_E1x(bp) ? 976 sb_data_e1x.common.state_machine : 977 sb_data_e2.common.state_machine; 978 struct hc_index_data *hc_index_p = 979 CHIP_IS_E1x(bp) ? 980 sb_data_e1x.index_data : 981 sb_data_e2.index_data; 982 u8 data_size, cos; 983 u32 *sb_data_p; 984 struct bnx2x_fp_txdata txdata; 985 986 if (!bp->fp) 987 break; 988 989 if (!fp->rx_cons_sb) 990 continue; 991 992 /* Rx */ 993 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n", 994 i, fp->rx_bd_prod, fp->rx_bd_cons, 995 fp->rx_comp_prod, 996 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 997 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n", 998 fp->rx_sge_prod, fp->last_max_sge, 999 le16_to_cpu(fp->fp_hc_idx)); 1000 1001 /* Tx */ 1002 for_each_cos_in_tx_queue(fp, cos) 1003 { 1004 if (!fp->txdata_ptr[cos]) 1005 break; 1006 1007 txdata = *fp->txdata_ptr[cos]; 1008 1009 if (!txdata.tx_cons_sb) 1010 continue; 1011 1012 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n", 1013 i, txdata.tx_pkt_prod, 1014 txdata.tx_pkt_cons, txdata.tx_bd_prod, 1015 txdata.tx_bd_cons, 1016 le16_to_cpu(*txdata.tx_cons_sb)); 1017 } 1018 1019 loop = CHIP_IS_E1x(bp) ? 1020 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2; 1021 1022 /* host sb data */ 1023 1024 if (IS_FCOE_FP(fp)) 1025 continue; 1026 1027 BNX2X_ERR(" run indexes ("); 1028 for (j = 0; j < HC_SB_MAX_SM; j++) 1029 pr_cont("0x%x%s", 1030 fp->sb_running_index[j], 1031 (j == HC_SB_MAX_SM - 1) ? ")" : " "); 1032 1033 BNX2X_ERR(" indexes ("); 1034 for (j = 0; j < loop; j++) 1035 pr_cont("0x%x%s", 1036 fp->sb_index_values[j], 1037 (j == loop - 1) ? ")" : " "); 1038 1039 /* VF cannot access FW refelection for status block */ 1040 if (IS_VF(bp)) 1041 continue; 1042 1043 /* fw sb data */ 1044 data_size = CHIP_IS_E1x(bp) ? 1045 sizeof(struct hc_status_block_data_e1x) : 1046 sizeof(struct hc_status_block_data_e2); 1047 data_size /= sizeof(u32); 1048 sb_data_p = CHIP_IS_E1x(bp) ? 1049 (u32 *)&sb_data_e1x : 1050 (u32 *)&sb_data_e2; 1051 /* copy sb data in here */ 1052 for (j = 0; j < data_size; j++) 1053 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + 1054 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) + 1055 j * sizeof(u32)); 1056 1057 if (!CHIP_IS_E1x(bp)) { 1058 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1059 sb_data_e2.common.p_func.pf_id, 1060 sb_data_e2.common.p_func.vf_id, 1061 sb_data_e2.common.p_func.vf_valid, 1062 sb_data_e2.common.p_func.vnic_id, 1063 sb_data_e2.common.same_igu_sb_1b, 1064 sb_data_e2.common.state); 1065 } else { 1066 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n", 1067 sb_data_e1x.common.p_func.pf_id, 1068 sb_data_e1x.common.p_func.vf_id, 1069 sb_data_e1x.common.p_func.vf_valid, 1070 sb_data_e1x.common.p_func.vnic_id, 1071 sb_data_e1x.common.same_igu_sb_1b, 1072 sb_data_e1x.common.state); 1073 } 1074 1075 /* SB_SMs data */ 1076 for (j = 0; j < HC_SB_MAX_SM; j++) { 1077 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n", 1078 j, hc_sm_p[j].__flags, 1079 hc_sm_p[j].igu_sb_id, 1080 hc_sm_p[j].igu_seg_id, 1081 hc_sm_p[j].time_to_expire, 1082 hc_sm_p[j].timer_value); 1083 } 1084 1085 /* Indices data */ 1086 for (j = 0; j < loop; j++) { 1087 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j, 1088 hc_index_p[j].flags, 1089 hc_index_p[j].timeout); 1090 } 1091 } 1092 1093#ifdef BNX2X_STOP_ON_ERROR 1094 if (IS_PF(bp)) { 1095 /* event queue */ 1096 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); 1097 for (i = 0; i < NUM_EQ_DESC; i++) { 1098 u32 *data = (u32 *)&bp->eq_ring[i].message.data; 1099 1100 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n", 1101 i, bp->eq_ring[i].message.opcode, 1102 bp->eq_ring[i].message.error); 1103 BNX2X_ERR("data: %x %x %x\n", 1104 data[0], data[1], data[2]); 1105 } 1106 } 1107 1108 /* Rings */ 1109 /* Rx */ 1110 for_each_valid_rx_queue(bp, i) { 1111 struct bnx2x_fastpath *fp = &bp->fp[i]; 1112 1113 if (!bp->fp) 1114 break; 1115 1116 if (!fp->rx_cons_sb) 1117 continue; 1118 1119 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10); 1120 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503); 1121 for (j = start; j != end; j = RX_BD(j + 1)) { 1122 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j]; 1123 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j]; 1124 1125 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n", 1126 i, j, rx_bd[1], rx_bd[0], sw_bd->data); 1127 } 1128 1129 start = RX_SGE(fp->rx_sge_prod); 1130 end = RX_SGE(fp->last_max_sge); 1131 for (j = start; j != end; j = RX_SGE(j + 1)) { 1132 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j]; 1133 struct sw_rx_page *sw_page = &fp->rx_page_ring[j]; 1134 1135 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n", 1136 i, j, rx_sge[1], rx_sge[0], sw_page->page); 1137 } 1138 1139 start = RCQ_BD(fp->rx_comp_cons - 10); 1140 end = RCQ_BD(fp->rx_comp_cons + 503); 1141 for (j = start; j != end; j = RCQ_BD(j + 1)) { 1142 u32 *cqe = (u32 *)&fp->rx_comp_ring[j]; 1143 1144 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n", 1145 i, j, cqe[0], cqe[1], cqe[2], cqe[3]); 1146 } 1147 } 1148 1149 /* Tx */ 1150 for_each_valid_tx_queue(bp, i) { 1151 struct bnx2x_fastpath *fp = &bp->fp[i]; 1152 1153 if (!bp->fp) 1154 break; 1155 1156 for_each_cos_in_tx_queue(fp, cos) { 1157 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos]; 1158 1159 if (!fp->txdata_ptr[cos]) 1160 break; 1161 1162 if (!txdata->tx_cons_sb) 1163 continue; 1164 1165 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10); 1166 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245); 1167 for (j = start; j != end; j = TX_BD(j + 1)) { 1168 struct sw_tx_bd *sw_bd = 1169 &txdata->tx_buf_ring[j]; 1170 1171 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n", 1172 i, cos, j, sw_bd->skb, 1173 sw_bd->first_bd); 1174 } 1175 1176 start = TX_BD(txdata->tx_bd_cons - 10); 1177 end = TX_BD(txdata->tx_bd_cons + 254); 1178 for (j = start; j != end; j = TX_BD(j + 1)) { 1179 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 1180 1181 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n", 1182 i, cos, j, tx_bd[0], tx_bd[1], 1183 tx_bd[2], tx_bd[3]); 1184 } 1185 } 1186 } 1187#endif 1188 if (IS_PF(bp)) { 1189 int tmp_msg_en = bp->msg_enable; 1190 1191 bnx2x_fw_dump(bp); 1192 bp->msg_enable |= NETIF_MSG_HW; 1193 BNX2X_ERR("Idle check (1st round) ----------\n"); 1194 bnx2x_idle_chk(bp); 1195 BNX2X_ERR("Idle check (2nd round) ----------\n"); 1196 bnx2x_idle_chk(bp); 1197 bp->msg_enable = tmp_msg_en; 1198 bnx2x_mc_assert(bp); 1199 } 1200 1201 BNX2X_ERR("end crash dump -----------------\n"); 1202} 1203 1204/* 1205 * FLR Support for E2 1206 * 1207 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW 1208 * initialization. 1209 */ 1210#define FLR_WAIT_USEC 10000 /* 10 milliseconds */ 1211#define FLR_WAIT_INTERVAL 50 /* usec */ 1212#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */ 1213 1214struct pbf_pN_buf_regs { 1215 int pN; 1216 u32 init_crd; 1217 u32 crd; 1218 u32 crd_freed; 1219}; 1220 1221struct pbf_pN_cmd_regs { 1222 int pN; 1223 u32 lines_occup; 1224 u32 lines_freed; 1225}; 1226 1227static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, 1228 struct pbf_pN_buf_regs *regs, 1229 u32 poll_count) 1230{ 1231 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start; 1232 u32 cur_cnt = poll_count; 1233 1234 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); 1235 crd = crd_start = REG_RD(bp, regs->crd); 1236 init_crd = REG_RD(bp, regs->init_crd); 1237 1238 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 1239 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd); 1240 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 1241 1242 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) < 1243 (init_crd - crd_start))) { 1244 if (cur_cnt--) { 1245 udelay(FLR_WAIT_INTERVAL); 1246 crd = REG_RD(bp, regs->crd); 1247 crd_freed = REG_RD(bp, regs->crd_freed); 1248 } else { 1249 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n", 1250 regs->pN); 1251 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n", 1252 regs->pN, crd); 1253 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n", 1254 regs->pN, crd_freed); 1255 break; 1256 } 1257 } 1258 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n", 1259 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1260} 1261 1262static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, 1263 struct pbf_pN_cmd_regs *regs, 1264 u32 poll_count) 1265{ 1266 u32 occup, to_free, freed, freed_start; 1267 u32 cur_cnt = poll_count; 1268 1269 occup = to_free = REG_RD(bp, regs->lines_occup); 1270 freed = freed_start = REG_RD(bp, regs->lines_freed); 1271 1272 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 1273 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 1274 1275 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) { 1276 if (cur_cnt--) { 1277 udelay(FLR_WAIT_INTERVAL); 1278 occup = REG_RD(bp, regs->lines_occup); 1279 freed = REG_RD(bp, regs->lines_freed); 1280 } else { 1281 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n", 1282 regs->pN); 1283 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", 1284 regs->pN, occup); 1285 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", 1286 regs->pN, freed); 1287 break; 1288 } 1289 } 1290 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n", 1291 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 1292} 1293 1294static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, 1295 u32 expected, u32 poll_count) 1296{ 1297 u32 cur_cnt = poll_count; 1298 u32 val; 1299 1300 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) 1301 udelay(FLR_WAIT_INTERVAL); 1302 1303 return val; 1304} 1305 1306int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1307 char *msg, u32 poll_cnt) 1308{ 1309 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); 1310 if (val != 0) { 1311 BNX2X_ERR("%s usage count=%d\n", msg, val); 1312 return 1; 1313 } 1314 return 0; 1315} 1316 1317/* Common routines with VF FLR cleanup */ 1318u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) 1319{ 1320 /* adjust polling timeout */ 1321 if (CHIP_REV_IS_EMUL(bp)) 1322 return FLR_POLL_CNT * 2000; 1323 1324 if (CHIP_REV_IS_FPGA(bp)) 1325 return FLR_POLL_CNT * 120; 1326 1327 return FLR_POLL_CNT; 1328} 1329 1330void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) 1331{ 1332 struct pbf_pN_cmd_regs cmd_regs[] = { 1333 {0, (CHIP_IS_E3B0(bp)) ? 1334 PBF_REG_TQ_OCCUPANCY_Q0 : 1335 PBF_REG_P0_TQ_OCCUPANCY, 1336 (CHIP_IS_E3B0(bp)) ? 1337 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 1338 PBF_REG_P0_TQ_LINES_FREED_CNT}, 1339 {1, (CHIP_IS_E3B0(bp)) ? 1340 PBF_REG_TQ_OCCUPANCY_Q1 : 1341 PBF_REG_P1_TQ_OCCUPANCY, 1342 (CHIP_IS_E3B0(bp)) ? 1343 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 1344 PBF_REG_P1_TQ_LINES_FREED_CNT}, 1345 {4, (CHIP_IS_E3B0(bp)) ? 1346 PBF_REG_TQ_OCCUPANCY_LB_Q : 1347 PBF_REG_P4_TQ_OCCUPANCY, 1348 (CHIP_IS_E3B0(bp)) ? 1349 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 1350 PBF_REG_P4_TQ_LINES_FREED_CNT} 1351 }; 1352 1353 struct pbf_pN_buf_regs buf_regs[] = { 1354 {0, (CHIP_IS_E3B0(bp)) ? 1355 PBF_REG_INIT_CRD_Q0 : 1356 PBF_REG_P0_INIT_CRD , 1357 (CHIP_IS_E3B0(bp)) ? 1358 PBF_REG_CREDIT_Q0 : 1359 PBF_REG_P0_CREDIT, 1360 (CHIP_IS_E3B0(bp)) ? 1361 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 1362 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 1363 {1, (CHIP_IS_E3B0(bp)) ? 1364 PBF_REG_INIT_CRD_Q1 : 1365 PBF_REG_P1_INIT_CRD, 1366 (CHIP_IS_E3B0(bp)) ? 1367 PBF_REG_CREDIT_Q1 : 1368 PBF_REG_P1_CREDIT, 1369 (CHIP_IS_E3B0(bp)) ? 1370 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 1371 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 1372 {4, (CHIP_IS_E3B0(bp)) ? 1373 PBF_REG_INIT_CRD_LB_Q : 1374 PBF_REG_P4_INIT_CRD, 1375 (CHIP_IS_E3B0(bp)) ? 1376 PBF_REG_CREDIT_LB_Q : 1377 PBF_REG_P4_CREDIT, 1378 (CHIP_IS_E3B0(bp)) ? 1379 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 1380 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 1381 }; 1382 1383 int i; 1384 1385 /* Verify the command queues are flushed P0, P1, P4 */ 1386 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) 1387 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); 1388 1389 /* Verify the transmission buffers are flushed P0, P1, P4 */ 1390 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) 1391 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); 1392} 1393 1394#define OP_GEN_PARAM(param) \ 1395 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 1396 1397#define OP_GEN_TYPE(type) \ 1398 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 1399 1400#define OP_GEN_AGG_VECT(index) \ 1401 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 1402 1403int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) 1404{ 1405 u32 op_gen_command = 0; 1406 u32 comp_addr = BAR_CSTRORM_INTMEM + 1407 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func); 1408 1409 if (REG_RD(bp, comp_addr)) { 1410 BNX2X_ERR("Cleanup complete was not 0 before sending\n"); 1411 return 1; 1412 } 1413 1414 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 1415 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 1416 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 1417 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 1418 1419 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n"); 1420 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); 1421 1422 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1423 BNX2X_ERR("FW final cleanup did not succeed\n"); 1424 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n", 1425 (REG_RD(bp, comp_addr))); 1426 bnx2x_panic(); 1427 return 1; 1428 } 1429 /* Zero completion for next FLR */ 1430 REG_WR(bp, comp_addr, 0); 1431 1432 return 0; 1433} 1434 1435u8 bnx2x_is_pcie_pending(struct pci_dev *dev) 1436{ 1437 u16 status; 1438 1439 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status); 1440 return status & PCI_EXP_DEVSTA_TRPND; 1441} 1442 1443/* PF FLR specific routines 1444*/ 1445static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) 1446{ 1447 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 1448 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1449 CFC_REG_NUM_LCIDS_INSIDE_PF, 1450 "CFC PF usage counter timed out", 1451 poll_cnt)) 1452 return 1; 1453 1454 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 1455 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1456 DORQ_REG_PF_USAGE_CNT, 1457 "DQ PF usage counter timed out", 1458 poll_cnt)) 1459 return 1; 1460 1461 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 1462 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1463 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), 1464 "QM PF usage counter timed out", 1465 poll_cnt)) 1466 return 1; 1467 1468 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 1469 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1470 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), 1471 "Timers VNIC usage counter timed out", 1472 poll_cnt)) 1473 return 1; 1474 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1475 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), 1476 "Timers NUM_SCANS usage counter timed out", 1477 poll_cnt)) 1478 return 1; 1479 1480 /* Wait DMAE PF usage counter to zero */ 1481 if (bnx2x_flr_clnup_poll_hw_counter(bp, 1482 dmae_reg_go_c[INIT_DMAE_C(bp)], 1483 "DMAE command register timed out", 1484 poll_cnt)) 1485 return 1; 1486 1487 return 0; 1488} 1489 1490static void bnx2x_hw_enable_status(struct bnx2x *bp) 1491{ 1492 u32 val; 1493 1494 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); 1495 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 1496 1497 val = REG_RD(bp, PBF_REG_DISABLE_PF); 1498 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val); 1499 1500 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); 1501 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 1502 1503 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); 1504 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 1505 1506 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 1507 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 1508 1509 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 1510 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 1511 1512 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 1513 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 1514 1515 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1516 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", 1517 val); 1518} 1519 1520static int bnx2x_pf_flr_clnup(struct bnx2x *bp) 1521{ 1522 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); 1523 1524 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); 1525 1526 /* Re-enable PF target read access */ 1527 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1528 1529 /* Poll HW usage counters */ 1530 DP(BNX2X_MSG_SP, "Polling usage counters\n"); 1531 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) 1532 return -EBUSY; 1533 1534 /* Zero the igu 'trailing edge' and 'leading edge' */ 1535 1536 /* Send the FW cleanup command */ 1537 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) 1538 return -EBUSY; 1539 1540 /* ATC cleanup */ 1541 1542 /* Verify TX hw is flushed */ 1543 bnx2x_tx_hw_flushed(bp, poll_cnt); 1544 1545 /* Wait 100ms (not adjusted according to platform) */ 1546 msleep(100); 1547 1548 /* Verify no pending pci transactions */ 1549 if (bnx2x_is_pcie_pending(bp->pdev)) 1550 BNX2X_ERR("PCIE Transactions still pending\n"); 1551 1552 /* Debug */ 1553 bnx2x_hw_enable_status(bp); 1554 1555 /* 1556 * Master enable - Due to WB DMAE writes performed before this 1557 * register is re-initialized as part of the regular function init 1558 */ 1559 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 1560 1561 return 0; 1562} 1563 1564static void bnx2x_hc_int_enable(struct bnx2x *bp) 1565{ 1566 int port = BP_PORT(bp); 1567 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 1568 u32 val = REG_RD(bp, addr); 1569 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1570 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1571 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1572 1573 if (msix) { 1574 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1575 HC_CONFIG_0_REG_INT_LINE_EN_0); 1576 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1577 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1578 if (single_msix) 1579 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 1580 } else if (msi) { 1581 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 1582 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1583 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1584 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1585 } else { 1586 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 1587 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 1588 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1589 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1590 1591 if (!CHIP_IS_E1(bp)) { 1592 DP(NETIF_MSG_IFUP, 1593 "write %x to HC %d (addr 0x%x)\n", val, port, addr); 1594 1595 REG_WR(bp, addr, val); 1596 1597 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 1598 } 1599 } 1600 1601 if (CHIP_IS_E1(bp)) 1602 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1603 1604 DP(NETIF_MSG_IFUP, 1605 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr, 1606 (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1607 1608 REG_WR(bp, addr, val); 1609 /* 1610 * Ensure that HC_CONFIG is written before leading/trailing edge config 1611 */ 1612 barrier(); 1613 1614 if (!CHIP_IS_E1(bp)) { 1615 /* init leading/trailing edge */ 1616 if (IS_MF(bp)) { 1617 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1618 if (bp->port.pmf) 1619 /* enable nig and gpio3 attention */ 1620 val |= 0x1100; 1621 } else 1622 val = 0xffff; 1623 1624 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 1625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 1626 } 1627} 1628 1629static void bnx2x_igu_int_enable(struct bnx2x *bp) 1630{ 1631 u32 val; 1632 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; 1633 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; 1634 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; 1635 1636 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 1637 1638 if (msix) { 1639 val &= ~(IGU_PF_CONF_INT_LINE_EN | 1640 IGU_PF_CONF_SINGLE_ISR_EN); 1641 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1642 IGU_PF_CONF_ATTN_BIT_EN); 1643 1644 if (single_msix) 1645 val |= IGU_PF_CONF_SINGLE_ISR_EN; 1646 } else if (msi) { 1647 val &= ~IGU_PF_CONF_INT_LINE_EN; 1648 val |= (IGU_PF_CONF_MSI_MSIX_EN | 1649 IGU_PF_CONF_ATTN_BIT_EN | 1650 IGU_PF_CONF_SINGLE_ISR_EN); 1651 } else { 1652 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 1653 val |= (IGU_PF_CONF_INT_LINE_EN | 1654 IGU_PF_CONF_ATTN_BIT_EN | 1655 IGU_PF_CONF_SINGLE_ISR_EN); 1656 } 1657 1658 /* Clean previous status - need to configure igu prior to ack*/ 1659 if ((!msix) || single_msix) { 1660 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1661 bnx2x_ack_int(bp); 1662 } 1663 1664 val |= IGU_PF_CONF_FUNC_EN; 1665 1666 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n", 1667 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1668 1669 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1670 1671 if (val & IGU_PF_CONF_INT_LINE_EN) 1672 pci_intx(bp->pdev, true); 1673 1674 barrier(); 1675 1676 /* init leading/trailing edge */ 1677 if (IS_MF(bp)) { 1678 val = (0xee0f | (1 << (BP_VN(bp) + 4))); 1679 if (bp->port.pmf) 1680 /* enable nig and gpio3 attention */ 1681 val |= 0x1100; 1682 } else 1683 val = 0xffff; 1684 1685 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 1686 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 1687} 1688 1689void bnx2x_int_enable(struct bnx2x *bp) 1690{ 1691 if (bp->common.int_block == INT_BLOCK_HC) 1692 bnx2x_hc_int_enable(bp); 1693 else 1694 bnx2x_igu_int_enable(bp); 1695} 1696 1697void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) 1698{ 1699 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 1700 int i, offset; 1701 1702 if (disable_hw) 1703 /* prevent the HW from sending interrupts */ 1704 bnx2x_int_disable(bp); 1705 1706 /* make sure all ISRs are done */ 1707 if (msix) { 1708 synchronize_irq(bp->msix_table[0].vector); 1709 offset = 1; 1710 if (CNIC_SUPPORT(bp)) 1711 offset++; 1712 for_each_eth_queue(bp, i) 1713 synchronize_irq(bp->msix_table[offset++].vector); 1714 } else 1715 synchronize_irq(bp->pdev->irq); 1716 1717 /* make sure sp_task is not running */ 1718 cancel_delayed_work(&bp->sp_task); 1719 cancel_delayed_work(&bp->period_task); 1720 flush_workqueue(bnx2x_wq); 1721} 1722 1723/* fast path */ 1724 1725/* 1726 * General service functions 1727 */ 1728 1729/* Return true if succeeded to acquire the lock */ 1730static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) 1731{ 1732 u32 lock_status; 1733 u32 resource_bit = (1 << resource); 1734 int func = BP_FUNC(bp); 1735 u32 hw_lock_control_reg; 1736 1737 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1738 "Trying to take a lock on resource %d\n", resource); 1739 1740 /* Validating that the resource is within range */ 1741 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1742 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1743 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1744 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1745 return false; 1746 } 1747 1748 if (func <= 5) 1749 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 1750 else 1751 hw_lock_control_reg = 1752 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 1753 1754 /* Try to acquire the lock */ 1755 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 1756 lock_status = REG_RD(bp, hw_lock_control_reg); 1757 if (lock_status & resource_bit) 1758 return true; 1759 1760 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, 1761 "Failed to get a lock on resource %d\n", resource); 1762 return false; 1763} 1764 1765/** 1766 * bnx2x_get_leader_lock_resource - get the recovery leader resource id 1767 * 1768 * @bp: driver handle 1769 * 1770 * Returns the recovery leader resource id according to the engine this function 1771 * belongs to. Currently only only 2 engines is supported. 1772 */ 1773static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) 1774{ 1775 if (BP_PATH(bp)) 1776 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1; 1777 else 1778 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0; 1779} 1780 1781/** 1782 * bnx2x_trylock_leader_lock- try to acquire a leader lock. 1783 * 1784 * @bp: driver handle 1785 * 1786 * Tries to acquire a leader lock for current engine. 1787 */ 1788static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) 1789{ 1790 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 1791} 1792 1793static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1794 1795/* schedule the sp task and mark that interrupt occurred (runs from ISR) */ 1796static int bnx2x_schedule_sp_task(struct bnx2x *bp) 1797{ 1798 /* Set the interrupt occurred bit for the sp-task to recognize it 1799 * must ack the interrupt and transition according to the IGU 1800 * state machine. 1801 */ 1802 atomic_set(&bp->interrupt_occurred, 1); 1803 1804 /* The sp_task must execute only after this bit 1805 * is set, otherwise we will get out of sync and miss all 1806 * further interrupts. Hence, the barrier. 1807 */ 1808 smp_wmb(); 1809 1810 /* schedule sp_task to workqueue */ 1811 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); 1812} 1813 1814void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe) 1815{ 1816 struct bnx2x *bp = fp->bp; 1817 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1818 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 1819 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX; 1820 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 1821 1822 DP(BNX2X_MSG_SP, 1823 "fp %d cid %d got ramrod #%d state is %x type is %d\n", 1824 fp->index, cid, command, bp->state, 1825 rr_cqe->ramrod_cqe.ramrod_type); 1826 1827 /* If cid is within VF range, replace the slowpath object with the 1828 * one corresponding to this VF 1829 */ 1830 if (cid >= BNX2X_FIRST_VF_CID && 1831 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS) 1832 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); 1833 1834 switch (command) { 1835 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 1836 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid); 1837 drv_cmd = BNX2X_Q_CMD_UPDATE; 1838 break; 1839 1840 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 1841 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid); 1842 drv_cmd = BNX2X_Q_CMD_SETUP; 1843 break; 1844 1845 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1846 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1847 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1848 break; 1849 1850 case (RAMROD_CMD_ID_ETH_HALT): 1851 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid); 1852 drv_cmd = BNX2X_Q_CMD_HALT; 1853 break; 1854 1855 case (RAMROD_CMD_ID_ETH_TERMINATE): 1856 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid); 1857 drv_cmd = BNX2X_Q_CMD_TERMINATE; 1858 break; 1859 1860 case (RAMROD_CMD_ID_ETH_EMPTY): 1861 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid); 1862 drv_cmd = BNX2X_Q_CMD_EMPTY; 1863 break; 1864 1865 case (RAMROD_CMD_ID_ETH_TPA_UPDATE): 1866 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid); 1867 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA; 1868 break; 1869 1870 default: 1871 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n", 1872 command, fp->index); 1873 return; 1874 } 1875 1876 if ((drv_cmd != BNX2X_Q_CMD_MAX) && 1877 q_obj->complete_cmd(bp, q_obj, drv_cmd)) 1878 /* q_obj->complete_cmd() failure means that this was 1879 * an unexpected completion. 1880 * 1881 * In this case we don't want to increase the bp->spq_left 1882 * because apparently we haven't sent this command the first 1883 * place. 1884 */ 1885#ifdef BNX2X_STOP_ON_ERROR 1886 bnx2x_panic(); 1887#else 1888 return; 1889#endif 1890 1891 smp_mb__before_atomic(); 1892 atomic_inc(&bp->cq_spq_left); 1893 /* push the change in bp->spq_left and towards the memory */ 1894 smp_mb__after_atomic(); 1895 1896 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); 1897 1898 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 1899 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { 1900 /* if Q update ramrod is completed for last Q in AFEX vif set 1901 * flow, then ACK MCP at the end 1902 * 1903 * mark pending ACK to MCP bit. 1904 * prevent case that both bits are cleared. 1905 * At the end of load/unload driver checks that 1906 * sp_state is cleared, and this order prevents 1907 * races 1908 */ 1909 smp_mb__before_atomic(); 1910 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); 1911 wmb(); 1912 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 1913 smp_mb__after_atomic(); 1914 1915 /* schedule the sp task as mcp ack is required */ 1916 bnx2x_schedule_sp_task(bp); 1917 } 1918 1919 return; 1920} 1921 1922irqreturn_t bnx2x_interrupt(int irq, void *dev_instance) 1923{ 1924 struct bnx2x *bp = netdev_priv(dev_instance); 1925 u16 status = bnx2x_ack_int(bp); 1926 u16 mask; 1927 int i; 1928 u8 cos; 1929 1930 /* Return here if interrupt is shared and it's not for us */ 1931 if (unlikely(status == 0)) { 1932 DP(NETIF_MSG_INTR, "not our interrupt!\n"); 1933 return IRQ_NONE; 1934 } 1935 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status); 1936 1937#ifdef BNX2X_STOP_ON_ERROR 1938 if (unlikely(bp->panic)) 1939 return IRQ_HANDLED; 1940#endif 1941 1942 for_each_eth_queue(bp, i) { 1943 struct bnx2x_fastpath *fp = &bp->fp[i]; 1944 1945 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); 1946 if (status & mask) { 1947 /* Handle Rx or Tx according to SB id */ 1948 for_each_cos_in_tx_queue(fp, cos) 1949 prefetch(fp->txdata_ptr[cos]->tx_cons_sb); 1950 prefetch(&fp->sb_running_index[SM_RX_ID]); 1951 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); 1952 status &= ~mask; 1953 } 1954 } 1955 1956 if (CNIC_SUPPORT(bp)) { 1957 mask = 0x2; 1958 if (status & (mask | 0x1)) { 1959 struct cnic_ops *c_ops = NULL; 1960 1961 rcu_read_lock(); 1962 c_ops = rcu_dereference(bp->cnic_ops); 1963 if (c_ops && (bp->cnic_eth_dev.drv_state & 1964 CNIC_DRV_STATE_HANDLES_IRQ)) 1965 c_ops->cnic_handler(bp->cnic_data, NULL); 1966 rcu_read_unlock(); 1967 1968 status &= ~mask; 1969 } 1970 } 1971 1972 if (unlikely(status & 0x1)) { 1973 1974 /* schedule sp task to perform default status block work, ack 1975 * attentions and enable interrupts. 1976 */ 1977 bnx2x_schedule_sp_task(bp); 1978 1979 status &= ~0x1; 1980 if (!status) 1981 return IRQ_HANDLED; 1982 } 1983 1984 if (unlikely(status)) 1985 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 1986 status); 1987 1988 return IRQ_HANDLED; 1989} 1990 1991/* Link */ 1992 1993/* 1994 * General service functions 1995 */ 1996 1997int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) 1998{ 1999 u32 lock_status; 2000 u32 resource_bit = (1 << resource); 2001 int func = BP_FUNC(bp); 2002 u32 hw_lock_control_reg; 2003 int cnt; 2004 2005 /* Validating that the resource is within range */ 2006 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 2007 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 2008 resource, HW_LOCK_MAX_RESOURCE_VALUE); 2009 return -EINVAL; 2010 } 2011 2012 if (func <= 5) { 2013 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 2014 } else { 2015 hw_lock_control_reg = 2016 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 2017 } 2018 2019 /* Validating that the resource is not already taken */ 2020 lock_status = REG_RD(bp, hw_lock_control_reg); 2021 if (lock_status & resource_bit) { 2022 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n", 2023 lock_status, resource_bit); 2024 return -EEXIST; 2025 } 2026 2027 /* Try for 5 second every 5ms */ 2028 for (cnt = 0; cnt < 1000; cnt++) { 2029 /* Try to acquire the lock */ 2030 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); 2031 lock_status = REG_RD(bp, hw_lock_control_reg); 2032 if (lock_status & resource_bit) 2033 return 0; 2034 2035 usleep_range(5000, 10000); 2036 } 2037 BNX2X_ERR("Timeout\n"); 2038 return -EAGAIN; 2039} 2040 2041int bnx2x_release_leader_lock(struct bnx2x *bp) 2042{ 2043 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); 2044} 2045 2046int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 2047{ 2048 u32 lock_status; 2049 u32 resource_bit = (1 << resource); 2050 int func = BP_FUNC(bp); 2051 u32 hw_lock_control_reg; 2052 2053 /* Validating that the resource is within range */ 2054 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 2055 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 2056 resource, HW_LOCK_MAX_RESOURCE_VALUE); 2057 return -EINVAL; 2058 } 2059 2060 if (func <= 5) { 2061 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 2062 } else { 2063 hw_lock_control_reg = 2064 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 2065 } 2066 2067 /* Validating that the resource is currently taken */ 2068 lock_status = REG_RD(bp, hw_lock_control_reg); 2069 if (!(lock_status & resource_bit)) { 2070 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n", 2071 lock_status, resource_bit); 2072 return -EFAULT; 2073 } 2074 2075 REG_WR(bp, hw_lock_control_reg, resource_bit); 2076 return 0; 2077} 2078 2079int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) 2080{ 2081 /* The GPIO should be swapped if swap register is set and active */ 2082 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2083 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2084 int gpio_shift = gpio_num + 2085 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2086 u32 gpio_mask = (1 << gpio_shift); 2087 u32 gpio_reg; 2088 int value; 2089 2090 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2091 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2092 return -EINVAL; 2093 } 2094 2095 /* read GPIO value */ 2096 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2097 2098 /* get the requested pin value */ 2099 if ((gpio_reg & gpio_mask) == gpio_mask) 2100 value = 1; 2101 else 2102 value = 0; 2103 2104 return value; 2105} 2106 2107int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2108{ 2109 /* The GPIO should be swapped if swap register is set and active */ 2110 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2111 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2112 int gpio_shift = gpio_num + 2113 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2114 u32 gpio_mask = (1 << gpio_shift); 2115 u32 gpio_reg; 2116 2117 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2118 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2119 return -EINVAL; 2120 } 2121 2122 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2123 /* read GPIO and mask except the float bits */ 2124 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2125 2126 switch (mode) { 2127 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2128 DP(NETIF_MSG_LINK, 2129 "Set GPIO %d (shift %d) -> output low\n", 2130 gpio_num, gpio_shift); 2131 /* clear FLOAT and set CLR */ 2132 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2133 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2134 break; 2135 2136 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2137 DP(NETIF_MSG_LINK, 2138 "Set GPIO %d (shift %d) -> output high\n", 2139 gpio_num, gpio_shift); 2140 /* clear FLOAT and set SET */ 2141 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2142 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2143 break; 2144 2145 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2146 DP(NETIF_MSG_LINK, 2147 "Set GPIO %d (shift %d) -> input\n", 2148 gpio_num, gpio_shift); 2149 /* set FLOAT */ 2150 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2151 break; 2152 2153 default: 2154 break; 2155 } 2156 2157 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2158 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2159 2160 return 0; 2161} 2162 2163int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) 2164{ 2165 u32 gpio_reg = 0; 2166 int rc = 0; 2167 2168 /* Any port swapping should be handled by caller. */ 2169 2170 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2171 /* read GPIO and mask except the float bits */ 2172 gpio_reg = REG_RD(bp, MISC_REG_GPIO); 2173 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2174 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2175 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2176 2177 switch (mode) { 2178 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2179 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins); 2180 /* set CLR */ 2181 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2182 break; 2183 2184 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2185 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins); 2186 /* set SET */ 2187 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2188 break; 2189 2190 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2191 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins); 2192 /* set FLOAT */ 2193 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2194 break; 2195 2196 default: 2197 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode); 2198 rc = -EINVAL; 2199 break; 2200 } 2201 2202 if (rc == 0) 2203 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 2204 2205 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2206 2207 return rc; 2208} 2209 2210int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) 2211{ 2212 /* The GPIO should be swapped if swap register is set and active */ 2213 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 2214 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; 2215 int gpio_shift = gpio_num + 2216 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); 2217 u32 gpio_mask = (1 << gpio_shift); 2218 u32 gpio_reg; 2219 2220 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2221 BNX2X_ERR("Invalid GPIO %d\n", gpio_num); 2222 return -EINVAL; 2223 } 2224 2225 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2226 /* read GPIO int */ 2227 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); 2228 2229 switch (mode) { 2230 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2231 DP(NETIF_MSG_LINK, 2232 "Clear GPIO INT %d (shift %d) -> output low\n", 2233 gpio_num, gpio_shift); 2234 /* clear SET and set CLR */ 2235 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2236 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2237 break; 2238 2239 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2240 DP(NETIF_MSG_LINK, 2241 "Set GPIO INT %d (shift %d) -> output high\n", 2242 gpio_num, gpio_shift); 2243 /* clear CLR and set SET */ 2244 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2245 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2246 break; 2247 2248 default: 2249 break; 2250 } 2251 2252 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); 2253 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 2254 2255 return 0; 2256} 2257 2258static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) 2259{ 2260 u32 spio_reg; 2261 2262 /* Only 2 SPIOs are configurable */ 2263 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 2264 BNX2X_ERR("Invalid SPIO 0x%x\n", spio); 2265 return -EINVAL; 2266 } 2267 2268 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2269 /* read SPIO and mask except the float bits */ 2270 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 2271 2272 switch (mode) { 2273 case MISC_SPIO_OUTPUT_LOW: 2274 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio); 2275 /* clear FLOAT and set CLR */ 2276 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2277 spio_reg |= (spio << MISC_SPIO_CLR_POS); 2278 break; 2279 2280 case MISC_SPIO_OUTPUT_HIGH: 2281 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio); 2282 /* clear FLOAT and set SET */ 2283 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 2284 spio_reg |= (spio << MISC_SPIO_SET_POS); 2285 break; 2286 2287 case MISC_SPIO_INPUT_HI_Z: 2288 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio); 2289 /* set FLOAT */ 2290 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 2291 break; 2292 2293 default: 2294 break; 2295 } 2296 2297 REG_WR(bp, MISC_REG_SPIO, spio_reg); 2298 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 2299 2300 return 0; 2301} 2302 2303void bnx2x_calc_fc_adv(struct bnx2x *bp) 2304{ 2305 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); 2306 2307 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 2308 ADVERTISED_Pause); 2309 switch (bp->link_vars.ieee_fc & 2310 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 2311 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 2312 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 2313 ADVERTISED_Pause); 2314 break; 2315 2316 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 2317 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 2318 break; 2319 2320 default: 2321 break; 2322 } 2323} 2324 2325static void bnx2x_set_requested_fc(struct bnx2x *bp) 2326{ 2327 /* Initialize link parameters structure variables 2328 * It is recommended to turn off RX FC for jumbo frames 2329 * for better performance 2330 */ 2331 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) 2332 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; 2333 else 2334 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; 2335} 2336 2337static void bnx2x_init_dropless_fc(struct bnx2x *bp) 2338{ 2339 u32 pause_enabled = 0; 2340 2341 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { 2342 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) 2343 pause_enabled = 1; 2344 2345 REG_WR(bp, BAR_USTRORM_INTMEM + 2346 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), 2347 pause_enabled); 2348 } 2349 2350 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n", 2351 pause_enabled ? "enabled" : "disabled"); 2352} 2353 2354int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) 2355{ 2356 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); 2357 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; 2358 2359 if (!BP_NOMCP(bp)) { 2360 bnx2x_set_requested_fc(bp); 2361 bnx2x_acquire_phy_lock(bp); 2362 2363 if (load_mode == LOAD_DIAG) { 2364 struct link_params *lp = &bp->link_params; 2365 lp->loopback_mode = LOOPBACK_XGXS; 2366 /* Prefer doing PHY loopback at highest speed */ 2367 if (lp->req_line_speed[cfx_idx] < SPEED_20000) { 2368 if (lp->speed_cap_mask[cfx_idx] & 2369 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 2370 lp->req_line_speed[cfx_idx] = 2371 SPEED_20000; 2372 else if (lp->speed_cap_mask[cfx_idx] & 2373 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 2374 lp->req_line_speed[cfx_idx] = 2375 SPEED_10000; 2376 else 2377 lp->req_line_speed[cfx_idx] = 2378 SPEED_1000; 2379 } 2380 } 2381 2382 if (load_mode == LOAD_LOOPBACK_EXT) { 2383 struct link_params *lp = &bp->link_params; 2384 lp->loopback_mode = LOOPBACK_EXT; 2385 } 2386 2387 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2388 2389 bnx2x_release_phy_lock(bp); 2390 2391 bnx2x_init_dropless_fc(bp); 2392 2393 bnx2x_calc_fc_adv(bp); 2394 2395 if (bp->link_vars.link_up) { 2396 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2397 bnx2x_link_report(bp); 2398 } 2399 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2400 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; 2401 return rc; 2402 } 2403 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 2404 return -EINVAL; 2405} 2406 2407void bnx2x_link_set(struct bnx2x *bp) 2408{ 2409 if (!BP_NOMCP(bp)) { 2410 bnx2x_acquire_phy_lock(bp); 2411 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 2412 bnx2x_release_phy_lock(bp); 2413 2414 bnx2x_init_dropless_fc(bp); 2415 2416 bnx2x_calc_fc_adv(bp); 2417 } else 2418 BNX2X_ERR("Bootcode is missing - can not set link\n"); 2419} 2420 2421static void bnx2x__link_reset(struct bnx2x *bp) 2422{ 2423 if (!BP_NOMCP(bp)) { 2424 bnx2x_acquire_phy_lock(bp); 2425 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); 2426 bnx2x_release_phy_lock(bp); 2427 } else 2428 BNX2X_ERR("Bootcode is missing - can not reset link\n"); 2429} 2430 2431void bnx2x_force_link_reset(struct bnx2x *bp) 2432{ 2433 bnx2x_acquire_phy_lock(bp); 2434 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); 2435 bnx2x_release_phy_lock(bp); 2436} 2437 2438u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) 2439{ 2440 u8 rc = 0; 2441 2442 if (!BP_NOMCP(bp)) { 2443 bnx2x_acquire_phy_lock(bp); 2444 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, 2445 is_serdes); 2446 bnx2x_release_phy_lock(bp); 2447 } else 2448 BNX2X_ERR("Bootcode is missing - can not test link\n"); 2449 2450 return rc; 2451} 2452 2453/* Calculates the sum of vn_min_rates. 2454 It's needed for further normalizing of the min_rates. 2455 Returns: 2456 sum of vn_min_rates. 2457 or 2458 0 - if all the min_rates are 0. 2459 In the later case fairness algorithm should be deactivated. 2460 If not all min_rates are zero then those that are zeroes will be set to 1. 2461 */ 2462static void bnx2x_calc_vn_min(struct bnx2x *bp, 2463 struct cmng_init_input *input) 2464{ 2465 int all_zero = 1; 2466 int vn; 2467 2468 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2469 u32 vn_cfg = bp->mf_config[vn]; 2470 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2471 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2472 2473 /* Skip hidden vns */ 2474 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2475 vn_min_rate = 0; 2476 /* If min rate is zero - set it to 1 */ 2477 else if (!vn_min_rate) 2478 vn_min_rate = DEF_MIN_RATE; 2479 else 2480 all_zero = 0; 2481 2482 input->vnic_min_rate[vn] = vn_min_rate; 2483 } 2484 2485 /* if ETS or all min rates are zeros - disable fairness */ 2486 if (BNX2X_IS_ETS_ENABLED(bp)) { 2487 input->flags.cmng_enables &= 2488 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2489 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n"); 2490 } else if (all_zero) { 2491 input->flags.cmng_enables &= 2492 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2493 DP(NETIF_MSG_IFUP, 2494 "All MIN values are zeroes fairness will be disabled\n"); 2495 } else 2496 input->flags.cmng_enables |= 2497 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2498} 2499 2500static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, 2501 struct cmng_init_input *input) 2502{ 2503 u16 vn_max_rate; 2504 u32 vn_cfg = bp->mf_config[vn]; 2505 2506 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) 2507 vn_max_rate = 0; 2508 else { 2509 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); 2510 2511 if (IS_MF_PERCENT_BW(bp)) { 2512 /* maxCfg in percents of linkspeed */ 2513 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; 2514 } else /* SD modes */ 2515 /* maxCfg is absolute in 100Mb units */ 2516 vn_max_rate = maxCfg * 100; 2517 } 2518 2519 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 2520 2521 input->vnic_max_rate[vn] = vn_max_rate; 2522} 2523 2524static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) 2525{ 2526 if (CHIP_REV_IS_SLOW(bp)) 2527 return CMNG_FNS_NONE; 2528 if (IS_MF(bp)) 2529 return CMNG_FNS_MINMAX; 2530 2531 return CMNG_FNS_NONE; 2532} 2533 2534void bnx2x_read_mf_cfg(struct bnx2x *bp) 2535{ 2536 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); 2537 2538 if (BP_NOMCP(bp)) 2539 return; /* what should be the default value in this case */ 2540 2541 /* For 2 port configuration the absolute function number formula 2542 * is: 2543 * abs_func = 2 * vn + BP_PORT + BP_PATH 2544 * 2545 * and there are 4 functions per port 2546 * 2547 * For 4 port configuration it is 2548 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH 2549 * 2550 * and there are 2 functions per port 2551 */ 2552 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2553 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2554 2555 if (func >= E1H_FUNC_MAX) 2556 break; 2557 2558 bp->mf_config[vn] = 2559 MF_CFG_RD(bp, func_mf_config[func].config); 2560 } 2561 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 2562 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n"); 2563 bp->flags |= MF_FUNC_DIS; 2564 } else { 2565 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 2566 bp->flags &= ~MF_FUNC_DIS; 2567 } 2568} 2569 2570static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) 2571{ 2572 struct cmng_init_input input; 2573 memset(&input, 0, sizeof(struct cmng_init_input)); 2574 2575 input.port_rate = bp->link_vars.line_speed; 2576 2577 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) { 2578 int vn; 2579 2580 /* read mf conf from shmem */ 2581 if (read_cfg) 2582 bnx2x_read_mf_cfg(bp); 2583 2584 /* vn_weight_sum and enable fairness if not 0 */ 2585 bnx2x_calc_vn_min(bp, &input); 2586 2587 /* calculate and set min-max rate for each vn */ 2588 if (bp->port.pmf) 2589 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) 2590 bnx2x_calc_vn_max(bp, vn, &input); 2591 2592 /* always enable rate shaping and fairness */ 2593 input.flags.cmng_enables |= 2594 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 2595 2596 bnx2x_init_cmng(&input, &bp->cmng); 2597 return; 2598 } 2599 2600 /* rate shaping and fairness are disabled */ 2601 DP(NETIF_MSG_IFUP, 2602 "rate shaping and fairness are disabled\n"); 2603} 2604 2605static void storm_memset_cmng(struct bnx2x *bp, 2606 struct cmng_init *cmng, 2607 u8 port) 2608{ 2609 int vn; 2610 size_t size = sizeof(struct cmng_struct_per_port); 2611 2612 u32 addr = BAR_XSTRORM_INTMEM + 2613 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 2614 2615 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); 2616 2617 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 2618 int func = func_by_vn(bp, vn); 2619 2620 addr = BAR_XSTRORM_INTMEM + 2621 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func); 2622 size = sizeof(struct rate_shaping_vars_per_vn); 2623 __storm_memset_struct(bp, addr, size, 2624 (u32 *)&cmng->vnic.vnic_max_rate[vn]); 2625 2626 addr = BAR_XSTRORM_INTMEM + 2627 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func); 2628 size = sizeof(struct fairness_vars_per_vn); 2629 __storm_memset_struct(bp, addr, size, 2630 (u32 *)&cmng->vnic.vnic_min_rate[vn]); 2631 } 2632} 2633 2634/* init cmng mode in HW according to local configuration */ 2635void bnx2x_set_local_cmng(struct bnx2x *bp) 2636{ 2637 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); 2638 2639 if (cmng_fns != CMNG_FNS_NONE) { 2640 bnx2x_cmng_fns_init(bp, false, cmng_fns); 2641 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 2642 } else { 2643 /* rate shaping and fairness are disabled */ 2644 DP(NETIF_MSG_IFUP, 2645 "single function mode without fairness\n"); 2646 } 2647} 2648 2649/* This function is called upon link interrupt */ 2650static void bnx2x_link_attn(struct bnx2x *bp) 2651{ 2652 /* Make sure that we are synced with the current statistics */ 2653 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2654 2655 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2656 2657 bnx2x_init_dropless_fc(bp); 2658 2659 if (bp->link_vars.link_up) { 2660 2661 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { 2662 struct host_port_stats *pstats; 2663 2664 pstats = bnx2x_sp(bp, port_stats); 2665 /* reset old mac stats */ 2666 memset(&(pstats->mac_stx[0]), 0, 2667 sizeof(struct mac_stx)); 2668 } 2669 if (bp->state == BNX2X_STATE_OPEN) 2670 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2671 } 2672 2673 if (bp->link_vars.link_up && bp->link_vars.line_speed) 2674 bnx2x_set_local_cmng(bp); 2675 2676 __bnx2x_link_report(bp); 2677 2678 if (IS_MF(bp)) 2679 bnx2x_link_sync_notify(bp); 2680} 2681 2682void bnx2x__link_status_update(struct bnx2x *bp) 2683{ 2684 if (bp->state != BNX2X_STATE_OPEN) 2685 return; 2686 2687 /* read updated dcb configuration */ 2688 if (IS_PF(bp)) { 2689 bnx2x_dcbx_pmf_update(bp); 2690 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); 2691 if (bp->link_vars.link_up) 2692 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2693 else 2694 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2695 /* indicate link status */ 2696 bnx2x_link_report(bp); 2697 2698 } else { /* VF */ 2699 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | 2700 SUPPORTED_10baseT_Full | 2701 SUPPORTED_100baseT_Half | 2702 SUPPORTED_100baseT_Full | 2703 SUPPORTED_1000baseT_Full | 2704 SUPPORTED_2500baseX_Full | 2705 SUPPORTED_10000baseT_Full | 2706 SUPPORTED_TP | 2707 SUPPORTED_FIBRE | 2708 SUPPORTED_Autoneg | 2709 SUPPORTED_Pause | 2710 SUPPORTED_Asym_Pause); 2711 bp->port.advertising[0] = bp->port.supported[0]; 2712 2713 bp->link_params.bp = bp; 2714 bp->link_params.port = BP_PORT(bp); 2715 bp->link_params.req_duplex[0] = DUPLEX_FULL; 2716 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; 2717 bp->link_params.req_line_speed[0] = SPEED_10000; 2718 bp->link_params.speed_cap_mask[0] = 0x7f0000; 2719 bp->link_params.switch_cfg = SWITCH_CFG_10G; 2720 bp->link_vars.mac_type = MAC_TYPE_BMAC; 2721 bp->link_vars.line_speed = SPEED_10000; 2722 bp->link_vars.link_status = 2723 (LINK_STATUS_LINK_UP | 2724 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 2725 bp->link_vars.link_up = 1; 2726 bp->link_vars.duplex = DUPLEX_FULL; 2727 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; 2728 __bnx2x_link_report(bp); 2729 2730 bnx2x_sample_bulletin(bp); 2731 2732 /* if bulletin board did not have an update for link status 2733 * __bnx2x_link_report will report current status 2734 * but it will NOT duplicate report in case of already reported 2735 * during sampling bulletin board. 2736 */ 2737 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); 2738 } 2739} 2740 2741static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, 2742 u16 vlan_val, u8 allowed_prio) 2743{ 2744 struct bnx2x_func_state_params func_params = {NULL}; 2745 struct bnx2x_func_afex_update_params *f_update_params = 2746 &func_params.params.afex_update; 2747 2748 func_params.f_obj = &bp->func_obj; 2749 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE; 2750 2751 /* no need to wait for RAMROD completion, so don't 2752 * set RAMROD_COMP_WAIT flag 2753 */ 2754 2755 f_update_params->vif_id = vifid; 2756 f_update_params->afex_default_vlan = vlan_val; 2757 f_update_params->allowed_priorities = allowed_prio; 2758 2759 /* if ramrod can not be sent, response to MCP immediately */ 2760 if (bnx2x_func_state_change(bp, &func_params) < 0) 2761 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 2762 2763 return 0; 2764} 2765 2766static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, 2767 u16 vif_index, u8 func_bit_map) 2768{ 2769 struct bnx2x_func_state_params func_params = {NULL}; 2770 struct bnx2x_func_afex_viflists_params *update_params = 2771 &func_params.params.afex_viflists; 2772 int rc; 2773 u32 drv_msg_code; 2774 2775 /* validate only LIST_SET and LIST_GET are received from switch */ 2776 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET)) 2777 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n", 2778 cmd_type); 2779 2780 func_params.f_obj = &bp->func_obj; 2781 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS; 2782 2783 /* set parameters according to cmd_type */ 2784 update_params->afex_vif_list_command = cmd_type; 2785 update_params->vif_list_index = vif_index; 2786 update_params->func_bit_map = 2787 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map; 2788 update_params->func_to_clear = 0; 2789 drv_msg_code = 2790 (cmd_type == VIF_LIST_RULE_GET) ? 2791 DRV_MSG_CODE_AFEX_LISTGET_ACK : 2792 DRV_MSG_CODE_AFEX_LISTSET_ACK; 2793 2794 /* if ramrod can not be sent, respond to MCP immediately for 2795 * SET and GET requests (other are not triggered from MCP) 2796 */ 2797 rc = bnx2x_func_state_change(bp, &func_params); 2798 if (rc < 0) 2799 bnx2x_fw_command(bp, drv_msg_code, 0); 2800 2801 return 0; 2802} 2803 2804static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) 2805{ 2806 struct afex_stats afex_stats; 2807 u32 func = BP_ABS_FUNC(bp); 2808 u32 mf_config; 2809 u16 vlan_val; 2810 u32 vlan_prio; 2811 u16 vif_id; 2812 u8 allowed_prio; 2813 u8 vlan_mode; 2814 u32 addr_to_write, vifid, addrs, stats_type, i; 2815 2816 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) { 2817 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2818 DP(BNX2X_MSG_MCP, 2819 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid); 2820 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); 2821 } 2822 2823 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) { 2824 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2825 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); 2826 DP(BNX2X_MSG_MCP, 2827 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n", 2828 vifid, addrs); 2829 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, 2830 addrs); 2831 } 2832 2833 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) { 2834 addr_to_write = SHMEM2_RD(bp, 2835 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); 2836 stats_type = SHMEM2_RD(bp, 2837 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); 2838 2839 DP(BNX2X_MSG_MCP, 2840 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n", 2841 addr_to_write); 2842 2843 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); 2844 2845 /* write response to scratchpad, for MCP */ 2846 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++) 2847 REG_WR(bp, addr_to_write + i*sizeof(u32), 2848 *(((u32 *)(&afex_stats))+i)); 2849 2850 /* send ack message to MCP */ 2851 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); 2852 } 2853 2854 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) { 2855 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); 2856 bp->mf_config[BP_VN(bp)] = mf_config; 2857 DP(BNX2X_MSG_MCP, 2858 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n", 2859 mf_config); 2860 2861 /* if VIF_SET is "enabled" */ 2862 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) { 2863 /* set rate limit directly to internal RAM */ 2864 struct cmng_init_input cmng_input; 2865 struct rate_shaping_vars_per_vn m_rs_vn; 2866 size_t size = sizeof(struct rate_shaping_vars_per_vn); 2867 u32 addr = BAR_XSTRORM_INTMEM + 2868 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); 2869 2870 bp->mf_config[BP_VN(bp)] = mf_config; 2871 2872 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); 2873 m_rs_vn.vn_counter.rate = 2874 cmng_input.vnic_max_rate[BP_VN(bp)]; 2875 m_rs_vn.vn_counter.quota = 2876 (m_rs_vn.vn_counter.rate * 2877 RS_PERIODIC_TIMEOUT_USEC) / 8; 2878 2879 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); 2880 2881 /* read relevant values from mf_cfg struct in shmem */ 2882 vif_id = 2883 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2884 FUNC_MF_CFG_E1HOV_TAG_MASK) >> 2885 FUNC_MF_CFG_E1HOV_TAG_SHIFT; 2886 vlan_val = 2887 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2888 FUNC_MF_CFG_AFEX_VLAN_MASK) >> 2889 FUNC_MF_CFG_AFEX_VLAN_SHIFT; 2890 vlan_prio = (mf_config & 2891 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 2892 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT; 2893 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT); 2894 vlan_mode = 2895 (MF_CFG_RD(bp, 2896 func_mf_config[func].afex_config) & 2897 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 2898 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT; 2899 allowed_prio = 2900 (MF_CFG_RD(bp, 2901 func_mf_config[func].afex_config) & 2902 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 2903 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT; 2904 2905 /* send ramrod to FW, return in case of failure */ 2906 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, 2907 allowed_prio)) 2908 return; 2909 2910 bp->afex_def_vlan_tag = vlan_val; 2911 bp->afex_vlan_mode = vlan_mode; 2912 } else { 2913 /* notify link down because BP->flags is disabled */ 2914 bnx2x_link_report(bp); 2915 2916 /* send INVALID VIF ramrod to FW */ 2917 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); 2918 2919 /* Reset the default afex VLAN */ 2920 bp->afex_def_vlan_tag = -1; 2921 } 2922 } 2923} 2924 2925static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) 2926{ 2927 struct bnx2x_func_switch_update_params *switch_update_params; 2928 struct bnx2x_func_state_params func_params; 2929 2930 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params)); 2931 switch_update_params = &func_params.params.switch_update; 2932 func_params.f_obj = &bp->func_obj; 2933 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 2934 2935 /* Prepare parameters for function state transitions */ 2936 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 2937 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 2938 2939 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) { 2940 int func = BP_ABS_FUNC(bp); 2941 u32 val; 2942 2943 /* Re-learn the S-tag from shmem */ 2944 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 2945 FUNC_MF_CFG_E1HOV_TAG_MASK; 2946 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 2947 bp->mf_ov = val; 2948 } else { 2949 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n"); 2950 goto fail; 2951 } 2952 2953 /* Configure new S-tag in LLH */ 2954 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, 2955 bp->mf_ov); 2956 2957 /* Send Ramrod to update FW of change */ 2958 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG, 2959 &switch_update_params->changes); 2960 switch_update_params->vlan = bp->mf_ov; 2961 2962 if (bnx2x_func_state_change(bp, &func_params) < 0) { 2963 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n", 2964 bp->mf_ov); 2965 goto fail; 2966 } else { 2967 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", 2968 bp->mf_ov); 2969 } 2970 } else { 2971 goto fail; 2972 } 2973 2974 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); 2975 return; 2976fail: 2977 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); 2978} 2979 2980static void bnx2x_pmf_update(struct bnx2x *bp) 2981{ 2982 int port = BP_PORT(bp); 2983 u32 val; 2984 2985 bp->port.pmf = 1; 2986 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); 2987 2988 /* 2989 * We need the mb() to ensure the ordering between the writing to 2990 * bp->port.pmf here and reading it from the bnx2x_periodic_task(). 2991 */ 2992 smp_mb(); 2993 2994 /* queue a periodic task */ 2995 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); 2996 2997 bnx2x_dcbx_pmf_update(bp); 2998 2999 /* enable nig attention */ 3000 val = (0xff0f | (1 << (BP_VN(bp) + 4))); 3001 if (bp->common.int_block == INT_BLOCK_HC) { 3002 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 3003 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 3004 } else if (!CHIP_IS_E1x(bp)) { 3005 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); 3006 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); 3007 } 3008 3009 bnx2x_stats_handle(bp, STATS_EVENT_PMF); 3010} 3011 3012/* end of Link */ 3013 3014/* slow path */ 3015 3016/* 3017 * General service functions 3018 */ 3019 3020/* send the MCP a request, block until there is a reply */ 3021u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) 3022{ 3023 int mb_idx = BP_FW_MB_IDX(bp); 3024 u32 seq; 3025 u32 rc = 0; 3026 u32 cnt = 1; 3027 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; 3028 3029 mutex_lock(&bp->fw_mb_mutex); 3030 seq = ++bp->fw_seq; 3031 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); 3032 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); 3033 3034 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n", 3035 (command | seq), param); 3036 3037 do { 3038 /* let the FW do it's magic ... */ 3039 msleep(delay); 3040 3041 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); 3042 3043 /* Give the FW up to 5 second (500*10ms) */ 3044 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 3045 3046 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n", 3047 cnt*delay, rc, seq); 3048 3049 /* is this a reply to our command? */ 3050 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) 3051 rc &= FW_MSG_CODE_MASK; 3052 else { 3053 /* FW BUG! */ 3054 BNX2X_ERR("FW failed to respond!\n"); 3055 bnx2x_fw_dump(bp); 3056 rc = 0; 3057 } 3058 mutex_unlock(&bp->fw_mb_mutex); 3059 3060 return rc; 3061} 3062 3063static void storm_memset_func_cfg(struct bnx2x *bp, 3064 struct tstorm_eth_function_common_config *tcfg, 3065 u16 abs_fid) 3066{ 3067 size_t size = sizeof(struct tstorm_eth_function_common_config); 3068 3069 u32 addr = BAR_TSTRORM_INTMEM + 3070 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 3071 3072 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 3073} 3074 3075void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) 3076{ 3077 if (CHIP_IS_E1x(bp)) { 3078 struct tstorm_eth_function_common_config tcfg = {0}; 3079 3080 storm_memset_func_cfg(bp, &tcfg, p->func_id); 3081 } 3082 3083 /* Enable the function in the FW */ 3084 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); 3085 storm_memset_func_en(bp, p->func_id, 1); 3086 3087 /* spq */ 3088 if (p->spq_active) { 3089 storm_memset_spq_addr(bp, p->spq_map, p->func_id); 3090 REG_WR(bp, XSEM_REG_FAST_MEMORY + 3091 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod); 3092 } 3093} 3094 3095/** 3096 * bnx2x_get_common_flags - Return common flags 3097 * 3098 * @bp: device handle 3099 * @fp: queue handle 3100 * @zero_stats: TRUE if statistics zeroing is needed 3101 * 3102 * Return the flags that are common for the Tx-only and not normal connections. 3103 */ 3104static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, 3105 struct bnx2x_fastpath *fp, 3106 bool zero_stats) 3107{ 3108 unsigned long flags = 0; 3109 3110 /* PF driver will always initialize the Queue to an ACTIVE state */ 3111 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags); 3112 3113 /* tx only connections collect statistics (on the same index as the 3114 * parent connection). The statistics are zeroed when the parent 3115 * connection is initialized. 3116 */ 3117 3118 __set_bit(BNX2X_Q_FLG_STATS, &flags); 3119 if (zero_stats) 3120 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags); 3121 3122 if (bp->flags & TX_SWITCHING) 3123 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags); 3124 3125 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags); 3126 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags); 3127 3128#ifdef BNX2X_STOP_ON_ERROR 3129 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags); 3130#endif 3131 3132 return flags; 3133} 3134 3135static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, 3136 struct bnx2x_fastpath *fp, 3137 bool leading) 3138{ 3139 unsigned long flags = 0; 3140 3141 /* calculate other queue flags */ 3142 if (IS_MF_SD(bp)) 3143 __set_bit(BNX2X_Q_FLG_OV, &flags); 3144 3145 if (IS_FCOE_FP(fp)) { 3146 __set_bit(BNX2X_Q_FLG_FCOE, &flags); 3147 /* For FCoE - force usage of default priority (for afex) */ 3148 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags); 3149 } 3150 3151 if (fp->mode != TPA_MODE_DISABLED) { 3152 __set_bit(BNX2X_Q_FLG_TPA, &flags); 3153 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags); 3154 if (fp->mode == TPA_MODE_GRO) 3155 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags); 3156 } 3157 3158 if (leading) { 3159 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags); 3160 __set_bit(BNX2X_Q_FLG_MCAST, &flags); 3161 } 3162 3163 /* Always set HW VLAN stripping */ 3164 __set_bit(BNX2X_Q_FLG_VLAN, &flags); 3165 3166 /* configure silent vlan removal */ 3167 if (IS_MF_AFEX(bp)) 3168 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags); 3169 3170 return flags | bnx2x_get_common_flags(bp, fp, true); 3171} 3172 3173static void bnx2x_pf_q_prep_general(struct bnx2x *bp, 3174 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init, 3175 u8 cos) 3176{ 3177 gen_init->stat_id = bnx2x_stats_id(fp); 3178 gen_init->spcl_id = fp->cl_id; 3179 3180 /* Always use mini-jumbo MTU for FCoE L2 ring */ 3181 if (IS_FCOE_FP(fp)) 3182 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU; 3183 else 3184 gen_init->mtu = bp->dev->mtu; 3185 3186 gen_init->cos = cos; 3187 3188 gen_init->fp_hsi = ETH_FP_HSI_VERSION; 3189} 3190 3191static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, 3192 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause, 3193 struct bnx2x_rxq_setup_params *rxq_init) 3194{ 3195 u8 max_sge = 0; 3196 u16 sge_sz = 0; 3197 u16 tpa_agg_size = 0; 3198 3199 if (fp->mode != TPA_MODE_DISABLED) { 3200 pause->sge_th_lo = SGE_TH_LO(bp); 3201 pause->sge_th_hi = SGE_TH_HI(bp); 3202 3203 /* validate SGE ring has enough to cross high threshold */ 3204 WARN_ON(bp->dropless_fc && 3205 pause->sge_th_hi + FW_PREFETCH_CNT > 3206 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); 3207 3208 tpa_agg_size = TPA_AGG_SIZE; 3209 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> 3210 SGE_PAGE_SHIFT; 3211 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 3212 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT; 3213 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff); 3214 } 3215 3216 /* pause - not for e1 */ 3217 if (!CHIP_IS_E1(bp)) { 3218 pause->bd_th_lo = BD_TH_LO(bp); 3219 pause->bd_th_hi = BD_TH_HI(bp); 3220 3221 pause->rcq_th_lo = RCQ_TH_LO(bp); 3222 pause->rcq_th_hi = RCQ_TH_HI(bp); 3223 /* 3224 * validate that rings have enough entries to cross 3225 * high thresholds 3226 */ 3227 WARN_ON(bp->dropless_fc && 3228 pause->bd_th_hi + FW_PREFETCH_CNT > 3229 bp->rx_ring_size); 3230 WARN_ON(bp->dropless_fc && 3231 pause->rcq_th_hi + FW_PREFETCH_CNT > 3232 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); 3233 3234 pause->pri_map = 1; 3235 } 3236 3237 /* rxq setup */ 3238 rxq_init->dscr_map = fp->rx_desc_mapping; 3239 rxq_init->sge_map = fp->rx_sge_mapping; 3240 rxq_init->rcq_map = fp->rx_comp_mapping; 3241 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE; 3242 3243 /* This should be a maximum number of data bytes that may be 3244 * placed on the BD (not including paddings). 3245 */ 3246 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START - 3247 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING; 3248 3249 rxq_init->cl_qzone_id = fp->cl_qzone_id; 3250 rxq_init->tpa_agg_sz = tpa_agg_size; 3251 rxq_init->sge_buf_sz = sge_sz; 3252 rxq_init->max_sges_pkt = max_sge; 3253 rxq_init->rss_engine_id = BP_FUNC(bp); 3254 rxq_init->mcast_engine_id = BP_FUNC(bp); 3255 3256 /* Maximum number or simultaneous TPA aggregation for this Queue. 3257 * 3258 * For PF Clients it should be the maximum available number. 3259 * VF driver(s) may want to define it to a smaller value. 3260 */ 3261 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); 3262 3263 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; 3264 rxq_init->fw_sb_id = fp->fw_sb_id; 3265 3266 if (IS_FCOE_FP(fp)) 3267 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS; 3268 else 3269 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 3270 /* configure silent vlan removal 3271 * if multi function mode is afex, then mask default vlan 3272 */ 3273 if (IS_MF_AFEX(bp)) { 3274 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; 3275 rxq_init->silent_removal_mask = VLAN_VID_MASK; 3276 } 3277} 3278 3279static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, 3280 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init, 3281 u8 cos) 3282{ 3283 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping; 3284 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 3285 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 3286 txq_init->fw_sb_id = fp->fw_sb_id; 3287 3288 /* 3289 * set the tss leading client id for TX classification == 3290 * leading RSS client id 3291 */ 3292 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); 3293 3294 if (IS_FCOE_FP(fp)) { 3295 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS; 3296 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE; 3297 } 3298} 3299 3300static void bnx2x_pf_init(struct bnx2x *bp) 3301{ 3302 struct bnx2x_func_init_params func_init = {0}; 3303 struct event_ring_data eq_data = { {0} }; 3304 3305 if (!CHIP_IS_E1x(bp)) { 3306 /* reset IGU PF statistics: MSIX + ATTN */ 3307 /* PF */ 3308 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3309 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3310 (CHIP_MODE_IS_4_PORT(bp) ? 3311 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3312 /* ATTN */ 3313 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 3314 BNX2X_IGU_STAS_MSG_VF_CNT*4 + 3315 BNX2X_IGU_STAS_MSG_PF_CNT*4 + 3316 (CHIP_MODE_IS_4_PORT(bp) ? 3317 BP_FUNC(bp) : BP_VN(bp))*4, 0); 3318 } 3319 3320 func_init.spq_active = true; 3321 func_init.pf_id = BP_FUNC(bp); 3322 func_init.func_id = BP_FUNC(bp); 3323 func_init.spq_map = bp->spq_mapping; 3324 func_init.spq_prod = bp->spq_prod_idx; 3325 3326 bnx2x_func_init(bp, &func_init); 3327 3328 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); 3329 3330 /* 3331 * Congestion management values depend on the link rate 3332 * There is no active link so initial link rate is set to 10 Gbps. 3333 * When the link comes up The congestion management values are 3334 * re-calculated according to the actual link rate. 3335 */ 3336 bp->link_vars.line_speed = SPEED_10000; 3337 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); 3338 3339 /* Only the PMF sets the HW */ 3340 if (bp->port.pmf) 3341 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3342 3343 /* init Event Queue - PCI bus guarantees correct endianity*/ 3344 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); 3345 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); 3346 eq_data.producer = bp->eq_prod; 3347 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 3348 eq_data.sb_id = DEF_SB_ID; 3349 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); 3350} 3351 3352static void bnx2x_e1h_disable(struct bnx2x *bp) 3353{ 3354 int port = BP_PORT(bp); 3355 3356 bnx2x_tx_disable(bp); 3357 3358 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 3359} 3360 3361static void bnx2x_e1h_enable(struct bnx2x *bp) 3362{ 3363 int port = BP_PORT(bp); 3364 3365 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 3366 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); 3367 3368 /* Tx queue should be only re-enabled */ 3369 netif_tx_wake_all_queues(bp->dev); 3370 3371 /* 3372 * Should not call netif_carrier_on since it will be called if the link 3373 * is up when checking for link state 3374 */ 3375} 3376 3377#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 3378 3379static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) 3380{ 3381 struct eth_stats_info *ether_stat = 3382 &bp->slowpath->drv_info_to_mcp.ether_stat; 3383 struct bnx2x_vlan_mac_obj *mac_obj = 3384 &bp->sp_objs->mac_obj; 3385 int i; 3386 3387 strscpy(ether_stat->version, DRV_MODULE_VERSION, 3388 ETH_STAT_INFO_VERSION_LEN); 3389 3390 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the 3391 * mac_local field in ether_stat struct. The base address is offset by 2 3392 * bytes to account for the field being 8 bytes but a mac address is 3393 * only 6 bytes. Likewise, the stride for the get_n_elements function is 3394 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes 3395 * allocated by the ether_stat struct, so the macs will land in their 3396 * proper positions. 3397 */ 3398 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++) 3399 memset(ether_stat->mac_local + i, 0, 3400 sizeof(ether_stat->mac_local[0])); 3401 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, 3402 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 3403 ether_stat->mac_local + MAC_PAD, MAC_PAD, 3404 ETH_ALEN); 3405 ether_stat->mtu_size = bp->dev->mtu; 3406 if (bp->dev->features & NETIF_F_RXCSUM) 3407 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 3408 if (bp->dev->features & NETIF_F_TSO) 3409 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 3410 ether_stat->feature_flags |= bp->common.boot_mode; 3411 3412 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; 3413 3414 ether_stat->txq_size = bp->tx_ring_size; 3415 ether_stat->rxq_size = bp->rx_ring_size; 3416 3417#ifdef CONFIG_BNX2X_SRIOV 3418 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; 3419#endif 3420} 3421 3422static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) 3423{ 3424 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3425 struct fcoe_stats_info *fcoe_stat = 3426 &bp->slowpath->drv_info_to_mcp.fcoe_stat; 3427 3428 if (!CNIC_LOADED(bp)) 3429 return; 3430 3431 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); 3432 3433 fcoe_stat->qos_priority = 3434 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE]; 3435 3436 /* insert FCoE stats from ramrod response */ 3437 if (!NO_FCOE(bp)) { 3438 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats = 3439 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3440 tstorm_queue_statistics; 3441 3442 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats = 3443 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. 3444 xstorm_queue_statistics; 3445 3446 struct fcoe_statistics_params *fw_fcoe_stat = 3447 &bp->fw_stats_data->fcoe; 3448 3449 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0, 3450 fcoe_stat->rx_bytes_lo, 3451 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt); 3452 3453 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3454 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi, 3455 fcoe_stat->rx_bytes_lo, 3456 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo); 3457 3458 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3459 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi, 3460 fcoe_stat->rx_bytes_lo, 3461 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo); 3462 3463 ADD_64_LE(fcoe_stat->rx_bytes_hi, 3464 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi, 3465 fcoe_stat->rx_bytes_lo, 3466 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo); 3467 3468 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3469 fcoe_stat->rx_frames_lo, 3470 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt); 3471 3472 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3473 fcoe_stat->rx_frames_lo, 3474 fcoe_q_tstorm_stats->rcv_ucast_pkts); 3475 3476 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3477 fcoe_stat->rx_frames_lo, 3478 fcoe_q_tstorm_stats->rcv_bcast_pkts); 3479 3480 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0, 3481 fcoe_stat->rx_frames_lo, 3482 fcoe_q_tstorm_stats->rcv_mcast_pkts); 3483 3484 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0, 3485 fcoe_stat->tx_bytes_lo, 3486 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt); 3487 3488 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3489 fcoe_q_xstorm_stats->ucast_bytes_sent.hi, 3490 fcoe_stat->tx_bytes_lo, 3491 fcoe_q_xstorm_stats->ucast_bytes_sent.lo); 3492 3493 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3494 fcoe_q_xstorm_stats->bcast_bytes_sent.hi, 3495 fcoe_stat->tx_bytes_lo, 3496 fcoe_q_xstorm_stats->bcast_bytes_sent.lo); 3497 3498 ADD_64_LE(fcoe_stat->tx_bytes_hi, 3499 fcoe_q_xstorm_stats->mcast_bytes_sent.hi, 3500 fcoe_stat->tx_bytes_lo, 3501 fcoe_q_xstorm_stats->mcast_bytes_sent.lo); 3502 3503 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3504 fcoe_stat->tx_frames_lo, 3505 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt); 3506 3507 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3508 fcoe_stat->tx_frames_lo, 3509 fcoe_q_xstorm_stats->ucast_pkts_sent); 3510 3511 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3512 fcoe_stat->tx_frames_lo, 3513 fcoe_q_xstorm_stats->bcast_pkts_sent); 3514 3515 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0, 3516 fcoe_stat->tx_frames_lo, 3517 fcoe_q_xstorm_stats->mcast_pkts_sent); 3518 } 3519 3520 /* ask L5 driver to add data to the struct */ 3521 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); 3522} 3523 3524static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) 3525{ 3526 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; 3527 struct iscsi_stats_info *iscsi_stat = 3528 &bp->slowpath->drv_info_to_mcp.iscsi_stat; 3529 3530 if (!CNIC_LOADED(bp)) 3531 return; 3532 3533 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, 3534 ETH_ALEN); 3535 3536 iscsi_stat->qos_priority = 3537 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI]; 3538 3539 /* ask L5 driver to add data to the struct */ 3540 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); 3541} 3542 3543/* called due to MCP event (on pmf): 3544 * reread new bandwidth configuration 3545 * configure FW 3546 * notify others function about the change 3547 */ 3548static void bnx2x_config_mf_bw(struct bnx2x *bp) 3549{ 3550 /* Workaround for MFW bug. 3551 * MFW is not supposed to generate BW attention in 3552 * single function mode. 3553 */ 3554 if (!IS_MF(bp)) { 3555 DP(BNX2X_MSG_MCP, 3556 "Ignoring MF BW config in single function mode\n"); 3557 return; 3558 } 3559 3560 if (bp->link_vars.link_up) { 3561 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); 3562 bnx2x_link_sync_notify(bp); 3563 } 3564 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); 3565} 3566 3567static void bnx2x_set_mf_bw(struct bnx2x *bp) 3568{ 3569 bnx2x_config_mf_bw(bp); 3570 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 3571} 3572 3573static void bnx2x_handle_eee_event(struct bnx2x *bp) 3574{ 3575 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n"); 3576 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 3577} 3578 3579#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20) 3580#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25) 3581 3582static void bnx2x_handle_drv_info_req(struct bnx2x *bp) 3583{ 3584 enum drv_info_opcode op_code; 3585 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); 3586 bool release = false; 3587 int wait; 3588 3589 /* if drv_info version supported by MFW doesn't match - send NACK */ 3590 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 3591 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3592 return; 3593 } 3594 3595 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 3596 DRV_INFO_CONTROL_OP_CODE_SHIFT; 3597 3598 /* Must prevent other flows from accessing drv_info_to_mcp */ 3599 mutex_lock(&bp->drv_info_mutex); 3600 3601 memset(&bp->slowpath->drv_info_to_mcp, 0, 3602 sizeof(union drv_info_to_mcp)); 3603 3604 switch (op_code) { 3605 case ETH_STATS_OPCODE: 3606 bnx2x_drv_info_ether_stat(bp); 3607 break; 3608 case FCOE_STATS_OPCODE: 3609 bnx2x_drv_info_fcoe_stat(bp); 3610 break; 3611 case ISCSI_STATS_OPCODE: 3612 bnx2x_drv_info_iscsi_stat(bp); 3613 break; 3614 default: 3615 /* if op code isn't supported - send NACK */ 3616 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); 3617 goto out; 3618 } 3619 3620 /* if we got drv_info attn from MFW then these fields are defined in 3621 * shmem2 for sure 3622 */ 3623 SHMEM2_WR(bp, drv_info_host_addr_lo, 3624 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3625 SHMEM2_WR(bp, drv_info_host_addr_hi, 3626 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); 3627 3628 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); 3629 3630 /* Since possible management wants both this and get_driver_version 3631 * need to wait until management notifies us it finished utilizing 3632 * the buffer. 3633 */ 3634 if (!SHMEM2_HAS(bp, mfw_drv_indication)) { 3635 DP(BNX2X_MSG_MCP, "Management does not support indication\n"); 3636 } else if (!bp->drv_info_mng_owner) { 3637 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); 3638 3639 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) { 3640 u32 indication = SHMEM2_RD(bp, mfw_drv_indication); 3641 3642 /* Management is done; need to clear indication */ 3643 if (indication & bit) { 3644 SHMEM2_WR(bp, mfw_drv_indication, 3645 indication & ~bit); 3646 release = true; 3647 break; 3648 } 3649 3650 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH); 3651 } 3652 } 3653 if (!release) { 3654 DP(BNX2X_MSG_MCP, "Management did not release indication\n"); 3655 bp->drv_info_mng_owner = true; 3656 } 3657 3658out: 3659 mutex_unlock(&bp->drv_info_mutex); 3660} 3661 3662static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format) 3663{ 3664 u8 vals[4]; 3665 int i = 0; 3666 3667 if (bnx2x_format) { 3668 i = sscanf(version, "1.%c%hhd.%hhd.%hhd", 3669 &vals[0], &vals[1], &vals[2], &vals[3]); 3670 if (i > 0) 3671 vals[0] -= '0'; 3672 } else { 3673 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd", 3674 &vals[0], &vals[1], &vals[2], &vals[3]); 3675 } 3676 3677 while (i < 4) 3678 vals[i++] = 0; 3679 3680 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3]; 3681} 3682 3683void bnx2x_update_mng_version(struct bnx2x *bp) 3684{ 3685 u32 iscsiver = DRV_VER_NOT_LOADED; 3686 u32 fcoever = DRV_VER_NOT_LOADED; 3687 u32 ethver = DRV_VER_NOT_LOADED; 3688 int idx = BP_FW_MB_IDX(bp); 3689 u8 *version; 3690 3691 if (!SHMEM2_HAS(bp, func_os_drv_ver)) 3692 return; 3693 3694 mutex_lock(&bp->drv_info_mutex); 3695 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */ 3696 if (bp->drv_info_mng_owner) 3697 goto out; 3698 3699 if (bp->state != BNX2X_STATE_OPEN) 3700 goto out; 3701 3702 /* Parse ethernet driver version */ 3703 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); 3704 if (!CNIC_LOADED(bp)) 3705 goto out; 3706 3707 /* Try getting storage driver version via cnic */ 3708 memset(&bp->slowpath->drv_info_to_mcp, 0, 3709 sizeof(union drv_info_to_mcp)); 3710 bnx2x_drv_info_iscsi_stat(bp); 3711 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; 3712 iscsiver = bnx2x_update_mng_version_utility(version, false); 3713 3714 memset(&bp->slowpath->drv_info_to_mcp, 0, 3715 sizeof(union drv_info_to_mcp)); 3716 bnx2x_drv_info_fcoe_stat(bp); 3717 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; 3718 fcoever = bnx2x_update_mng_version_utility(version, false); 3719 3720out: 3721 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); 3722 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); 3723 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); 3724 3725 mutex_unlock(&bp->drv_info_mutex); 3726 3727 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n", 3728 ethver, iscsiver, fcoever); 3729} 3730 3731void bnx2x_update_mfw_dump(struct bnx2x *bp) 3732{ 3733 u32 drv_ver; 3734 u32 valid_dump; 3735 3736 if (!SHMEM2_HAS(bp, drv_info)) 3737 return; 3738 3739 /* Update Driver load time, possibly broken in y2038 */ 3740 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds()); 3741 3742 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true); 3743 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver); 3744 3745 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM)); 3746 3747 /* Check & notify On-Chip dump. */ 3748 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump); 3749 3750 if (valid_dump & FIRST_DUMP_VALID) 3751 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n"); 3752 3753 if (valid_dump & SECOND_DUMP_VALID) 3754 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n"); 3755} 3756 3757static void bnx2x_oem_event(struct bnx2x *bp, u32 event) 3758{ 3759 u32 cmd_ok, cmd_fail; 3760 3761 /* sanity */ 3762 if (event & DRV_STATUS_DCC_EVENT_MASK && 3763 event & DRV_STATUS_OEM_EVENT_MASK) { 3764 BNX2X_ERR("Received simultaneous events %08x\n", event); 3765 return; 3766 } 3767 3768 if (event & DRV_STATUS_DCC_EVENT_MASK) { 3769 cmd_fail = DRV_MSG_CODE_DCC_FAILURE; 3770 cmd_ok = DRV_MSG_CODE_DCC_OK; 3771 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ { 3772 cmd_fail = DRV_MSG_CODE_OEM_FAILURE; 3773 cmd_ok = DRV_MSG_CODE_OEM_OK; 3774 } 3775 3776 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event); 3777 3778 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF | 3779 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) { 3780 /* This is the only place besides the function initialization 3781 * where the bp->flags can change so it is done without any 3782 * locks 3783 */ 3784 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3785 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n"); 3786 bp->flags |= MF_FUNC_DIS; 3787 3788 bnx2x_e1h_disable(bp); 3789 } else { 3790 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n"); 3791 bp->flags &= ~MF_FUNC_DIS; 3792 3793 bnx2x_e1h_enable(bp); 3794 } 3795 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF | 3796 DRV_STATUS_OEM_DISABLE_ENABLE_PF); 3797 } 3798 3799 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | 3800 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) { 3801 bnx2x_config_mf_bw(bp); 3802 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION | 3803 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION); 3804 } 3805 3806 /* Report results to MCP */ 3807 if (event) 3808 bnx2x_fw_command(bp, cmd_fail, 0); 3809 else 3810 bnx2x_fw_command(bp, cmd_ok, 0); 3811} 3812 3813/* must be called under the spq lock */ 3814static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) 3815{ 3816 struct eth_spe *next_spe = bp->spq_prod_bd; 3817 3818 if (bp->spq_prod_bd == bp->spq_last_bd) { 3819 bp->spq_prod_bd = bp->spq; 3820 bp->spq_prod_idx = 0; 3821 DP(BNX2X_MSG_SP, "end of spq\n"); 3822 } else { 3823 bp->spq_prod_bd++; 3824 bp->spq_prod_idx++; 3825 } 3826 return next_spe; 3827} 3828 3829/* must be called under the spq lock */ 3830static void bnx2x_sp_prod_update(struct bnx2x *bp) 3831{ 3832 int func = BP_FUNC(bp); 3833 3834 /* 3835 * Make sure that BD data is updated before writing the producer: 3836 * BD data is written to the memory, the producer is read from the 3837 * memory, thus we need a full memory barrier to ensure the ordering. 3838 */ 3839 mb(); 3840 3841 REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), 3842 bp->spq_prod_idx); 3843} 3844 3845/** 3846 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ 3847 * 3848 * @cmd: command to check 3849 * @cmd_type: command type 3850 */ 3851static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type) 3852{ 3853 if ((cmd_type == NONE_CONNECTION_TYPE) || 3854 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 3855 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 3856 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 3857 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 3858 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 3859 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) 3860 return true; 3861 else 3862 return false; 3863} 3864 3865/** 3866 * bnx2x_sp_post - place a single command on an SP ring 3867 * 3868 * @bp: driver handle 3869 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 3870 * @cid: SW CID the command is related to 3871 * @data_hi: command private data address (high 32 bits) 3872 * @data_lo: command private data address (low 32 bits) 3873 * @cmd_type: command type (e.g. NONE, ETH) 3874 * 3875 * SP data is handled as if it's always an address pair, thus data fields are 3876 * not swapped to little endian in upper functions. Instead this function swaps 3877 * data as if it's two u32 fields. 3878 */ 3879int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 3880 u32 data_hi, u32 data_lo, int cmd_type) 3881{ 3882 struct eth_spe *spe; 3883 u16 type; 3884 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3885 3886#ifdef BNX2X_STOP_ON_ERROR 3887 if (unlikely(bp->panic)) { 3888 BNX2X_ERR("Can't post SP when there is panic\n"); 3889 return -EIO; 3890 } 3891#endif 3892 3893 spin_lock_bh(&bp->spq_lock); 3894 3895 if (common) { 3896 if (!atomic_read(&bp->eq_spq_left)) { 3897 BNX2X_ERR("BUG! EQ ring full!\n"); 3898 spin_unlock_bh(&bp->spq_lock); 3899 bnx2x_panic(); 3900 return -EBUSY; 3901 } 3902 } else if (!atomic_read(&bp->cq_spq_left)) { 3903 BNX2X_ERR("BUG! SPQ ring full!\n"); 3904 spin_unlock_bh(&bp->spq_lock); 3905 bnx2x_panic(); 3906 return -EBUSY; 3907 } 3908 3909 spe = bnx2x_sp_get_next(bp); 3910 3911 /* CID needs port number to be encoded int it */ 3912 spe->hdr.conn_and_cmd_data = 3913 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) | 3914 HW_CID(bp, cid)); 3915 3916 /* In some cases, type may already contain the func-id 3917 * mainly in SRIOV related use cases, so we add it here only 3918 * if it's not already set. 3919 */ 3920 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) { 3921 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & 3922 SPE_HDR_CONN_TYPE; 3923 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & 3924 SPE_HDR_FUNCTION_ID); 3925 } else { 3926 type = cmd_type; 3927 } 3928 3929 spe->hdr.type = cpu_to_le16(type); 3930 3931 spe->data.update_data_addr.hi = cpu_to_le32(data_hi); 3932 spe->data.update_data_addr.lo = cpu_to_le32(data_lo); 3933 3934 /* 3935 * It's ok if the actual decrement is issued towards the memory 3936 * somewhere between the spin_lock and spin_unlock. Thus no 3937 * more explicit memory barrier is needed. 3938 */ 3939 if (common) 3940 atomic_dec(&bp->eq_spq_left); 3941 else 3942 atomic_dec(&bp->cq_spq_left); 3943 3944 DP(BNX2X_MSG_SP, 3945 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n", 3946 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3947 (u32)(U64_LO(bp->spq_mapping) + 3948 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3949 HW_CID(bp, cid), data_hi, data_lo, type, 3950 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); 3951 3952 bnx2x_sp_prod_update(bp); 3953 spin_unlock_bh(&bp->spq_lock); 3954 return 0; 3955} 3956 3957/* acquire split MCP access lock register */ 3958static int bnx2x_acquire_alr(struct bnx2x *bp) 3959{ 3960 u32 j, val; 3961 int rc = 0; 3962 3963 might_sleep(); 3964 for (j = 0; j < 1000; j++) { 3965 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); 3966 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); 3967 if (val & MCPR_ACCESS_LOCK_LOCK) 3968 break; 3969 3970 usleep_range(5000, 10000); 3971 } 3972 if (!(val & MCPR_ACCESS_LOCK_LOCK)) { 3973 BNX2X_ERR("Cannot acquire MCP access lock register\n"); 3974 rc = -EBUSY; 3975 } 3976 3977 return rc; 3978} 3979 3980/* release split MCP access lock register */ 3981static void bnx2x_release_alr(struct bnx2x *bp) 3982{ 3983 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); 3984} 3985 3986#define BNX2X_DEF_SB_ATT_IDX 0x0001 3987#define BNX2X_DEF_SB_IDX 0x0002 3988 3989static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) 3990{ 3991 struct host_sp_status_block *def_sb = bp->def_status_blk; 3992 u16 rc = 0; 3993 3994 barrier(); /* status block is written to by the chip */ 3995 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 3996 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 3997 rc |= BNX2X_DEF_SB_ATT_IDX; 3998 } 3999 4000 if (bp->def_idx != def_sb->sp_sb.running_index) { 4001 bp->def_idx = def_sb->sp_sb.running_index; 4002 rc |= BNX2X_DEF_SB_IDX; 4003 } 4004 4005 /* Do not reorder: indices reading should complete before handling */ 4006 barrier(); 4007 return rc; 4008} 4009 4010/* 4011 * slow path service functions 4012 */ 4013 4014static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) 4015{ 4016 int port = BP_PORT(bp); 4017 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4018 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4019 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 4020 NIG_REG_MASK_INTERRUPT_PORT0; 4021 u32 aeu_mask; 4022 u32 nig_mask = 0; 4023 u32 reg_addr; 4024 4025 if (bp->attn_state & asserted) 4026 BNX2X_ERR("IGU ERROR\n"); 4027 4028 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4029 aeu_mask = REG_RD(bp, aeu_addr); 4030 4031 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n", 4032 aeu_mask, asserted); 4033 aeu_mask &= ~(asserted & 0x3ff); 4034 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 4035 4036 REG_WR(bp, aeu_addr, aeu_mask); 4037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 4038 4039 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 4040 bp->attn_state |= asserted; 4041 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 4042 4043 if (asserted & ATTN_HARD_WIRED_MASK) { 4044 if (asserted & ATTN_NIG_FOR_FUNC) { 4045 4046 bnx2x_acquire_phy_lock(bp); 4047 4048 /* save nig interrupt mask */ 4049 nig_mask = REG_RD(bp, nig_int_mask_addr); 4050 4051 /* If nig_mask is not set, no need to call the update 4052 * function. 4053 */ 4054 if (nig_mask) { 4055 REG_WR(bp, nig_int_mask_addr, 0); 4056 4057 bnx2x_link_attn(bp); 4058 } 4059 4060 /* handle unicore attn? */ 4061 } 4062 if (asserted & ATTN_SW_TIMER_4_FUNC) 4063 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n"); 4064 4065 if (asserted & GPIO_2_FUNC) 4066 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n"); 4067 4068 if (asserted & GPIO_3_FUNC) 4069 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n"); 4070 4071 if (asserted & GPIO_4_FUNC) 4072 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n"); 4073 4074 if (port == 0) { 4075 if (asserted & ATTN_GENERAL_ATTN_1) { 4076 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n"); 4077 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 4078 } 4079 if (asserted & ATTN_GENERAL_ATTN_2) { 4080 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n"); 4081 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 4082 } 4083 if (asserted & ATTN_GENERAL_ATTN_3) { 4084 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n"); 4085 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 4086 } 4087 } else { 4088 if (asserted & ATTN_GENERAL_ATTN_4) { 4089 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n"); 4090 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 4091 } 4092 if (asserted & ATTN_GENERAL_ATTN_5) { 4093 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n"); 4094 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 4095 } 4096 if (asserted & ATTN_GENERAL_ATTN_6) { 4097 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n"); 4098 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 4099 } 4100 } 4101 4102 } /* if hardwired */ 4103 4104 if (bp->common.int_block == INT_BLOCK_HC) 4105 reg_addr = (HC_REG_COMMAND_REG + port*32 + 4106 COMMAND_REG_ATTN_BITS_SET); 4107 else 4108 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 4109 4110 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted, 4111 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 4112 REG_WR(bp, reg_addr, asserted); 4113 4114 /* now set back the mask */ 4115 if (asserted & ATTN_NIG_FOR_FUNC) { 4116 /* Verify that IGU ack through BAR was written before restoring 4117 * NIG mask. This loop should exit after 2-3 iterations max. 4118 */ 4119 if (bp->common.int_block != INT_BLOCK_HC) { 4120 u32 cnt = 0, igu_acked; 4121 do { 4122 igu_acked = REG_RD(bp, 4123 IGU_REG_ATTENTION_ACK_BITS); 4124 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 4125 (++cnt < MAX_IGU_ATTN_ACK_TO)); 4126 if (!igu_acked) 4127 DP(NETIF_MSG_HW, 4128 "Failed to verify IGU ack on time\n"); 4129 barrier(); 4130 } 4131 REG_WR(bp, nig_int_mask_addr, nig_mask); 4132 bnx2x_release_phy_lock(bp); 4133 } 4134} 4135 4136static void bnx2x_fan_failure(struct bnx2x *bp) 4137{ 4138 int port = BP_PORT(bp); 4139 u32 ext_phy_config; 4140 /* mark the failure */ 4141 ext_phy_config = 4142 SHMEM_RD(bp, 4143 dev_info.port_hw_config[port].external_phy_config); 4144 4145 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 4146 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 4147 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, 4148 ext_phy_config); 4149 4150 /* log the failure */ 4151 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n" 4152 "Please contact OEM Support for assistance\n"); 4153 4154 /* Schedule device reset (unload) 4155 * This is due to some boards consuming sufficient power when driver is 4156 * up to overheat if fan fails. 4157 */ 4158 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); 4159} 4160 4161static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) 4162{ 4163 int port = BP_PORT(bp); 4164 int reg_offset; 4165 u32 val; 4166 4167 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 4168 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 4169 4170 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 4171 4172 val = REG_RD(bp, reg_offset); 4173 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 4174 REG_WR(bp, reg_offset, val); 4175 4176 BNX2X_ERR("SPIO5 hw attention\n"); 4177 4178 /* Fan failure attention */ 4179 bnx2x_hw_reset_phy(&bp->link_params); 4180 bnx2x_fan_failure(bp); 4181 } 4182 4183 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { 4184 bnx2x_acquire_phy_lock(bp); 4185 bnx2x_handle_module_detect_int(&bp->link_params); 4186 bnx2x_release_phy_lock(bp); 4187 } 4188 4189 if (attn & HW_INTERRUPT_ASSERT_SET_0) { 4190 4191 val = REG_RD(bp, reg_offset); 4192 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0); 4193 REG_WR(bp, reg_offset, val); 4194 4195 BNX2X_ERR("FATAL HW block attention set0 0x%x\n", 4196 (u32)(attn & HW_INTERRUPT_ASSERT_SET_0)); 4197 bnx2x_panic(); 4198 } 4199} 4200 4201static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) 4202{ 4203 u32 val; 4204 4205 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 4206 4207 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); 4208 BNX2X_ERR("DB hw attention 0x%x\n", val); 4209 /* DORQ discard attention */ 4210 if (val & 0x2) 4211 BNX2X_ERR("FATAL error from DORQ\n"); 4212 } 4213 4214 if (attn & HW_INTERRUPT_ASSERT_SET_1) { 4215 4216 int port = BP_PORT(bp); 4217 int reg_offset; 4218 4219 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 4220 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 4221 4222 val = REG_RD(bp, reg_offset); 4223 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1); 4224 REG_WR(bp, reg_offset, val); 4225 4226 BNX2X_ERR("FATAL HW block attention set1 0x%x\n", 4227 (u32)(attn & HW_INTERRUPT_ASSERT_SET_1)); 4228 bnx2x_panic(); 4229 } 4230} 4231 4232static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) 4233{ 4234 u32 val; 4235 4236 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 4237 4238 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); 4239 BNX2X_ERR("CFC hw attention 0x%x\n", val); 4240 /* CFC error attention */ 4241 if (val & 0x2) 4242 BNX2X_ERR("FATAL error from CFC\n"); 4243 } 4244 4245 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 4246 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); 4247 BNX2X_ERR("PXP hw attention-0 0x%x\n", val); 4248 /* RQ_USDMDP_FIFO_OVERFLOW */ 4249 if (val & 0x18000) 4250 BNX2X_ERR("FATAL error from PXP\n"); 4251 4252 if (!CHIP_IS_E1x(bp)) { 4253 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); 4254 BNX2X_ERR("PXP hw attention-1 0x%x\n", val); 4255 } 4256 } 4257 4258 if (attn & HW_INTERRUPT_ASSERT_SET_2) { 4259 4260 int port = BP_PORT(bp); 4261 int reg_offset; 4262 4263 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 4264 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 4265 4266 val = REG_RD(bp, reg_offset); 4267 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2); 4268 REG_WR(bp, reg_offset, val); 4269 4270 BNX2X_ERR("FATAL HW block attention set2 0x%x\n", 4271 (u32)(attn & HW_INTERRUPT_ASSERT_SET_2)); 4272 bnx2x_panic(); 4273 } 4274} 4275 4276static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 4277{ 4278 u32 val; 4279 4280 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 4281 4282 if (attn & BNX2X_PMF_LINK_ASSERT) { 4283 int func = BP_FUNC(bp); 4284 4285 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 4286 bnx2x_read_mf_cfg(bp); 4287 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, 4288 func_mf_config[BP_ABS_FUNC(bp)].config); 4289 val = SHMEM_RD(bp, 4290 func_mb[BP_FW_MB_IDX(bp)].drv_status); 4291 4292 if (val & (DRV_STATUS_DCC_EVENT_MASK | 4293 DRV_STATUS_OEM_EVENT_MASK)) 4294 bnx2x_oem_event(bp, 4295 (val & (DRV_STATUS_DCC_EVENT_MASK | 4296 DRV_STATUS_OEM_EVENT_MASK))); 4297 4298 if (val & DRV_STATUS_SET_MF_BW) 4299 bnx2x_set_mf_bw(bp); 4300 4301 if (val & DRV_STATUS_DRV_INFO_REQ) 4302 bnx2x_handle_drv_info_req(bp); 4303 4304 if (val & DRV_STATUS_VF_DISABLED) 4305 bnx2x_schedule_iov_task(bp, 4306 BNX2X_IOV_HANDLE_FLR); 4307 4308 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 4309 bnx2x_pmf_update(bp); 4310 4311 if (bp->port.pmf && 4312 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 4313 bp->dcbx_enabled > 0) 4314 /* start dcbx state machine */ 4315 bnx2x_dcbx_set_params(bp, 4316 BNX2X_DCBX_STATE_NEG_RECEIVED); 4317 if (val & DRV_STATUS_AFEX_EVENT_MASK) 4318 bnx2x_handle_afex_cmd(bp, 4319 val & DRV_STATUS_AFEX_EVENT_MASK); 4320 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 4321 bnx2x_handle_eee_event(bp); 4322 4323 if (val & DRV_STATUS_OEM_UPDATE_SVID) 4324 bnx2x_schedule_sp_rtnl(bp, 4325 BNX2X_SP_RTNL_UPDATE_SVID, 0); 4326 4327 if (bp->link_vars.periodic_flags & 4328 PERIODIC_FLAGS_LINK_EVENT) { 4329 /* sync with link */ 4330 bnx2x_acquire_phy_lock(bp); 4331 bp->link_vars.periodic_flags &= 4332 ~PERIODIC_FLAGS_LINK_EVENT; 4333 bnx2x_release_phy_lock(bp); 4334 if (IS_MF(bp)) 4335 bnx2x_link_sync_notify(bp); 4336 bnx2x_link_report(bp); 4337 } 4338 /* Always call it here: bnx2x_link_report() will 4339 * prevent the link indication duplication. 4340 */ 4341 bnx2x__link_status_update(bp); 4342 } else if (attn & BNX2X_MC_ASSERT_BITS) { 4343 4344 BNX2X_ERR("MC assert!\n"); 4345 bnx2x_mc_assert(bp); 4346 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); 4347 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); 4348 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); 4349 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); 4350 bnx2x_panic(); 4351 4352 } else if (attn & BNX2X_MCP_ASSERT) { 4353 4354 BNX2X_ERR("MCP assert!\n"); 4355 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); 4356 bnx2x_fw_dump(bp); 4357 4358 } else 4359 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); 4360 } 4361 4362 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 4363 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn); 4364 if (attn & BNX2X_GRC_TIMEOUT) { 4365 val = CHIP_IS_E1(bp) ? 0 : 4366 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); 4367 BNX2X_ERR("GRC time-out 0x%08x\n", val); 4368 } 4369 if (attn & BNX2X_GRC_RSV) { 4370 val = CHIP_IS_E1(bp) ? 0 : 4371 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); 4372 BNX2X_ERR("GRC reserved 0x%08x\n", val); 4373 } 4374 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 4375 } 4376} 4377 4378/* 4379 * Bits map: 4380 * 0-7 - Engine0 load counter. 4381 * 8-15 - Engine1 load counter. 4382 * 16 - Engine0 RESET_IN_PROGRESS bit. 4383 * 17 - Engine1 RESET_IN_PROGRESS bit. 4384 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function 4385 * on the engine 4386 * 19 - Engine1 ONE_IS_LOADED. 4387 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 4388 * leader to complete (check for both RESET_IN_PROGRESS bits and not for 4389 * just the one belonging to its engine). 4390 * 4391 */ 4392#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 4393 4394#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff 4395#define BNX2X_PATH0_LOAD_CNT_SHIFT 0 4396#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00 4397#define BNX2X_PATH1_LOAD_CNT_SHIFT 8 4398#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000 4399#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000 4400#define BNX2X_GLOBAL_RESET_BIT 0x00040000 4401 4402/* 4403 * Set the GLOBAL_RESET bit. 4404 * 4405 * Should be run under rtnl lock 4406 */ 4407void bnx2x_set_reset_global(struct bnx2x *bp) 4408{ 4409 u32 val; 4410 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4411 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4412 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); 4413 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4414} 4415 4416/* 4417 * Clear the GLOBAL_RESET bit. 4418 * 4419 * Should be run under rtnl lock 4420 */ 4421static void bnx2x_clear_reset_global(struct bnx2x *bp) 4422{ 4423 u32 val; 4424 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4425 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4426 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); 4427 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4428} 4429 4430/* 4431 * Checks the GLOBAL_RESET bit. 4432 * 4433 * should be run under rtnl lock 4434 */ 4435static bool bnx2x_reset_is_global(struct bnx2x *bp) 4436{ 4437 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4438 4439 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 4440 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false; 4441} 4442 4443/* 4444 * Clear RESET_IN_PROGRESS bit for the current engine. 4445 * 4446 * Should be run under rtnl lock 4447 */ 4448static void bnx2x_set_reset_done(struct bnx2x *bp) 4449{ 4450 u32 val; 4451 u32 bit = BP_PATH(bp) ? 4452 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4453 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4454 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4455 4456 /* Clear the bit */ 4457 val &= ~bit; 4458 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4459 4460 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4461} 4462 4463/* 4464 * Set RESET_IN_PROGRESS for the current engine. 4465 * 4466 * should be run under rtnl lock 4467 */ 4468void bnx2x_set_reset_in_progress(struct bnx2x *bp) 4469{ 4470 u32 val; 4471 u32 bit = BP_PATH(bp) ? 4472 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4473 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4474 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4475 4476 /* Set the bit */ 4477 val |= bit; 4478 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4479 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4480} 4481 4482/* 4483 * Checks the RESET_IN_PROGRESS bit for the given engine. 4484 * should be run under rtnl lock 4485 */ 4486bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) 4487{ 4488 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4489 u32 bit = engine ? 4490 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT; 4491 4492 /* return false if bit is set */ 4493 return (val & bit) ? false : true; 4494} 4495 4496/* 4497 * set pf load for the current pf. 4498 * 4499 * should be run under rtnl lock 4500 */ 4501void bnx2x_set_pf_load(struct bnx2x *bp) 4502{ 4503 u32 val1, val; 4504 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4505 BNX2X_PATH0_LOAD_CNT_MASK; 4506 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4507 BNX2X_PATH0_LOAD_CNT_SHIFT; 4508 4509 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4510 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4511 4512 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val); 4513 4514 /* get the current counter value */ 4515 val1 = (val & mask) >> shift; 4516 4517 /* set bit of that PF */ 4518 val1 |= (1 << bp->pf_num); 4519 4520 /* clear the old value */ 4521 val &= ~mask; 4522 4523 /* set the new one */ 4524 val |= ((val1 << shift) & mask); 4525 4526 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4527 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4528} 4529 4530/** 4531 * bnx2x_clear_pf_load - clear pf load mark 4532 * 4533 * @bp: driver handle 4534 * 4535 * Should be run under rtnl lock. 4536 * Decrements the load counter for the current engine. Returns 4537 * whether other functions are still loaded 4538 */ 4539bool bnx2x_clear_pf_load(struct bnx2x *bp) 4540{ 4541 u32 val1, val; 4542 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : 4543 BNX2X_PATH0_LOAD_CNT_MASK; 4544 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4545 BNX2X_PATH0_LOAD_CNT_SHIFT; 4546 4547 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4548 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4549 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val); 4550 4551 /* get the current counter value */ 4552 val1 = (val & mask) >> shift; 4553 4554 /* clear bit of that PF */ 4555 val1 &= ~(1 << bp->pf_num); 4556 4557 /* clear the old value */ 4558 val &= ~mask; 4559 4560 /* set the new one */ 4561 val |= ((val1 << shift) & mask); 4562 4563 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); 4564 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 4565 return val1 != 0; 4566} 4567 4568/* 4569 * Read the load status for the current engine. 4570 * 4571 * should be run under rtnl lock 4572 */ 4573static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) 4574{ 4575 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK : 4576 BNX2X_PATH0_LOAD_CNT_MASK); 4577 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT : 4578 BNX2X_PATH0_LOAD_CNT_SHIFT); 4579 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 4580 4581 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val); 4582 4583 val = (val & mask) >> shift; 4584 4585 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n", 4586 engine, val); 4587 4588 return val != 0; 4589} 4590 4591static void _print_parity(struct bnx2x *bp, u32 reg) 4592{ 4593 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); 4594} 4595 4596static void _print_next_block(int idx, const char *blk) 4597{ 4598 pr_cont("%s%s", idx ? ", " : "", blk); 4599} 4600 4601static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, 4602 int *par_num, bool print) 4603{ 4604 u32 cur_bit; 4605 bool res; 4606 int i; 4607 4608 res = false; 4609 4610 for (i = 0; sig; i++) { 4611 cur_bit = (0x1UL << i); 4612 if (sig & cur_bit) { 4613 res |= true; /* Each bit is real error! */ 4614 4615 if (print) { 4616 switch (cur_bit) { 4617 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 4618 _print_next_block((*par_num)++, "BRB"); 4619 _print_parity(bp, 4620 BRB1_REG_BRB1_PRTY_STS); 4621 break; 4622 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 4623 _print_next_block((*par_num)++, 4624 "PARSER"); 4625 _print_parity(bp, PRS_REG_PRS_PRTY_STS); 4626 break; 4627 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 4628 _print_next_block((*par_num)++, "TSDM"); 4629 _print_parity(bp, 4630 TSDM_REG_TSDM_PRTY_STS); 4631 break; 4632 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 4633 _print_next_block((*par_num)++, 4634 "SEARCHER"); 4635 _print_parity(bp, SRC_REG_SRC_PRTY_STS); 4636 break; 4637 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 4638 _print_next_block((*par_num)++, "TCM"); 4639 _print_parity(bp, TCM_REG_TCM_PRTY_STS); 4640 break; 4641 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 4642 _print_next_block((*par_num)++, 4643 "TSEMI"); 4644 _print_parity(bp, 4645 TSEM_REG_TSEM_PRTY_STS_0); 4646 _print_parity(bp, 4647 TSEM_REG_TSEM_PRTY_STS_1); 4648 break; 4649 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 4650 _print_next_block((*par_num)++, "XPB"); 4651 _print_parity(bp, GRCBASE_XPB + 4652 PB_REG_PB_PRTY_STS); 4653 break; 4654 } 4655 } 4656 4657 /* Clear the bit */ 4658 sig &= ~cur_bit; 4659 } 4660 } 4661 4662 return res; 4663} 4664 4665static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, 4666 int *par_num, bool *global, 4667 bool print) 4668{ 4669 u32 cur_bit; 4670 bool res; 4671 int i; 4672 4673 res = false; 4674 4675 for (i = 0; sig; i++) { 4676 cur_bit = (0x1UL << i); 4677 if (sig & cur_bit) { 4678 res |= true; /* Each bit is real error! */ 4679 switch (cur_bit) { 4680 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 4681 if (print) { 4682 _print_next_block((*par_num)++, "PBF"); 4683 _print_parity(bp, PBF_REG_PBF_PRTY_STS); 4684 } 4685 break; 4686 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 4687 if (print) { 4688 _print_next_block((*par_num)++, "QM"); 4689 _print_parity(bp, QM_REG_QM_PRTY_STS); 4690 } 4691 break; 4692 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 4693 if (print) { 4694 _print_next_block((*par_num)++, "TM"); 4695 _print_parity(bp, TM_REG_TM_PRTY_STS); 4696 } 4697 break; 4698 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 4699 if (print) { 4700 _print_next_block((*par_num)++, "XSDM"); 4701 _print_parity(bp, 4702 XSDM_REG_XSDM_PRTY_STS); 4703 } 4704 break; 4705 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 4706 if (print) { 4707 _print_next_block((*par_num)++, "XCM"); 4708 _print_parity(bp, XCM_REG_XCM_PRTY_STS); 4709 } 4710 break; 4711 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 4712 if (print) { 4713 _print_next_block((*par_num)++, 4714 "XSEMI"); 4715 _print_parity(bp, 4716 XSEM_REG_XSEM_PRTY_STS_0); 4717 _print_parity(bp, 4718 XSEM_REG_XSEM_PRTY_STS_1); 4719 } 4720 break; 4721 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 4722 if (print) { 4723 _print_next_block((*par_num)++, 4724 "DOORBELLQ"); 4725 _print_parity(bp, 4726 DORQ_REG_DORQ_PRTY_STS); 4727 } 4728 break; 4729 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 4730 if (print) { 4731 _print_next_block((*par_num)++, "NIG"); 4732 if (CHIP_IS_E1x(bp)) { 4733 _print_parity(bp, 4734 NIG_REG_NIG_PRTY_STS); 4735 } else { 4736 _print_parity(bp, 4737 NIG_REG_NIG_PRTY_STS_0); 4738 _print_parity(bp, 4739 NIG_REG_NIG_PRTY_STS_1); 4740 } 4741 } 4742 break; 4743 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 4744 if (print) 4745 _print_next_block((*par_num)++, 4746 "VAUX PCI CORE"); 4747 *global = true; 4748 break; 4749 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 4750 if (print) { 4751 _print_next_block((*par_num)++, 4752 "DEBUG"); 4753 _print_parity(bp, DBG_REG_DBG_PRTY_STS); 4754 } 4755 break; 4756 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 4757 if (print) { 4758 _print_next_block((*par_num)++, "USDM"); 4759 _print_parity(bp, 4760 USDM_REG_USDM_PRTY_STS); 4761 } 4762 break; 4763 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 4764 if (print) { 4765 _print_next_block((*par_num)++, "UCM"); 4766 _print_parity(bp, UCM_REG_UCM_PRTY_STS); 4767 } 4768 break; 4769 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 4770 if (print) { 4771 _print_next_block((*par_num)++, 4772 "USEMI"); 4773 _print_parity(bp, 4774 USEM_REG_USEM_PRTY_STS_0); 4775 _print_parity(bp, 4776 USEM_REG_USEM_PRTY_STS_1); 4777 } 4778 break; 4779 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 4780 if (print) { 4781 _print_next_block((*par_num)++, "UPB"); 4782 _print_parity(bp, GRCBASE_UPB + 4783 PB_REG_PB_PRTY_STS); 4784 } 4785 break; 4786 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 4787 if (print) { 4788 _print_next_block((*par_num)++, "CSDM"); 4789 _print_parity(bp, 4790 CSDM_REG_CSDM_PRTY_STS); 4791 } 4792 break; 4793 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 4794 if (print) { 4795 _print_next_block((*par_num)++, "CCM"); 4796 _print_parity(bp, CCM_REG_CCM_PRTY_STS); 4797 } 4798 break; 4799 } 4800 4801 /* Clear the bit */ 4802 sig &= ~cur_bit; 4803 } 4804 } 4805 4806 return res; 4807} 4808 4809static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, 4810 int *par_num, bool print) 4811{ 4812 u32 cur_bit; 4813 bool res; 4814 int i; 4815 4816 res = false; 4817 4818 for (i = 0; sig; i++) { 4819 cur_bit = (0x1UL << i); 4820 if (sig & cur_bit) { 4821 res = true; /* Each bit is real error! */ 4822 if (print) { 4823 switch (cur_bit) { 4824 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 4825 _print_next_block((*par_num)++, 4826 "CSEMI"); 4827 _print_parity(bp, 4828 CSEM_REG_CSEM_PRTY_STS_0); 4829 _print_parity(bp, 4830 CSEM_REG_CSEM_PRTY_STS_1); 4831 break; 4832 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 4833 _print_next_block((*par_num)++, "PXP"); 4834 _print_parity(bp, PXP_REG_PXP_PRTY_STS); 4835 _print_parity(bp, 4836 PXP2_REG_PXP2_PRTY_STS_0); 4837 _print_parity(bp, 4838 PXP2_REG_PXP2_PRTY_STS_1); 4839 break; 4840 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 4841 _print_next_block((*par_num)++, 4842 "PXPPCICLOCKCLIENT"); 4843 break; 4844 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 4845 _print_next_block((*par_num)++, "CFC"); 4846 _print_parity(bp, 4847 CFC_REG_CFC_PRTY_STS); 4848 break; 4849 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 4850 _print_next_block((*par_num)++, "CDU"); 4851 _print_parity(bp, CDU_REG_CDU_PRTY_STS); 4852 break; 4853 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 4854 _print_next_block((*par_num)++, "DMAE"); 4855 _print_parity(bp, 4856 DMAE_REG_DMAE_PRTY_STS); 4857 break; 4858 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 4859 _print_next_block((*par_num)++, "IGU"); 4860 if (CHIP_IS_E1x(bp)) 4861 _print_parity(bp, 4862 HC_REG_HC_PRTY_STS); 4863 else 4864 _print_parity(bp, 4865 IGU_REG_IGU_PRTY_STS); 4866 break; 4867 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 4868 _print_next_block((*par_num)++, "MISC"); 4869 _print_parity(bp, 4870 MISC_REG_MISC_PRTY_STS); 4871 break; 4872 } 4873 } 4874 4875 /* Clear the bit */ 4876 sig &= ~cur_bit; 4877 } 4878 } 4879 4880 return res; 4881} 4882 4883static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, 4884 int *par_num, bool *global, 4885 bool print) 4886{ 4887 bool res = false; 4888 u32 cur_bit; 4889 int i; 4890 4891 for (i = 0; sig; i++) { 4892 cur_bit = (0x1UL << i); 4893 if (sig & cur_bit) { 4894 switch (cur_bit) { 4895 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 4896 if (print) 4897 _print_next_block((*par_num)++, 4898 "MCP ROM"); 4899 *global = true; 4900 res = true; 4901 break; 4902 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 4903 if (print) 4904 _print_next_block((*par_num)++, 4905 "MCP UMP RX"); 4906 *global = true; 4907 res = true; 4908 break; 4909 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 4910 if (print) 4911 _print_next_block((*par_num)++, 4912 "MCP UMP TX"); 4913 *global = true; 4914 res = true; 4915 break; 4916 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 4917 (*par_num)++; 4918 /* clear latched SCPAD PATIRY from MCP */ 4919 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 4920 1UL << 10); 4921 break; 4922 } 4923 4924 /* Clear the bit */ 4925 sig &= ~cur_bit; 4926 } 4927 } 4928 4929 return res; 4930} 4931 4932static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, 4933 int *par_num, bool print) 4934{ 4935 u32 cur_bit; 4936 bool res; 4937 int i; 4938 4939 res = false; 4940 4941 for (i = 0; sig; i++) { 4942 cur_bit = (0x1UL << i); 4943 if (sig & cur_bit) { 4944 res = true; /* Each bit is real error! */ 4945 if (print) { 4946 switch (cur_bit) { 4947 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 4948 _print_next_block((*par_num)++, 4949 "PGLUE_B"); 4950 _print_parity(bp, 4951 PGLUE_B_REG_PGLUE_B_PRTY_STS); 4952 break; 4953 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 4954 _print_next_block((*par_num)++, "ATC"); 4955 _print_parity(bp, 4956 ATC_REG_ATC_PRTY_STS); 4957 break; 4958 } 4959 } 4960 /* Clear the bit */ 4961 sig &= ~cur_bit; 4962 } 4963 } 4964 4965 return res; 4966} 4967 4968static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, 4969 u32 *sig) 4970{ 4971 bool res = false; 4972 4973 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 4974 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4975 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4976 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4977 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4978 int par_num = 0; 4979 4980 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n" 4981 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 4982 sig[0] & HW_PRTY_ASSERT_SET_0, 4983 sig[1] & HW_PRTY_ASSERT_SET_1, 4984 sig[2] & HW_PRTY_ASSERT_SET_2, 4985 sig[3] & HW_PRTY_ASSERT_SET_3, 4986 sig[4] & HW_PRTY_ASSERT_SET_4); 4987 if (print) { 4988 if (((sig[0] & HW_PRTY_ASSERT_SET_0) || 4989 (sig[1] & HW_PRTY_ASSERT_SET_1) || 4990 (sig[2] & HW_PRTY_ASSERT_SET_2) || 4991 (sig[4] & HW_PRTY_ASSERT_SET_4)) || 4992 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) { 4993 netdev_err(bp->dev, 4994 "Parity errors detected in blocks: "); 4995 } else { 4996 print = false; 4997 } 4998 } 4999 res |= bnx2x_check_blocks_with_parity0(bp, 5000 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print); 5001 res |= bnx2x_check_blocks_with_parity1(bp, 5002 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print); 5003 res |= bnx2x_check_blocks_with_parity2(bp, 5004 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print); 5005 res |= bnx2x_check_blocks_with_parity3(bp, 5006 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print); 5007 res |= bnx2x_check_blocks_with_parity4(bp, 5008 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print); 5009 5010 if (print) 5011 pr_cont("\n"); 5012 } 5013 5014 return res; 5015} 5016 5017/** 5018 * bnx2x_chk_parity_attn - checks for parity attentions. 5019 * 5020 * @bp: driver handle 5021 * @global: true if there was a global attention 5022 * @print: show parity attention in syslog 5023 */ 5024bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) 5025{ 5026 struct attn_route attn = { {0} }; 5027 int port = BP_PORT(bp); 5028 5029 attn.sig[0] = REG_RD(bp, 5030 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 5031 port*4); 5032 attn.sig[1] = REG_RD(bp, 5033 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + 5034 port*4); 5035 attn.sig[2] = REG_RD(bp, 5036 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + 5037 port*4); 5038 attn.sig[3] = REG_RD(bp, 5039 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 5040 port*4); 5041 /* Since MCP attentions can't be disabled inside the block, we need to 5042 * read AEU registers to see whether they're currently disabled 5043 */ 5044 attn.sig[3] &= ((REG_RD(bp, 5045 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 5046 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) & 5047 MISC_AEU_ENABLE_MCP_PRTY_BITS) | 5048 ~MISC_AEU_ENABLE_MCP_PRTY_BITS); 5049 5050 if (!CHIP_IS_E1x(bp)) 5051 attn.sig[4] = REG_RD(bp, 5052 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + 5053 port*4); 5054 5055 return bnx2x_parity_attn(bp, global, print, attn.sig); 5056} 5057 5058static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) 5059{ 5060 u32 val; 5061 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 5062 5063 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 5064 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 5065 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 5066 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 5067 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 5068 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 5069 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 5070 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 5071 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 5072 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 5073 if (val & 5074 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 5075 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 5076 if (val & 5077 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 5078 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 5079 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 5080 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 5081 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 5082 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 5083 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 5084 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 5085 } 5086 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 5087 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 5088 BNX2X_ERR("ATC hw attention 0x%x\n", val); 5089 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 5090 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 5091 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 5092 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 5093 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 5094 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 5095 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 5096 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 5097 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 5098 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 5099 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 5100 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 5101 } 5102 5103 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 5104 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 5105 BNX2X_ERR("FATAL parity attention set4 0x%x\n", 5106 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 5107 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 5108 } 5109} 5110 5111static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 5112{ 5113 struct attn_route attn, *group_mask; 5114 int port = BP_PORT(bp); 5115 int index; 5116 u32 reg_addr; 5117 u32 val; 5118 u32 aeu_mask; 5119 bool global = false; 5120 5121 /* need to take HW lock because MCP or other port might also 5122 try to handle this event */ 5123 bnx2x_acquire_alr(bp); 5124 5125 if (bnx2x_chk_parity_attn(bp, &global, true)) { 5126#ifndef BNX2X_STOP_ON_ERROR 5127 bp->recovery_state = BNX2X_RECOVERY_INIT; 5128 schedule_delayed_work(&bp->sp_rtnl_task, 0); 5129 /* Disable HW interrupts */ 5130 bnx2x_int_disable(bp); 5131 /* In case of parity errors don't handle attentions so that 5132 * other function would "see" parity errors. 5133 */ 5134#else 5135 bnx2x_panic(); 5136#endif 5137 bnx2x_release_alr(bp); 5138 return; 5139 } 5140 5141 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 5142 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 5143 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 5144 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 5145 if (!CHIP_IS_E1x(bp)) 5146 attn.sig[4] = 5147 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 5148 else 5149 attn.sig[4] = 0; 5150 5151 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n", 5152 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 5153 5154 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 5155 if (deasserted & (1 << index)) { 5156 group_mask = &bp->attn_group[index]; 5157 5158 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n", 5159 index, 5160 group_mask->sig[0], group_mask->sig[1], 5161 group_mask->sig[2], group_mask->sig[3], 5162 group_mask->sig[4]); 5163 5164 bnx2x_attn_int_deasserted4(bp, 5165 attn.sig[4] & group_mask->sig[4]); 5166 bnx2x_attn_int_deasserted3(bp, 5167 attn.sig[3] & group_mask->sig[3]); 5168 bnx2x_attn_int_deasserted1(bp, 5169 attn.sig[1] & group_mask->sig[1]); 5170 bnx2x_attn_int_deasserted2(bp, 5171 attn.sig[2] & group_mask->sig[2]); 5172 bnx2x_attn_int_deasserted0(bp, 5173 attn.sig[0] & group_mask->sig[0]); 5174 } 5175 } 5176 5177 bnx2x_release_alr(bp); 5178 5179 if (bp->common.int_block == INT_BLOCK_HC) 5180 reg_addr = (HC_REG_COMMAND_REG + port*32 + 5181 COMMAND_REG_ATTN_BITS_CLR); 5182 else 5183 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 5184 5185 val = ~deasserted; 5186 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val, 5187 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 5188 REG_WR(bp, reg_addr, val); 5189 5190 if (~bp->attn_state & deasserted) 5191 BNX2X_ERR("IGU ERROR\n"); 5192 5193 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 5194 MISC_REG_AEU_MASK_ATTN_FUNC_0; 5195 5196 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 5197 aeu_mask = REG_RD(bp, reg_addr); 5198 5199 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n", 5200 aeu_mask, deasserted); 5201 aeu_mask |= (deasserted & 0x3ff); 5202 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask); 5203 5204 REG_WR(bp, reg_addr, aeu_mask); 5205 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 5206 5207 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); 5208 bp->attn_state &= ~deasserted; 5209 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); 5210} 5211 5212static void bnx2x_attn_int(struct bnx2x *bp) 5213{ 5214 /* read local copy of bits */ 5215 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. 5216 attn_bits); 5217 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. 5218 attn_bits_ack); 5219 u32 attn_state = bp->attn_state; 5220 5221 /* look for changed bits */ 5222 u32 asserted = attn_bits & ~attn_ack & ~attn_state; 5223 u32 deasserted = ~attn_bits & attn_ack & attn_state; 5224 5225 DP(NETIF_MSG_HW, 5226 "attn_bits %x attn_ack %x asserted %x deasserted %x\n", 5227 attn_bits, attn_ack, asserted, deasserted); 5228 5229 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) 5230 BNX2X_ERR("BAD attention state\n"); 5231 5232 /* handle bits that were raised */ 5233 if (asserted) 5234 bnx2x_attn_int_asserted(bp, asserted); 5235 5236 if (deasserted) 5237 bnx2x_attn_int_deasserted(bp, deasserted); 5238} 5239 5240void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 5241 u16 index, u8 op, u8 update) 5242{ 5243 u32 igu_addr = bp->igu_base_addr; 5244 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 5245 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, 5246 igu_addr); 5247} 5248 5249static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) 5250{ 5251 /* No memory barriers */ 5252 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); 5253} 5254 5255static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, 5256 union event_ring_elem *elem) 5257{ 5258 u8 err = elem->message.error; 5259 5260 if (!bp->cnic_eth_dev.starting_cid || 5261 (cid < bp->cnic_eth_dev.starting_cid && 5262 cid != bp->cnic_eth_dev.iscsi_l2_cid)) 5263 return 1; 5264 5265 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid); 5266 5267 if (unlikely(err)) { 5268 5269 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n", 5270 cid); 5271 bnx2x_panic_dump(bp, false); 5272 } 5273 bnx2x_cnic_cfc_comp(bp, cid, err); 5274 return 0; 5275} 5276 5277static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) 5278{ 5279 struct bnx2x_mcast_ramrod_params rparam; 5280 int rc; 5281 5282 memset(&rparam, 0, sizeof(rparam)); 5283 5284 rparam.mcast_obj = &bp->mcast_obj; 5285 5286 netif_addr_lock_bh(bp->dev); 5287 5288 /* Clear pending state for the last command */ 5289 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); 5290 5291 /* If there are pending mcast commands - send them */ 5292 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { 5293 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 5294 if (rc < 0) 5295 BNX2X_ERR("Failed to send pending mcast commands: %d\n", 5296 rc); 5297 } 5298 5299 netif_addr_unlock_bh(bp->dev); 5300} 5301 5302static void bnx2x_handle_classification_eqe(struct bnx2x *bp, 5303 union event_ring_elem *elem) 5304{ 5305 unsigned long ramrod_flags = 0; 5306 int rc = 0; 5307 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo); 5308 u32 cid = echo & BNX2X_SWCID_MASK; 5309 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 5310 5311 /* Always push next commands out, don't wait here */ 5312 __set_bit(RAMROD_CONT, &ramrod_flags); 5313 5314 switch (echo >> BNX2X_SWCID_SHIFT) { 5315 case BNX2X_FILTER_MAC_PENDING: 5316 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n"); 5317 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) 5318 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 5319 else 5320 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; 5321 5322 break; 5323 case BNX2X_FILTER_VLAN_PENDING: 5324 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n"); 5325 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj; 5326 break; 5327 case BNX2X_FILTER_MCAST_PENDING: 5328 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n"); 5329 /* This is only relevant for 57710 where multicast MACs are 5330 * configured as unicast MACs using the same ramrod. 5331 */ 5332 bnx2x_handle_mcast_eqe(bp); 5333 return; 5334 default: 5335 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo); 5336 return; 5337 } 5338 5339 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); 5340 5341 if (rc < 0) 5342 BNX2X_ERR("Failed to schedule new commands: %d\n", rc); 5343 else if (rc > 0) 5344 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n"); 5345} 5346 5347static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start); 5348 5349static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) 5350{ 5351 netif_addr_lock_bh(bp->dev); 5352 5353 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 5354 5355 /* Send rx_mode command again if was requested */ 5356 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) 5357 bnx2x_set_storm_rx_mode(bp); 5358 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, 5359 &bp->sp_state)) 5360 bnx2x_set_iscsi_eth_rx_mode(bp, true); 5361 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 5362 &bp->sp_state)) 5363 bnx2x_set_iscsi_eth_rx_mode(bp, false); 5364 5365 netif_addr_unlock_bh(bp->dev); 5366} 5367 5368static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, 5369 union event_ring_elem *elem) 5370{ 5371 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) { 5372 DP(BNX2X_MSG_SP, 5373 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n", 5374 elem->message.data.vif_list_event.func_bit_map); 5375 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, 5376 elem->message.data.vif_list_event.func_bit_map); 5377 } else if (elem->message.data.vif_list_event.echo == 5378 VIF_LIST_RULE_SET) { 5379 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n"); 5380 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); 5381 } 5382} 5383 5384/* called with rtnl_lock */ 5385static void bnx2x_after_function_update(struct bnx2x *bp) 5386{ 5387 int q, rc; 5388 struct bnx2x_fastpath *fp; 5389 struct bnx2x_queue_state_params queue_params = {NULL}; 5390 struct bnx2x_queue_update_params *q_update_params = 5391 &queue_params.params.update; 5392 5393 /* Send Q update command with afex vlan removal values for all Qs */ 5394 queue_params.cmd = BNX2X_Q_CMD_UPDATE; 5395 5396 /* set silent vlan removal values according to vlan mode */ 5397 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 5398 &q_update_params->update_flags); 5399 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM, 5400 &q_update_params->update_flags); 5401 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5402 5403 /* in access mode mark mask and value are 0 to strip all vlans */ 5404 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { 5405 q_update_params->silent_removal_value = 0; 5406 q_update_params->silent_removal_mask = 0; 5407 } else { 5408 q_update_params->silent_removal_value = 5409 (bp->afex_def_vlan_tag & VLAN_VID_MASK); 5410 q_update_params->silent_removal_mask = VLAN_VID_MASK; 5411 } 5412 5413 for_each_eth_queue(bp, q) { 5414 /* Set the appropriate Queue object */ 5415 fp = &bp->fp[q]; 5416 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5417 5418 /* send the ramrod */ 5419 rc = bnx2x_queue_state_change(bp, &queue_params); 5420 if (rc < 0) 5421 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5422 q); 5423 } 5424 5425 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { 5426 fp = &bp->fp[FCOE_IDX(bp)]; 5427 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 5428 5429 /* clear pending completion bit */ 5430 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags); 5431 5432 /* mark latest Q bit */ 5433 smp_mb__before_atomic(); 5434 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); 5435 smp_mb__after_atomic(); 5436 5437 /* send Q update ramrod for FCoE Q */ 5438 rc = bnx2x_queue_state_change(bp, &queue_params); 5439 if (rc < 0) 5440 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n", 5441 q); 5442 } else { 5443 /* If no FCoE ring - ACK MCP now */ 5444 bnx2x_link_report(bp); 5445 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5446 } 5447} 5448 5449static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj( 5450 struct bnx2x *bp, u32 cid) 5451{ 5452 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid); 5453 5454 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) 5455 return &bnx2x_fcoe_sp_obj(bp, q_obj); 5456 else 5457 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; 5458} 5459 5460static void bnx2x_eq_int(struct bnx2x *bp) 5461{ 5462 u16 hw_cons, sw_cons, sw_prod; 5463 union event_ring_elem *elem; 5464 u8 echo; 5465 u32 cid; 5466 u8 opcode; 5467 int rc, spqe_cnt = 0; 5468 struct bnx2x_queue_sp_obj *q_obj; 5469 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; 5470 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; 5471 5472 hw_cons = le16_to_cpu(*bp->eq_cons_sb); 5473 5474 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256. 5475 * when we get the next-page we need to adjust so the loop 5476 * condition below will be met. The next element is the size of a 5477 * regular element and hence incrementing by 1 5478 */ 5479 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) 5480 hw_cons++; 5481 5482 /* This function may never run in parallel with itself for a 5483 * specific bp, thus there is no need in "paired" read memory 5484 * barrier here. 5485 */ 5486 sw_cons = bp->eq_cons; 5487 sw_prod = bp->eq_prod; 5488 5489 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n", 5490 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); 5491 5492 for (; sw_cons != hw_cons; 5493 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 5494 5495 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; 5496 5497 rc = bnx2x_iov_eq_sp_event(bp, elem); 5498 if (!rc) { 5499 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n", 5500 rc); 5501 goto next_spqe; 5502 } 5503 5504 opcode = elem->message.opcode; 5505 5506 /* handle eq element */ 5507 switch (opcode) { 5508 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 5509 bnx2x_vf_mbx_schedule(bp, 5510 &elem->message.data.vf_pf_event); 5511 continue; 5512 5513 case EVENT_RING_OPCODE_STAT_QUERY: 5514 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS), 5515 "got statistics comp event %d\n", 5516 bp->stats_comp++); 5517 /* nothing to do with stats comp */ 5518 goto next_spqe; 5519 5520 case EVENT_RING_OPCODE_CFC_DEL: 5521 /* handle according to cid range */ 5522 /* 5523 * we may want to verify here that the bp state is 5524 * HALTING 5525 */ 5526 5527 /* elem CID originates from FW; actually LE */ 5528 cid = SW_CID(elem->message.data.cfc_del_event.cid); 5529 5530 DP(BNX2X_MSG_SP, 5531 "got delete ramrod for MULTI[%d]\n", cid); 5532 5533 if (CNIC_LOADED(bp) && 5534 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) 5535 goto next_spqe; 5536 5537 q_obj = bnx2x_cid_to_q_obj(bp, cid); 5538 5539 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) 5540 break; 5541 5542 goto next_spqe; 5543 5544 case EVENT_RING_OPCODE_STOP_TRAFFIC: 5545 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n"); 5546 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); 5547 if (f_obj->complete_cmd(bp, f_obj, 5548 BNX2X_F_CMD_TX_STOP)) 5549 break; 5550 goto next_spqe; 5551 5552 case EVENT_RING_OPCODE_START_TRAFFIC: 5553 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n"); 5554 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 5555 if (f_obj->complete_cmd(bp, f_obj, 5556 BNX2X_F_CMD_TX_START)) 5557 break; 5558 goto next_spqe; 5559 5560 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 5561 echo = elem->message.data.function_update_event.echo; 5562 if (echo == SWITCH_UPDATE) { 5563 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5564 "got FUNC_SWITCH_UPDATE ramrod\n"); 5565 if (f_obj->complete_cmd( 5566 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) 5567 break; 5568 5569 } else { 5570 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE; 5571 5572 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP, 5573 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 5574 f_obj->complete_cmd(bp, f_obj, 5575 BNX2X_F_CMD_AFEX_UPDATE); 5576 5577 /* We will perform the Queues update from 5578 * sp_rtnl task as all Queue SP operations 5579 * should run under rtnl_lock. 5580 */ 5581 bnx2x_schedule_sp_rtnl(bp, cmd, 0); 5582 } 5583 5584 goto next_spqe; 5585 5586 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 5587 f_obj->complete_cmd(bp, f_obj, 5588 BNX2X_F_CMD_AFEX_VIFLISTS); 5589 bnx2x_after_afex_vif_lists(bp, elem); 5590 goto next_spqe; 5591 case EVENT_RING_OPCODE_FUNCTION_START: 5592 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5593 "got FUNC_START ramrod\n"); 5594 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 5595 break; 5596 5597 goto next_spqe; 5598 5599 case EVENT_RING_OPCODE_FUNCTION_STOP: 5600 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP, 5601 "got FUNC_STOP ramrod\n"); 5602 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 5603 break; 5604 5605 goto next_spqe; 5606 5607 case EVENT_RING_OPCODE_SET_TIMESYNC: 5608 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP, 5609 "got set_timesync ramrod completion\n"); 5610 if (f_obj->complete_cmd(bp, f_obj, 5611 BNX2X_F_CMD_SET_TIMESYNC)) 5612 break; 5613 goto next_spqe; 5614 } 5615 5616 switch (opcode | bp->state) { 5617 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5618 BNX2X_STATE_OPEN): 5619 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5620 BNX2X_STATE_OPENING_WAIT4_PORT): 5621 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | 5622 BNX2X_STATE_CLOSING_WAIT4_HALT): 5623 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n", 5624 SW_CID(elem->message.data.eth_event.echo)); 5625 rss_raw->clear_pending(rss_raw); 5626 break; 5627 5628 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN): 5629 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG): 5630 case (EVENT_RING_OPCODE_SET_MAC | 5631 BNX2X_STATE_CLOSING_WAIT4_HALT): 5632 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5633 BNX2X_STATE_OPEN): 5634 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5635 BNX2X_STATE_DIAG): 5636 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | 5637 BNX2X_STATE_CLOSING_WAIT4_HALT): 5638 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n"); 5639 bnx2x_handle_classification_eqe(bp, elem); 5640 break; 5641 5642 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5643 BNX2X_STATE_OPEN): 5644 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5645 BNX2X_STATE_DIAG): 5646 case (EVENT_RING_OPCODE_MULTICAST_RULES | 5647 BNX2X_STATE_CLOSING_WAIT4_HALT): 5648 DP(BNX2X_MSG_SP, "got mcast ramrod\n"); 5649 bnx2x_handle_mcast_eqe(bp); 5650 break; 5651 5652 case (EVENT_RING_OPCODE_FILTERS_RULES | 5653 BNX2X_STATE_OPEN): 5654 case (EVENT_RING_OPCODE_FILTERS_RULES | 5655 BNX2X_STATE_DIAG): 5656 case (EVENT_RING_OPCODE_FILTERS_RULES | 5657 BNX2X_STATE_CLOSING_WAIT4_HALT): 5658 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n"); 5659 bnx2x_handle_rx_mode_eqe(bp); 5660 break; 5661 default: 5662 /* unknown event log error and continue */ 5663 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n", 5664 elem->message.opcode, bp->state); 5665 } 5666next_spqe: 5667 spqe_cnt++; 5668 } /* for */ 5669 5670 smp_mb__before_atomic(); 5671 atomic_add(spqe_cnt, &bp->eq_spq_left); 5672 5673 bp->eq_cons = sw_cons; 5674 bp->eq_prod = sw_prod; 5675 /* Make sure that above mem writes were issued towards the memory */ 5676 smp_wmb(); 5677 5678 /* update producer */ 5679 bnx2x_update_eq_prod(bp, bp->eq_prod); 5680} 5681 5682static void bnx2x_sp_task(struct work_struct *work) 5683{ 5684 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); 5685 5686 DP(BNX2X_MSG_SP, "sp task invoked\n"); 5687 5688 /* make sure the atomic interrupt_occurred has been written */ 5689 smp_rmb(); 5690 if (atomic_read(&bp->interrupt_occurred)) { 5691 5692 /* what work needs to be performed? */ 5693 u16 status = bnx2x_update_dsb_idx(bp); 5694 5695 DP(BNX2X_MSG_SP, "status %x\n", status); 5696 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n"); 5697 atomic_set(&bp->interrupt_occurred, 0); 5698 5699 /* HW attentions */ 5700 if (status & BNX2X_DEF_SB_ATT_IDX) { 5701 bnx2x_attn_int(bp); 5702 status &= ~BNX2X_DEF_SB_ATT_IDX; 5703 } 5704 5705 /* SP events: STAT_QUERY and others */ 5706 if (status & BNX2X_DEF_SB_IDX) { 5707 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 5708 5709 if (FCOE_INIT(bp) && 5710 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 5711 /* Prevent local bottom-halves from running as 5712 * we are going to change the local NAPI list. 5713 */ 5714 local_bh_disable(); 5715 napi_schedule(&bnx2x_fcoe(bp, napi)); 5716 local_bh_enable(); 5717 } 5718 5719 /* Handle EQ completions */ 5720 bnx2x_eq_int(bp); 5721 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 5722 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); 5723 5724 status &= ~BNX2X_DEF_SB_IDX; 5725 } 5726 5727 /* if status is non zero then perhaps something went wrong */ 5728 if (unlikely(status)) 5729 DP(BNX2X_MSG_SP, 5730 "got an unknown interrupt! (status 0x%x)\n", status); 5731 5732 /* ack status block only if something was actually handled */ 5733 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 5734 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); 5735 } 5736 5737 /* afex - poll to check if VIFSET_ACK should be sent to MFW */ 5738 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, 5739 &bp->sp_state)) { 5740 bnx2x_link_report(bp); 5741 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 5742 } 5743} 5744 5745irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) 5746{ 5747 struct net_device *dev = dev_instance; 5748 struct bnx2x *bp = netdev_priv(dev); 5749 5750 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, 5751 IGU_INT_DISABLE, 0); 5752 5753#ifdef BNX2X_STOP_ON_ERROR 5754 if (unlikely(bp->panic)) 5755 return IRQ_HANDLED; 5756#endif 5757 5758 if (CNIC_LOADED(bp)) { 5759 struct cnic_ops *c_ops; 5760 5761 rcu_read_lock(); 5762 c_ops = rcu_dereference(bp->cnic_ops); 5763 if (c_ops) 5764 c_ops->cnic_handler(bp->cnic_data, NULL); 5765 rcu_read_unlock(); 5766 } 5767 5768 /* schedule sp task to perform default status block work, ack 5769 * attentions and enable interrupts. 5770 */ 5771 bnx2x_schedule_sp_task(bp); 5772 5773 return IRQ_HANDLED; 5774} 5775 5776/* end of slow path */ 5777 5778void bnx2x_drv_pulse(struct bnx2x *bp) 5779{ 5780 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, 5781 bp->fw_drv_pulse_wr_seq); 5782} 5783 5784static void bnx2x_timer(struct timer_list *t) 5785{ 5786 struct bnx2x *bp = from_timer(bp, t, timer); 5787 5788 if (!netif_running(bp->dev)) 5789 return; 5790 5791 if (IS_PF(bp) && 5792 !BP_NOMCP(bp)) { 5793 int mb_idx = BP_FW_MB_IDX(bp); 5794 u16 drv_pulse; 5795 u16 mcp_pulse; 5796 5797 ++bp->fw_drv_pulse_wr_seq; 5798 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 5799 drv_pulse = bp->fw_drv_pulse_wr_seq; 5800 bnx2x_drv_pulse(bp); 5801 5802 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & 5803 MCP_PULSE_SEQ_MASK); 5804 /* The delta between driver pulse and mcp response 5805 * should not get too big. If the MFW is more than 5 pulses 5806 * behind, we should worry about it enough to generate an error 5807 * log. 5808 */ 5809 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5) 5810 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 5811 drv_pulse, mcp_pulse); 5812 } 5813 5814 if (bp->state == BNX2X_STATE_OPEN) 5815 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); 5816 5817 /* sample pf vf bulletin board for new posts from pf */ 5818 if (IS_VF(bp)) 5819 bnx2x_timer_sriov(bp); 5820 5821 mod_timer(&bp->timer, jiffies + bp->current_interval); 5822} 5823 5824/* end of Statistics */ 5825 5826/* nic init */ 5827 5828/* 5829 * nic init service functions 5830 */ 5831 5832static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) 5833{ 5834 u32 i; 5835 if (!(len%4) && !(addr%4)) 5836 for (i = 0; i < len; i += 4) 5837 REG_WR(bp, addr + i, fill); 5838 else 5839 for (i = 0; i < len; i++) 5840 REG_WR8(bp, addr + i, fill); 5841} 5842 5843/* helper: writes FP SP data to FW - data_size in dwords */ 5844static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, 5845 int fw_sb_id, 5846 u32 *sb_data_p, 5847 u32 data_size) 5848{ 5849 int index; 5850 for (index = 0; index < data_size; index++) 5851 REG_WR(bp, BAR_CSTRORM_INTMEM + 5852 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 5853 sizeof(u32)*index, 5854 *(sb_data_p + index)); 5855} 5856 5857static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) 5858{ 5859 u32 *sb_data_p; 5860 u32 data_size = 0; 5861 struct hc_status_block_data_e2 sb_data_e2; 5862 struct hc_status_block_data_e1x sb_data_e1x; 5863 5864 /* disable the function first */ 5865 if (!CHIP_IS_E1x(bp)) { 5866 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5867 sb_data_e2.common.state = SB_DISABLED; 5868 sb_data_e2.common.p_func.vf_valid = false; 5869 sb_data_p = (u32 *)&sb_data_e2; 5870 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5871 } else { 5872 memset(&sb_data_e1x, 0, 5873 sizeof(struct hc_status_block_data_e1x)); 5874 sb_data_e1x.common.state = SB_DISABLED; 5875 sb_data_e1x.common.p_func.vf_valid = false; 5876 sb_data_p = (u32 *)&sb_data_e1x; 5877 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 5878 } 5879 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5880 5881 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5882 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0, 5883 CSTORM_STATUS_BLOCK_SIZE); 5884 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5885 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0, 5886 CSTORM_SYNC_BLOCK_SIZE); 5887} 5888 5889/* helper: writes SP SB data to FW */ 5890static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, 5891 struct hc_sp_status_block_data *sp_sb_data) 5892{ 5893 int func = BP_FUNC(bp); 5894 int i; 5895 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++) 5896 REG_WR(bp, BAR_CSTRORM_INTMEM + 5897 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) + 5898 i*sizeof(u32), 5899 *((u32 *)sp_sb_data + i)); 5900} 5901 5902static void bnx2x_zero_sp_sb(struct bnx2x *bp) 5903{ 5904 int func = BP_FUNC(bp); 5905 struct hc_sp_status_block_data sp_sb_data; 5906 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 5907 5908 sp_sb_data.state = SB_DISABLED; 5909 sp_sb_data.p_func.vf_valid = false; 5910 5911 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 5912 5913 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5914 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0, 5915 CSTORM_SP_STATUS_BLOCK_SIZE); 5916 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + 5917 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0, 5918 CSTORM_SP_SYNC_BLOCK_SIZE); 5919} 5920 5921static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 5922 int igu_sb_id, int igu_seg_id) 5923{ 5924 hc_sm->igu_sb_id = igu_sb_id; 5925 hc_sm->igu_seg_id = igu_seg_id; 5926 hc_sm->timer_value = 0xFF; 5927 hc_sm->time_to_expire = 0xFFFFFFFF; 5928} 5929 5930/* allocates state machine ids. */ 5931static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) 5932{ 5933 /* zero out state machine indices */ 5934 /* rx indices */ 5935 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5936 5937 /* tx indices */ 5938 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 5939 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 5940 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 5941 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 5942 5943 /* map indices */ 5944 /* rx indices */ 5945 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 5946 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5947 5948 /* tx indices */ 5949 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 5950 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5951 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 5952 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5953 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 5954 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5955 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 5956 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; 5957} 5958 5959void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 5960 u8 vf_valid, int fw_sb_id, int igu_sb_id) 5961{ 5962 int igu_seg_id; 5963 5964 struct hc_status_block_data_e2 sb_data_e2; 5965 struct hc_status_block_data_e1x sb_data_e1x; 5966 struct hc_status_block_sm *hc_sm_p; 5967 int data_size; 5968 u32 *sb_data_p; 5969 5970 if (CHIP_INT_MODE_IS_BC(bp)) 5971 igu_seg_id = HC_SEG_ACCESS_NORM; 5972 else 5973 igu_seg_id = IGU_SEG_ACCESS_NORM; 5974 5975 bnx2x_zero_fp_sb(bp, fw_sb_id); 5976 5977 if (!CHIP_IS_E1x(bp)) { 5978 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 5979 sb_data_e2.common.state = SB_ENABLED; 5980 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); 5981 sb_data_e2.common.p_func.vf_id = vfid; 5982 sb_data_e2.common.p_func.vf_valid = vf_valid; 5983 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); 5984 sb_data_e2.common.same_igu_sb_1b = true; 5985 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping); 5986 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping); 5987 hc_sm_p = sb_data_e2.common.state_machine; 5988 sb_data_p = (u32 *)&sb_data_e2; 5989 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); 5990 bnx2x_map_sb_state_machines(sb_data_e2.index_data); 5991 } else { 5992 memset(&sb_data_e1x, 0, 5993 sizeof(struct hc_status_block_data_e1x)); 5994 sb_data_e1x.common.state = SB_ENABLED; 5995 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); 5996 sb_data_e1x.common.p_func.vf_id = 0xff; 5997 sb_data_e1x.common.p_func.vf_valid = false; 5998 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); 5999 sb_data_e1x.common.same_igu_sb_1b = true; 6000 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping); 6001 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping); 6002 hc_sm_p = sb_data_e1x.common.state_machine; 6003 sb_data_p = (u32 *)&sb_data_e1x; 6004 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); 6005 bnx2x_map_sb_state_machines(sb_data_e1x.index_data); 6006 } 6007 6008 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], 6009 igu_sb_id, igu_seg_id); 6010 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 6011 igu_sb_id, igu_seg_id); 6012 6013 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id); 6014 6015 /* write indices to HW - PCI guarantees endianity of regpairs */ 6016 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 6017} 6018 6019static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, 6020 u16 tx_usec, u16 rx_usec) 6021{ 6022 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, 6023 false, rx_usec); 6024 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6025 HC_INDEX_ETH_TX_CQ_CONS_COS0, false, 6026 tx_usec); 6027 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6028 HC_INDEX_ETH_TX_CQ_CONS_COS1, false, 6029 tx_usec); 6030 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, 6031 HC_INDEX_ETH_TX_CQ_CONS_COS2, false, 6032 tx_usec); 6033} 6034 6035static void bnx2x_init_def_sb(struct bnx2x *bp) 6036{ 6037 struct host_sp_status_block *def_sb = bp->def_status_blk; 6038 dma_addr_t mapping = bp->def_status_blk_mapping; 6039 int igu_sp_sb_index; 6040 int igu_seg_id; 6041 int port = BP_PORT(bp); 6042 int func = BP_FUNC(bp); 6043 int reg_offset, reg_offset_en5; 6044 u64 section; 6045 int index; 6046 struct hc_sp_status_block_data sp_sb_data; 6047 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 6048 6049 if (CHIP_INT_MODE_IS_BC(bp)) { 6050 igu_sp_sb_index = DEF_SB_IGU_ID; 6051 igu_seg_id = HC_SEG_ACCESS_DEF; 6052 } else { 6053 igu_sp_sb_index = bp->igu_dsb_id; 6054 igu_seg_id = IGU_SEG_ACCESS_DEF; 6055 } 6056 6057 /* ATTN */ 6058 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 6059 atten_status_block); 6060 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 6061 6062 bp->attn_state = 0; 6063 6064 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 6065 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 6066 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 6067 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0); 6068 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 6069 int sindex; 6070 /* take care of sig[0]..sig[4] */ 6071 for (sindex = 0; sindex < 4; sindex++) 6072 bp->attn_group[index].sig[sindex] = 6073 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); 6074 6075 if (!CHIP_IS_E1x(bp)) 6076 /* 6077 * enable5 is separate from the rest of the registers, 6078 * and therefore the address skip is 4 6079 * and not 16 between the different groups 6080 */ 6081 bp->attn_group[index].sig[4] = REG_RD(bp, 6082 reg_offset_en5 + 0x4*index); 6083 else 6084 bp->attn_group[index].sig[4] = 0; 6085 } 6086 6087 if (bp->common.int_block == INT_BLOCK_HC) { 6088 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L : 6089 HC_REG_ATTN_MSG0_ADDR_L); 6090 6091 REG_WR(bp, reg_offset, U64_LO(section)); 6092 REG_WR(bp, reg_offset + 4, U64_HI(section)); 6093 } else if (!CHIP_IS_E1x(bp)) { 6094 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 6095 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 6096 } 6097 6098 section = ((u64)mapping) + offsetof(struct host_sp_status_block, 6099 sp_sb); 6100 6101 bnx2x_zero_sp_sb(bp); 6102 6103 /* PCI guarantees endianity of regpairs */ 6104 sp_sb_data.state = SB_ENABLED; 6105 sp_sb_data.host_sb_addr.lo = U64_LO(section); 6106 sp_sb_data.host_sb_addr.hi = U64_HI(section); 6107 sp_sb_data.igu_sb_id = igu_sp_sb_index; 6108 sp_sb_data.igu_seg_id = igu_seg_id; 6109 sp_sb_data.p_func.pf_id = func; 6110 sp_sb_data.p_func.vnic_id = BP_VN(bp); 6111 sp_sb_data.p_func.vf_id = 0xff; 6112 6113 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); 6114 6115 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 6116} 6117 6118void bnx2x_update_coalesce(struct bnx2x *bp) 6119{ 6120 int i; 6121 6122 for_each_eth_queue(bp, i) 6123 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, 6124 bp->tx_ticks, bp->rx_ticks); 6125} 6126 6127static void bnx2x_init_sp_ring(struct bnx2x *bp) 6128{ 6129 spin_lock_init(&bp->spq_lock); 6130 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); 6131 6132 bp->spq_prod_idx = 0; 6133 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; 6134 bp->spq_prod_bd = bp->spq; 6135 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; 6136} 6137 6138static void bnx2x_init_eq_ring(struct bnx2x *bp) 6139{ 6140 int i; 6141 for (i = 1; i <= NUM_EQ_PAGES; i++) { 6142 union event_ring_elem *elem = 6143 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; 6144 6145 elem->next_page.addr.hi = 6146 cpu_to_le32(U64_HI(bp->eq_mapping + 6147 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES))); 6148 elem->next_page.addr.lo = 6149 cpu_to_le32(U64_LO(bp->eq_mapping + 6150 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES))); 6151 } 6152 bp->eq_cons = 0; 6153 bp->eq_prod = NUM_EQ_DESC; 6154 bp->eq_cons_sb = BNX2X_EQ_INDEX; 6155 /* we want a warning message before it gets wrought... */ 6156 atomic_set(&bp->eq_spq_left, 6157 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1); 6158} 6159 6160/* called with netif_addr_lock_bh() */ 6161static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 6162 unsigned long rx_mode_flags, 6163 unsigned long rx_accept_flags, 6164 unsigned long tx_accept_flags, 6165 unsigned long ramrod_flags) 6166{ 6167 struct bnx2x_rx_mode_ramrod_params ramrod_param; 6168 int rc; 6169 6170 memset(&ramrod_param, 0, sizeof(ramrod_param)); 6171 6172 /* Prepare ramrod parameters */ 6173 ramrod_param.cid = 0; 6174 ramrod_param.cl_id = cl_id; 6175 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; 6176 ramrod_param.func_id = BP_FUNC(bp); 6177 6178 ramrod_param.pstate = &bp->sp_state; 6179 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING; 6180 6181 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); 6182 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); 6183 6184 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); 6185 6186 ramrod_param.ramrod_flags = ramrod_flags; 6187 ramrod_param.rx_mode_flags = rx_mode_flags; 6188 6189 ramrod_param.rx_accept_flags = rx_accept_flags; 6190 ramrod_param.tx_accept_flags = tx_accept_flags; 6191 6192 rc = bnx2x_config_rx_mode(bp, &ramrod_param); 6193 if (rc < 0) { 6194 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); 6195 return rc; 6196 } 6197 6198 return 0; 6199} 6200 6201static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, 6202 unsigned long *rx_accept_flags, 6203 unsigned long *tx_accept_flags) 6204{ 6205 /* Clear the flags first */ 6206 *rx_accept_flags = 0; 6207 *tx_accept_flags = 0; 6208 6209 switch (rx_mode) { 6210 case BNX2X_RX_MODE_NONE: 6211 /* 6212 * 'drop all' supersedes any accept flags that may have been 6213 * passed to the function. 6214 */ 6215 break; 6216 case BNX2X_RX_MODE_NORMAL: 6217 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6218 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags); 6219 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6220 6221 /* internal switching mode */ 6222 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6223 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags); 6224 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6225 6226 if (bp->accept_any_vlan) { 6227 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6228 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6229 } 6230 6231 break; 6232 case BNX2X_RX_MODE_ALLMULTI: 6233 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6234 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 6235 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6236 6237 /* internal switching mode */ 6238 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6239 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 6240 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6241 6242 if (bp->accept_any_vlan) { 6243 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6244 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6245 } 6246 6247 break; 6248 case BNX2X_RX_MODE_PROMISC: 6249 /* According to definition of SI mode, iface in promisc mode 6250 * should receive matched and unmatched (in resolution of port) 6251 * unicast packets. 6252 */ 6253 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags); 6254 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags); 6255 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags); 6256 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags); 6257 6258 /* internal switching mode */ 6259 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags); 6260 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags); 6261 6262 if (IS_MF_SI(bp)) 6263 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags); 6264 else 6265 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags); 6266 6267 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags); 6268 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags); 6269 6270 break; 6271 default: 6272 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode); 6273 return -EINVAL; 6274 } 6275 6276 return 0; 6277} 6278 6279/* called with netif_addr_lock_bh() */ 6280static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) 6281{ 6282 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 6283 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 6284 int rc; 6285 6286 if (!NO_FCOE(bp)) 6287 /* Configure rx_mode of FCoE Queue */ 6288 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags); 6289 6290 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, 6291 &tx_accept_flags); 6292 if (rc) 6293 return rc; 6294 6295 __set_bit(RAMROD_RX, &ramrod_flags); 6296 __set_bit(RAMROD_TX, &ramrod_flags); 6297 6298 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, 6299 rx_accept_flags, tx_accept_flags, 6300 ramrod_flags); 6301} 6302 6303static void bnx2x_init_internal_common(struct bnx2x *bp) 6304{ 6305 int i; 6306 6307 /* Zero this manually as its initialization is 6308 currently missing in the initTool */ 6309 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) 6310 REG_WR(bp, BAR_USTRORM_INTMEM + 6311 USTORM_AGG_DATA_OFFSET + i * 4, 0); 6312 if (!CHIP_IS_E1x(bp)) { 6313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, 6314 CHIP_INT_MODE_IS_BC(bp) ? 6315 HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 6316 } 6317} 6318 6319static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 6320{ 6321 switch (load_code) { 6322 case FW_MSG_CODE_DRV_LOAD_COMMON: 6323 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 6324 bnx2x_init_internal_common(bp); 6325 fallthrough; 6326 6327 case FW_MSG_CODE_DRV_LOAD_PORT: 6328 /* nothing to do */ 6329 fallthrough; 6330 6331 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 6332 /* internal memory per function is 6333 initialized inside bnx2x_pf_init */ 6334 break; 6335 6336 default: 6337 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code); 6338 break; 6339 } 6340} 6341 6342static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp) 6343{ 6344 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); 6345} 6346 6347static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp) 6348{ 6349 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); 6350} 6351 6352static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp) 6353{ 6354 if (CHIP_IS_E1x(fp->bp)) 6355 return BP_L_ID(fp->bp) + fp->index; 6356 else /* We want Client ID to be the same as IGU SB ID for 57712 */ 6357 return bnx2x_fp_igu_sb_id(fp); 6358} 6359 6360static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) 6361{ 6362 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; 6363 u8 cos; 6364 unsigned long q_type = 0; 6365 u32 cids[BNX2X_MULTI_TX_COS] = { 0 }; 6366 fp->rx_queue = fp_idx; 6367 fp->cid = fp_idx; 6368 fp->cl_id = bnx2x_fp_cl_id(fp); 6369 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp); 6370 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp); 6371 /* qZone id equals to FW (per path) client id */ 6372 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp); 6373 6374 /* init shortcut */ 6375 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp); 6376 6377 /* Setup SB indices */ 6378 fp->rx_cons_sb = BNX2X_RX_SB_INDEX; 6379 6380 /* Configure Queue State object */ 6381 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6382 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6383 6384 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS); 6385 6386 /* init tx data */ 6387 for_each_cos_in_tx_queue(fp, cos) { 6388 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], 6389 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), 6390 FP_COS_TO_TXQ(fp, cos, bp), 6391 BNX2X_TX_SB_INDEX_BASE + cos, fp); 6392 cids[cos] = fp->txdata_ptr[cos]->cid; 6393 } 6394 6395 /* nothing more for vf to do here */ 6396 if (IS_VF(bp)) 6397 return; 6398 6399 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 6400 fp->fw_sb_id, fp->igu_sb_id); 6401 bnx2x_update_fpsb_idx(fp); 6402 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, 6403 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6404 bnx2x_sp_mapping(bp, q_rdata), q_type); 6405 6406 /** 6407 * Configure classification DBs: Always enable Tx switching 6408 */ 6409 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 6410 6411 DP(NETIF_MSG_IFUP, 6412 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6413 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6414 fp->igu_sb_id); 6415} 6416 6417static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 6418{ 6419 int i; 6420 6421 for (i = 1; i <= NUM_TX_RINGS; i++) { 6422 struct eth_tx_next_bd *tx_next_bd = 6423 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 6424 6425 tx_next_bd->addr_hi = 6426 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 6427 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6428 tx_next_bd->addr_lo = 6429 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 6430 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 6431 } 6432 6433 *txdata->tx_cons_sb = cpu_to_le16(0); 6434 6435 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 6436 txdata->tx_db.data.zero_fill1 = 0; 6437 txdata->tx_db.data.prod = 0; 6438 6439 txdata->tx_pkt_prod = 0; 6440 txdata->tx_pkt_cons = 0; 6441 txdata->tx_bd_prod = 0; 6442 txdata->tx_bd_cons = 0; 6443 txdata->tx_pkt = 0; 6444} 6445 6446static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) 6447{ 6448 int i; 6449 6450 for_each_tx_queue_cnic(bp, i) 6451 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); 6452} 6453 6454static void bnx2x_init_tx_rings(struct bnx2x *bp) 6455{ 6456 int i; 6457 u8 cos; 6458 6459 for_each_eth_queue(bp, i) 6460 for_each_cos_in_tx_queue(&bp->fp[i], cos) 6461 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); 6462} 6463 6464static void bnx2x_init_fcoe_fp(struct bnx2x *bp) 6465{ 6466 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 6467 unsigned long q_type = 0; 6468 6469 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 6470 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 6471 BNX2X_FCOE_ETH_CL_ID_IDX); 6472 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 6473 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 6474 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 6475 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 6476 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 6477 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 6478 fp); 6479 6480 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 6481 6482 /* qZone id equals to FW (per path) client id */ 6483 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 6484 /* init shortcut */ 6485 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 6486 bnx2x_rx_ustorm_prods_offset(fp); 6487 6488 /* Configure Queue State object */ 6489 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 6490 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 6491 6492 /* No multi-CoS for FCoE L2 client */ 6493 BUG_ON(fp->max_cos != 1); 6494 6495 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 6496 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 6497 bnx2x_sp_mapping(bp, q_rdata), q_type); 6498 6499 DP(NETIF_MSG_IFUP, 6500 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 6501 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 6502 fp->igu_sb_id); 6503} 6504 6505void bnx2x_nic_init_cnic(struct bnx2x *bp) 6506{ 6507 if (!NO_FCOE(bp)) 6508 bnx2x_init_fcoe_fp(bp); 6509 6510 bnx2x_init_sb(bp, bp->cnic_sb_mapping, 6511 BNX2X_VF_ID_INVALID, false, 6512 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); 6513 6514 /* ensure status block indices were read */ 6515 rmb(); 6516 bnx2x_init_rx_rings_cnic(bp); 6517 bnx2x_init_tx_rings_cnic(bp); 6518 6519 /* flush all */ 6520 mb(); 6521} 6522 6523void bnx2x_pre_irq_nic_init(struct bnx2x *bp) 6524{ 6525 int i; 6526 6527 /* Setup NIC internals and enable interrupts */ 6528 for_each_eth_queue(bp, i) 6529 bnx2x_init_eth_fp(bp, i); 6530 6531 /* ensure status block indices were read */ 6532 rmb(); 6533 bnx2x_init_rx_rings(bp); 6534 bnx2x_init_tx_rings(bp); 6535 6536 if (IS_PF(bp)) { 6537 /* Initialize MOD_ABS interrupts */ 6538 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, 6539 bp->common.shmem_base, 6540 bp->common.shmem2_base, BP_PORT(bp)); 6541 6542 /* initialize the default status block and sp ring */ 6543 bnx2x_init_def_sb(bp); 6544 bnx2x_update_dsb_idx(bp); 6545 bnx2x_init_sp_ring(bp); 6546 } else { 6547 bnx2x_memset_stats(bp); 6548 } 6549} 6550 6551void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) 6552{ 6553 bnx2x_init_eq_ring(bp); 6554 bnx2x_init_internal(bp, load_code); 6555 bnx2x_pf_init(bp); 6556 bnx2x_stats_init(bp); 6557 6558 /* flush all before enabling interrupts */ 6559 mb(); 6560 6561 bnx2x_int_enable(bp); 6562 6563 /* Check for SPIO5 */ 6564 bnx2x_attn_int_deasserted0(bp, 6565 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & 6566 AEU_INPUTS_ATTN_BITS_SPIO5); 6567} 6568 6569/* gzip service functions */ 6570static int bnx2x_gunzip_init(struct bnx2x *bp) 6571{ 6572 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, 6573 &bp->gunzip_mapping, GFP_KERNEL); 6574 if (bp->gunzip_buf == NULL) 6575 goto gunzip_nomem1; 6576 6577 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); 6578 if (bp->strm == NULL) 6579 goto gunzip_nomem2; 6580 6581 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); 6582 if (bp->strm->workspace == NULL) 6583 goto gunzip_nomem3; 6584 6585 return 0; 6586 6587gunzip_nomem3: 6588 kfree(bp->strm); 6589 bp->strm = NULL; 6590 6591gunzip_nomem2: 6592 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6593 bp->gunzip_mapping); 6594 bp->gunzip_buf = NULL; 6595 6596gunzip_nomem1: 6597 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n"); 6598 return -ENOMEM; 6599} 6600 6601static void bnx2x_gunzip_end(struct bnx2x *bp) 6602{ 6603 if (bp->strm) { 6604 vfree(bp->strm->workspace); 6605 kfree(bp->strm); 6606 bp->strm = NULL; 6607 } 6608 6609 if (bp->gunzip_buf) { 6610 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, 6611 bp->gunzip_mapping); 6612 bp->gunzip_buf = NULL; 6613 } 6614} 6615 6616static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) 6617{ 6618 int n, rc; 6619 6620 /* check gzip header */ 6621 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) { 6622 BNX2X_ERR("Bad gzip header\n"); 6623 return -EINVAL; 6624 } 6625 6626 n = 10; 6627 6628#define FNAME 0x8 6629 6630 if (zbuf[3] & FNAME) 6631 while ((zbuf[n++] != 0) && (n < len)); 6632 6633 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; 6634 bp->strm->avail_in = len - n; 6635 bp->strm->next_out = bp->gunzip_buf; 6636 bp->strm->avail_out = FW_BUF_SIZE; 6637 6638 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); 6639 if (rc != Z_OK) 6640 return rc; 6641 6642 rc = zlib_inflate(bp->strm, Z_FINISH); 6643 if ((rc != Z_OK) && (rc != Z_STREAM_END)) 6644 netdev_err(bp->dev, "Firmware decompression error: %s\n", 6645 bp->strm->msg); 6646 6647 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 6648 if (bp->gunzip_outlen & 0x3) 6649 netdev_err(bp->dev, 6650 "Firmware decompression error: gunzip_outlen (%d) not aligned\n", 6651 bp->gunzip_outlen); 6652 bp->gunzip_outlen >>= 2; 6653 6654 zlib_inflateEnd(bp->strm); 6655 6656 if (rc == Z_STREAM_END) 6657 return 0; 6658 6659 return rc; 6660} 6661 6662/* nic load/unload */ 6663 6664/* 6665 * General service functions 6666 */ 6667 6668/* send a NIG loopback debug packet */ 6669static void bnx2x_lb_pckt(struct bnx2x *bp) 6670{ 6671 u32 wb_write[3]; 6672 6673 /* Ethernet source and destination addresses */ 6674 wb_write[0] = 0x55555555; 6675 wb_write[1] = 0x55555555; 6676 wb_write[2] = 0x20; /* SOP */ 6677 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6678 6679 /* NON-IP protocol */ 6680 wb_write[0] = 0x09000000; 6681 wb_write[1] = 0x55555555; 6682 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 6683 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 6684} 6685 6686/* some of the internal memories 6687 * are not directly readable from the driver 6688 * to test them we send debug packets 6689 */ 6690static int bnx2x_int_mem_test(struct bnx2x *bp) 6691{ 6692 int factor; 6693 int count, i; 6694 u32 val = 0; 6695 6696 if (CHIP_REV_IS_FPGA(bp)) 6697 factor = 120; 6698 else if (CHIP_REV_IS_EMUL(bp)) 6699 factor = 200; 6700 else 6701 factor = 1; 6702 6703 /* Disable inputs of parser neighbor blocks */ 6704 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6705 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6706 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6707 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6708 6709 /* Write 0 to parser credits for CFC search request */ 6710 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6711 6712 /* send Ethernet packet */ 6713 bnx2x_lb_pckt(bp); 6714 6715 /* TODO do i reset NIG statistic? */ 6716 /* Wait until NIG register shows 1 packet of size 0x10 */ 6717 count = 1000 * factor; 6718 while (count) { 6719 6720 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6721 val = *bnx2x_sp(bp, wb_data[0]); 6722 if (val == 0x10) 6723 break; 6724 6725 usleep_range(10000, 20000); 6726 count--; 6727 } 6728 if (val != 0x10) { 6729 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6730 return -1; 6731 } 6732 6733 /* Wait until PRS register shows 1 packet */ 6734 count = 1000 * factor; 6735 while (count) { 6736 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6737 if (val == 1) 6738 break; 6739 6740 usleep_range(10000, 20000); 6741 count--; 6742 } 6743 if (val != 0x1) { 6744 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6745 return -2; 6746 } 6747 6748 /* Reset and init BRB, PRS */ 6749 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6750 msleep(50); 6751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6752 msleep(50); 6753 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6754 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6755 6756 DP(NETIF_MSG_HW, "part2\n"); 6757 6758 /* Disable inputs of parser neighbor blocks */ 6759 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); 6760 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); 6761 REG_WR(bp, CFC_REG_DEBUG0, 0x1); 6762 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); 6763 6764 /* Write 0 to parser credits for CFC search request */ 6765 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 6766 6767 /* send 10 Ethernet packets */ 6768 for (i = 0; i < 10; i++) 6769 bnx2x_lb_pckt(bp); 6770 6771 /* Wait until NIG register shows 10 + 1 6772 packets of size 11*0x10 = 0xb0 */ 6773 count = 1000 * factor; 6774 while (count) { 6775 6776 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 6777 val = *bnx2x_sp(bp, wb_data[0]); 6778 if (val == 0xb0) 6779 break; 6780 6781 usleep_range(10000, 20000); 6782 count--; 6783 } 6784 if (val != 0xb0) { 6785 BNX2X_ERR("NIG timeout val = 0x%x\n", val); 6786 return -3; 6787 } 6788 6789 /* Wait until PRS register shows 2 packets */ 6790 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6791 if (val != 2) 6792 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6793 6794 /* Write 1 to parser credits for CFC search request */ 6795 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 6796 6797 /* Wait until PRS register shows 3 packets */ 6798 msleep(10 * factor); 6799 /* Wait until NIG register shows 1 packet of size 0x10 */ 6800 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); 6801 if (val != 3) 6802 BNX2X_ERR("PRS timeout val = 0x%x\n", val); 6803 6804 /* clear NIG EOP FIFO */ 6805 for (i = 0; i < 11; i++) 6806 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); 6807 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); 6808 if (val != 1) { 6809 BNX2X_ERR("clear of NIG failed\n"); 6810 return -4; 6811 } 6812 6813 /* Reset and init BRB, PRS, NIG */ 6814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 6815 msleep(50); 6816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 6817 msleep(50); 6818 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 6819 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 6820 if (!CNIC_SUPPORT(bp)) 6821 /* set NIC mode */ 6822 REG_WR(bp, PRS_REG_NIC_MODE, 1); 6823 6824 /* Enable inputs of parser neighbor blocks */ 6825 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); 6826 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); 6827 REG_WR(bp, CFC_REG_DEBUG0, 0x0); 6828 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); 6829 6830 DP(NETIF_MSG_HW, "done\n"); 6831 6832 return 0; /* OK */ 6833} 6834 6835static void bnx2x_enable_blocks_attention(struct bnx2x *bp) 6836{ 6837 u32 val; 6838 6839 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 6840 if (!CHIP_IS_E1x(bp)) 6841 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); 6842 else 6843 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); 6844 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 6845 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 6846 /* 6847 * mask read length error interrupts in brb for parser 6848 * (parsing unit and 'checksum and crc' unit) 6849 * these errors are legal (PU reads fixed length and CAC can cause 6850 * read length error on truncated packets) 6851 */ 6852 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); 6853 REG_WR(bp, QM_REG_QM_INT_MASK, 0); 6854 REG_WR(bp, TM_REG_TM_INT_MASK, 0); 6855 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); 6856 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); 6857 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); 6858/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ 6859/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ 6860 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); 6861 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); 6862 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); 6863/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ 6864/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ 6865 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 6866 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); 6867 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); 6868 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); 6869/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ 6870/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ 6871 6872 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 6873 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 6874 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN; 6875 if (!CHIP_IS_E1x(bp)) 6876 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 6877 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED; 6878 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); 6879 6880 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); 6881 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); 6882 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); 6883/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ 6884 6885 if (!CHIP_IS_E1x(bp)) 6886 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 6887 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 6888 6889 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); 6890 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); 6891/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ 6892 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 6893} 6894 6895static void bnx2x_reset_common(struct bnx2x *bp) 6896{ 6897 u32 val = 0x1400; 6898 6899 /* reset_common */ 6900 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 6901 0xd3ffff7f); 6902 6903 if (CHIP_IS_E3(bp)) { 6904 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 6905 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 6906 } 6907 6908 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); 6909} 6910 6911static void bnx2x_setup_dmae(struct bnx2x *bp) 6912{ 6913 bp->dmae_ready = 0; 6914 spin_lock_init(&bp->dmae_lock); 6915} 6916 6917static void bnx2x_init_pxp(struct bnx2x *bp) 6918{ 6919 u16 devctl; 6920 int r_order, w_order; 6921 6922 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); 6923 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl); 6924 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); 6925 if (bp->mrrs == -1) 6926 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12); 6927 else { 6928 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); 6929 r_order = bp->mrrs; 6930 } 6931 6932 bnx2x_init_pxp_arb(bp, r_order, w_order); 6933} 6934 6935static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 6936{ 6937 int is_required; 6938 u32 val; 6939 int port; 6940 6941 if (BP_NOMCP(bp)) 6942 return; 6943 6944 is_required = 0; 6945 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & 6946 SHARED_HW_CFG_FAN_FAILURE_MASK; 6947 6948 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) 6949 is_required = 1; 6950 6951 /* 6952 * The fan failure mechanism is usually related to the PHY type since 6953 * the power consumption of the board is affected by the PHY. Currently, 6954 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 6955 */ 6956 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) 6957 for (port = PORT_0; port < PORT_MAX; port++) { 6958 is_required |= 6959 bnx2x_fan_failure_det_req( 6960 bp, 6961 bp->common.shmem_base, 6962 bp->common.shmem2_base, 6963 port); 6964 } 6965 6966 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required); 6967 6968 if (is_required == 0) 6969 return; 6970 6971 /* Fan failure is indicated by SPIO 5 */ 6972 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 6973 6974 /* set to active low mode */ 6975 val = REG_RD(bp, MISC_REG_SPIO_INT); 6976 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 6977 REG_WR(bp, MISC_REG_SPIO_INT, val); 6978 6979 /* enable interrupt to signal the IGU */ 6980 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 6981 val |= MISC_SPIO_SPIO5; 6982 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); 6983} 6984 6985void bnx2x_pf_disable(struct bnx2x *bp) 6986{ 6987 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 6988 val &= ~IGU_PF_CONF_FUNC_EN; 6989 6990 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 6991 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 6992 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); 6993} 6994 6995static void bnx2x__common_init_phy(struct bnx2x *bp) 6996{ 6997 u32 shmem_base[2], shmem2_base[2]; 6998 /* Avoid common init in case MFW supports LFA */ 6999 if (SHMEM2_RD(bp, size) > 7000 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 7001 return; 7002 shmem_base[0] = bp->common.shmem_base; 7003 shmem2_base[0] = bp->common.shmem2_base; 7004 if (!CHIP_IS_E1x(bp)) { 7005 shmem_base[1] = 7006 SHMEM2_RD(bp, other_shmem_base_addr); 7007 shmem2_base[1] = 7008 SHMEM2_RD(bp, other_shmem2_base_addr); 7009 } 7010 bnx2x_acquire_phy_lock(bp); 7011 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, 7012 bp->common.chip_id); 7013 bnx2x_release_phy_lock(bp); 7014} 7015 7016static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) 7017{ 7018 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); 7019 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); 7020 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); 7021 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); 7022 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); 7023 7024 /* make sure this value is 0 */ 7025 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); 7026 7027 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); 7028 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); 7029 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); 7030 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); 7031} 7032 7033static void bnx2x_set_endianity(struct bnx2x *bp) 7034{ 7035#ifdef __BIG_ENDIAN 7036 bnx2x_config_endianity(bp, 1); 7037#else 7038 bnx2x_config_endianity(bp, 0); 7039#endif 7040} 7041 7042static void bnx2x_reset_endianity(struct bnx2x *bp) 7043{ 7044 bnx2x_config_endianity(bp, 0); 7045} 7046 7047/** 7048 * bnx2x_init_hw_common - initialize the HW at the COMMON phase. 7049 * 7050 * @bp: driver handle 7051 */ 7052static int bnx2x_init_hw_common(struct bnx2x *bp) 7053{ 7054 u32 val; 7055 7056 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); 7057 7058 /* 7059 * take the RESET lock to protect undi_unload flow from accessing 7060 * registers while we're resetting the chip 7061 */ 7062 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 7063 7064 bnx2x_reset_common(bp); 7065 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); 7066 7067 val = 0xfffc; 7068 if (CHIP_IS_E3(bp)) { 7069 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 7070 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 7071 } 7072 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); 7073 7074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 7075 7076 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); 7077 7078 if (!CHIP_IS_E1x(bp)) { 7079 u8 abs_func_id; 7080 7081 /** 7082 * 4-port mode or 2-port mode we need to turn of master-enable 7083 * for everyone, after that, turn it back on for self. 7084 * so, we disregard multi-function or not, and always disable 7085 * for all functions on the given path, this means 0,2,4,6 for 7086 * path 0 and 1,3,5,7 for path 1 7087 */ 7088 for (abs_func_id = BP_PATH(bp); 7089 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) { 7090 if (abs_func_id == BP_ABS_FUNC(bp)) { 7091 REG_WR(bp, 7092 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 7093 1); 7094 continue; 7095 } 7096 7097 bnx2x_pretend_func(bp, abs_func_id); 7098 /* clear pf enable */ 7099 bnx2x_pf_disable(bp); 7100 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 7101 } 7102 } 7103 7104 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); 7105 if (CHIP_IS_E1(bp)) { 7106 /* enable HW interrupt from PXP on USDM overflow 7107 bit 16 on INT_MASK_0 */ 7108 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); 7109 } 7110 7111 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); 7112 bnx2x_init_pxp(bp); 7113 bnx2x_set_endianity(bp); 7114 bnx2x_ilt_init_page_size(bp, INITOP_SET); 7115 7116 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) 7117 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 7118 7119 /* let the HW do it's magic ... */ 7120 msleep(100); 7121 /* finish PXP init */ 7122 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); 7123 if (val != 1) { 7124 BNX2X_ERR("PXP2 CFG failed\n"); 7125 return -EBUSY; 7126 } 7127 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); 7128 if (val != 1) { 7129 BNX2X_ERR("PXP2 RD_INIT failed\n"); 7130 return -EBUSY; 7131 } 7132 7133 /* Timers bug workaround E2 only. We need to set the entire ILT to 7134 * have entries with value "0" and valid bit on. 7135 * This needs to be done by the first PF that is loaded in a path 7136 * (i.e. common phase) 7137 */ 7138 if (!CHIP_IS_E1x(bp)) { 7139/* In E2 there is a bug in the timers block that can cause function 6 / 7 7140 * (i.e. vnic3) to start even if it is marked as "scan-off". 7141 * This occurs when a different function (func2,3) is being marked 7142 * as "scan-off". Real-life scenario for example: if a driver is being 7143 * load-unloaded while func6,7 are down. This will cause the timer to access 7144 * the ilt, translate to a logical address and send a request to read/write. 7145 * Since the ilt for the function that is down is not valid, this will cause 7146 * a translation error which is unrecoverable. 7147 * The Workaround is intended to make sure that when this happens nothing fatal 7148 * will occur. The workaround: 7149 * 1. First PF driver which loads on a path will: 7150 * a. After taking the chip out of reset, by using pretend, 7151 * it will write "0" to the following registers of 7152 * the other vnics. 7153 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 7154 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 7155 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 7156 * And for itself it will write '1' to 7157 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 7158 * dmae-operations (writing to pram for example.) 7159 * note: can be done for only function 6,7 but cleaner this 7160 * way. 7161 * b. Write zero+valid to the entire ILT. 7162 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 7163 * VNIC3 (of that port). The range allocated will be the 7164 * entire ILT. This is needed to prevent ILT range error. 7165 * 2. Any PF driver load flow: 7166 * a. ILT update with the physical addresses of the allocated 7167 * logical pages. 7168 * b. Wait 20msec. - note that this timeout is needed to make 7169 * sure there are no requests in one of the PXP internal 7170 * queues with "old" ILT addresses. 7171 * c. PF enable in the PGLC. 7172 * d. Clear the was_error of the PF in the PGLC. (could have 7173 * occurred while driver was down) 7174 * e. PF enable in the CFC (WEAK + STRONG) 7175 * f. Timers scan enable 7176 * 3. PF driver unload flow: 7177 * a. Clear the Timers scan_en. 7178 * b. Polling for scan_on=0 for that PF. 7179 * c. Clear the PF enable bit in the PXP. 7180 * d. Clear the PF enable in the CFC (WEAK + STRONG) 7181 * e. Write zero+valid to all ILT entries (The valid bit must 7182 * stay set) 7183 * f. If this is VNIC 3 of a port then also init 7184 * first_timers_ilt_entry to zero and last_timers_ilt_entry 7185 * to the last entry in the ILT. 7186 * 7187 * Notes: 7188 * Currently the PF error in the PGLC is non recoverable. 7189 * In the future the there will be a recovery routine for this error. 7190 * Currently attention is masked. 7191 * Having an MCP lock on the load/unload process does not guarantee that 7192 * there is no Timer disable during Func6/7 enable. This is because the 7193 * Timers scan is currently being cleared by the MCP on FLR. 7194 * Step 2.d can be done only for PF6/7 and the driver can also check if 7195 * there is error before clearing it. But the flow above is simpler and 7196 * more general. 7197 * All ILT entries are written by zero+valid and not just PF6/7 7198 * ILT entries since in the future the ILT entries allocation for 7199 * PF-s might be dynamic. 7200 */ 7201 struct ilt_client_info ilt_cli; 7202 struct bnx2x_ilt ilt; 7203 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 7204 memset(&ilt, 0, sizeof(struct bnx2x_ilt)); 7205 7206 /* initialize dummy TM client */ 7207 ilt_cli.start = 0; 7208 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 7209 ilt_cli.client_num = ILT_CLIENT_TM; 7210 7211 /* Step 1: set zeroes to all ilt page entries with valid bit on 7212 * Step 2: set the timers first/last ilt entry to point 7213 * to the entire range to prevent ILT range error for 3rd/4th 7214 * vnic (this code assumes existence of the vnic) 7215 * 7216 * both steps performed by call to bnx2x_ilt_client_init_op() 7217 * with dummy TM client 7218 * 7219 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 7220 * and his brother are split registers 7221 */ 7222 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); 7223 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); 7224 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); 7225 7226 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); 7227 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); 7228 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 7229 } 7230 7231 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); 7232 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); 7233 7234 if (!CHIP_IS_E1x(bp)) { 7235 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : 7236 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); 7237 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); 7238 7239 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); 7240 7241 /* let the HW do it's magic ... */ 7242 do { 7243 msleep(200); 7244 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); 7245 } while (factor-- && (val != 1)); 7246 7247 if (val != 1) { 7248 BNX2X_ERR("ATC_INIT failed\n"); 7249 return -EBUSY; 7250 } 7251 } 7252 7253 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); 7254 7255 bnx2x_iov_init_dmae(bp); 7256 7257 /* clean the DMAE memory */ 7258 bp->dmae_ready = 1; 7259 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); 7260 7261 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); 7262 7263 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); 7264 7265 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); 7266 7267 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); 7268 7269 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); 7270 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); 7271 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); 7272 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); 7273 7274 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); 7275 7276 /* QM queues pointers table */ 7277 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); 7278 7279 /* soft reset pulse */ 7280 REG_WR(bp, QM_REG_SOFT_RESET, 1); 7281 REG_WR(bp, QM_REG_SOFT_RESET, 0); 7282 7283 if (CNIC_SUPPORT(bp)) 7284 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); 7285 7286 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); 7287 7288 if (!CHIP_REV_IS_SLOW(bp)) 7289 /* enable hw interrupt from doorbell Q */ 7290 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); 7291 7292 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); 7293 7294 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); 7295 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); 7296 7297 if (!CHIP_IS_E1(bp)) 7298 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); 7299 7300 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { 7301 if (IS_MF_AFEX(bp)) { 7302 /* configure that VNTag and VLAN headers must be 7303 * received in afex mode 7304 */ 7305 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); 7306 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); 7307 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 7308 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 7309 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); 7310 } else { 7311 /* Bit-map indicating which L2 hdrs may appear 7312 * after the basic Ethernet header 7313 */ 7314 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 7315 bp->path_has_ovlan ? 7 : 6); 7316 } 7317 } 7318 7319 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); 7320 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); 7321 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); 7322 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); 7323 7324 if (!CHIP_IS_E1x(bp)) { 7325 /* reset VFC memories */ 7326 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 7327 VFC_MEMORIES_RST_REG_CAM_RST | 7328 VFC_MEMORIES_RST_REG_RAM_RST); 7329 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 7330 VFC_MEMORIES_RST_REG_CAM_RST | 7331 VFC_MEMORIES_RST_REG_RAM_RST); 7332 7333 msleep(20); 7334 } 7335 7336 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); 7337 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); 7338 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); 7339 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); 7340 7341 /* sync semi rtc */ 7342 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 7343 0x80000000); 7344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 7345 0x80000000); 7346 7347 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); 7348 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); 7349 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); 7350 7351 if (!CHIP_IS_E1x(bp)) { 7352 if (IS_MF_AFEX(bp)) { 7353 /* configure that VNTag and VLAN headers must be 7354 * sent in afex mode 7355 */ 7356 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); 7357 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); 7358 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 7359 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 7360 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); 7361 } else { 7362 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 7363 bp->path_has_ovlan ? 7 : 6); 7364 } 7365 } 7366 7367 REG_WR(bp, SRC_REG_SOFT_RST, 1); 7368 7369 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); 7370 7371 if (CNIC_SUPPORT(bp)) { 7372 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); 7373 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 7374 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); 7375 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); 7376 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); 7377 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 7378 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); 7379 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 7380 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); 7381 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); 7382 } 7383 REG_WR(bp, SRC_REG_SOFT_RST, 0); 7384 7385 if (sizeof(union cdu_context) != 1024) 7386 /* we currently assume that a context is 1024 bytes */ 7387 dev_alert(&bp->pdev->dev, 7388 "please adjust the size of cdu_context(%ld)\n", 7389 (long)sizeof(union cdu_context)); 7390 7391 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 7392 val = (4 << 24) + (0 << 12) + 1024; 7393 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); 7394 7395 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); 7396 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); 7397 /* enable context validation interrupt from CFC */ 7398 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); 7399 7400 /* set the thresholds to prevent CFC/CDU race */ 7401 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); 7402 7403 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); 7404 7405 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) 7406 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); 7407 7408 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); 7409 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); 7410 7411 /* Reset PCIE errors for debug */ 7412 REG_WR(bp, 0x2814, 0xffffffff); 7413 REG_WR(bp, 0x3820, 0xffffffff); 7414 7415 if (!CHIP_IS_E1x(bp)) { 7416 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 7417 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 7418 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 7419 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 7420 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 7421 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 7422 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 7423 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 7424 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 7425 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 7426 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 7427 } 7428 7429 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); 7430 if (!CHIP_IS_E1(bp)) { 7431 /* in E3 this done in per-port section */ 7432 if (!CHIP_IS_E3(bp)) 7433 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7434 } 7435 if (CHIP_IS_E1H(bp)) 7436 /* not applicable for E2 (and above ...) */ 7437 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); 7438 7439 if (CHIP_REV_IS_SLOW(bp)) 7440 msleep(200); 7441 7442 /* finish CFC init */ 7443 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); 7444 if (val != 1) { 7445 BNX2X_ERR("CFC LL_INIT failed\n"); 7446 return -EBUSY; 7447 } 7448 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); 7449 if (val != 1) { 7450 BNX2X_ERR("CFC AC_INIT failed\n"); 7451 return -EBUSY; 7452 } 7453 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 7454 if (val != 1) { 7455 BNX2X_ERR("CFC CAM_INIT failed\n"); 7456 return -EBUSY; 7457 } 7458 REG_WR(bp, CFC_REG_DEBUG0, 0); 7459 7460 if (CHIP_IS_E1(bp)) { 7461 /* read NIG statistic 7462 to see if this is our first up since powerup */ 7463 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); 7464 val = *bnx2x_sp(bp, wb_data[0]); 7465 7466 /* do internal memory self test */ 7467 if ((val == 0) && bnx2x_int_mem_test(bp)) { 7468 BNX2X_ERR("internal mem self test failed\n"); 7469 return -EBUSY; 7470 } 7471 } 7472 7473 bnx2x_setup_fan_failure_detection(bp); 7474 7475 /* clear PXP2 attentions */ 7476 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 7477 7478 bnx2x_enable_blocks_attention(bp); 7479 bnx2x_enable_blocks_parity(bp); 7480 7481 if (!BP_NOMCP(bp)) { 7482 if (CHIP_IS_E1x(bp)) 7483 bnx2x__common_init_phy(bp); 7484 } else 7485 BNX2X_ERR("Bootcode is missing - can not initialize link\n"); 7486 7487 if (SHMEM2_HAS(bp, netproc_fw_ver)) 7488 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM)); 7489 7490 return 0; 7491} 7492 7493/** 7494 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase. 7495 * 7496 * @bp: driver handle 7497 */ 7498static int bnx2x_init_hw_common_chip(struct bnx2x *bp) 7499{ 7500 int rc = bnx2x_init_hw_common(bp); 7501 7502 if (rc) 7503 return rc; 7504 7505 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 7506 if (!BP_NOMCP(bp)) 7507 bnx2x__common_init_phy(bp); 7508 7509 return 0; 7510} 7511 7512static int bnx2x_init_hw_port(struct bnx2x *bp) 7513{ 7514 int port = BP_PORT(bp); 7515 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 7516 u32 low, high; 7517 u32 val, reg; 7518 7519 DP(NETIF_MSG_HW, "starting port init port %d\n", port); 7520 7521 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 7522 7523 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 7524 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7525 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7526 7527 /* Timers bug workaround: disables the pf_master bit in pglue at 7528 * common phase, we need to enable it here before any dmae access are 7529 * attempted. Therefore we manually added the enable-master to the 7530 * port phase (it also happens in the function phase) 7531 */ 7532 if (!CHIP_IS_E1x(bp)) 7533 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 7534 7535 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 7536 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 7537 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 7538 bnx2x_init_block(bp, BLOCK_QM, init_phase); 7539 7540 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 7541 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 7542 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 7543 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 7544 7545 /* QM cid (connection) count */ 7546 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); 7547 7548 if (CNIC_SUPPORT(bp)) { 7549 bnx2x_init_block(bp, BLOCK_TM, init_phase); 7550 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); 7551 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 7552 } 7553 7554 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 7555 7556 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 7557 7558 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { 7559 7560 if (IS_MF(bp)) 7561 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); 7562 else if (bp->dev->mtu > 4096) { 7563 if (bp->flags & ONE_PORT_FLAG) 7564 low = 160; 7565 else { 7566 val = bp->dev->mtu; 7567 /* (24*1024 + val*4)/256 */ 7568 low = 96 + (val/64) + 7569 ((val % 64) ? 1 : 0); 7570 } 7571 } else 7572 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); 7573 high = low + 56; /* 14*1024/256 */ 7574 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 7575 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 7576 } 7577 7578 if (CHIP_MODE_IS_4_PORT(bp)) 7579 REG_WR(bp, (BP_PORT(bp) ? 7580 BRB1_REG_MAC_GUARANTIED_1 : 7581 BRB1_REG_MAC_GUARANTIED_0), 40); 7582 7583 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 7584 if (CHIP_IS_E3B0(bp)) { 7585 if (IS_MF_AFEX(bp)) { 7586 /* configure headers for AFEX mode */ 7587 REG_WR(bp, BP_PORT(bp) ? 7588 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7589 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 7590 REG_WR(bp, BP_PORT(bp) ? 7591 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 7592 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 7593 REG_WR(bp, BP_PORT(bp) ? 7594 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 7595 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 7596 } else { 7597 /* Ovlan exists only if we are in multi-function + 7598 * switch-dependent mode, in switch-independent there 7599 * is no ovlan headers 7600 */ 7601 REG_WR(bp, BP_PORT(bp) ? 7602 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 7603 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 7604 (bp->path_has_ovlan ? 7 : 6)); 7605 } 7606 } 7607 7608 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 7609 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 7610 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 7611 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 7612 7613 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 7614 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 7615 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 7616 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 7617 7618 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 7619 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 7620 7621 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 7622 7623 if (CHIP_IS_E1x(bp)) { 7624 /* configure PBF to work without PAUSE mtu 9000 */ 7625 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 7626 7627 /* update threshold */ 7628 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 7629 /* update init credit */ 7630 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 7631 7632 /* probe changes */ 7633 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); 7634 udelay(50); 7635 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); 7636 } 7637 7638 if (CNIC_SUPPORT(bp)) 7639 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 7640 7641 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 7642 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 7643 7644 if (CHIP_IS_E1(bp)) { 7645 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 7646 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 7647 } 7648 bnx2x_init_block(bp, BLOCK_HC, init_phase); 7649 7650 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 7651 7652 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 7653 /* init aeu_mask_attn_func_0/1: 7654 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use 7655 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF 7656 * bits 4-7 are used for "per vn group attention" */ 7657 val = IS_MF(bp) ? 0xF7 : 0x7; 7658 /* Enable DCBX attention for all but E1 */ 7659 val |= CHIP_IS_E1(bp) ? 0 : 0x10; 7660 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 7661 7662 /* SCPAD_PARITY should NOT trigger close the gates */ 7663 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0; 7664 REG_WR(bp, reg, 7665 REG_RD(bp, reg) & 7666 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); 7667 7668 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0; 7669 REG_WR(bp, reg, 7670 REG_RD(bp, reg) & 7671 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY); 7672 7673 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 7674 7675 if (!CHIP_IS_E1x(bp)) { 7676 /* Bit-map indicating which L2 hdrs may appear after the 7677 * basic Ethernet header 7678 */ 7679 if (IS_MF_AFEX(bp)) 7680 REG_WR(bp, BP_PORT(bp) ? 7681 NIG_REG_P1_HDRS_AFTER_BASIC : 7682 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 7683 else 7684 REG_WR(bp, BP_PORT(bp) ? 7685 NIG_REG_P1_HDRS_AFTER_BASIC : 7686 NIG_REG_P0_HDRS_AFTER_BASIC, 7687 IS_MF_SD(bp) ? 7 : 6); 7688 7689 if (CHIP_IS_E3(bp)) 7690 REG_WR(bp, BP_PORT(bp) ? 7691 NIG_REG_LLH1_MF_MODE : 7692 NIG_REG_LLH_MF_MODE, IS_MF(bp)); 7693 } 7694 if (!CHIP_IS_E3(bp)) 7695 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 7696 7697 if (!CHIP_IS_E1(bp)) { 7698 /* 0x2 disable mf_ov, 0x1 enable */ 7699 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 7700 (IS_MF_SD(bp) ? 0x1 : 0x2)); 7701 7702 if (!CHIP_IS_E1x(bp)) { 7703 val = 0; 7704 switch (bp->mf_mode) { 7705 case MULTI_FUNCTION_SD: 7706 val = 1; 7707 break; 7708 case MULTI_FUNCTION_SI: 7709 case MULTI_FUNCTION_AFEX: 7710 val = 2; 7711 break; 7712 } 7713 7714 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : 7715 NIG_REG_LLH0_CLS_TYPE), val); 7716 } 7717 { 7718 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 7719 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 7720 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 7721 } 7722 } 7723 7724 /* If SPIO5 is set to generate interrupts, enable it for this port */ 7725 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); 7726 if (val & MISC_SPIO_SPIO5) { 7727 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 7728 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 7729 val = REG_RD(bp, reg_addr); 7730 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 7731 REG_WR(bp, reg_addr, val); 7732 } 7733 7734 if (CHIP_IS_E3B0(bp)) 7735 bp->flags |= PTP_SUPPORTED; 7736 7737 return 0; 7738} 7739 7740static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 7741{ 7742 int reg; 7743 u32 wb_write[2]; 7744 7745 if (CHIP_IS_E1(bp)) 7746 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 7747 else 7748 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 7749 7750 wb_write[0] = ONCHIP_ADDR1(addr); 7751 wb_write[1] = ONCHIP_ADDR2(addr); 7752 REG_WR_DMAE(bp, reg, wb_write, 2); 7753} 7754 7755void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) 7756{ 7757 u32 data, ctl, cnt = 100; 7758 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 7759 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 7760 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 7761 u32 sb_bit = 1 << (idu_sb_id%32); 7762 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 7763 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 7764 7765 /* Not supported in BC mode */ 7766 if (CHIP_INT_MODE_IS_BC(bp)) 7767 return; 7768 7769 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 7770 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 7771 IGU_REGULAR_CLEANUP_SET | 7772 IGU_REGULAR_BCLEANUP; 7773 7774 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 7775 func_encode << IGU_CTRL_REG_FID_SHIFT | 7776 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 7777 7778 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7779 data, igu_addr_data); 7780 REG_WR(bp, igu_addr_data, data); 7781 barrier(); 7782 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 7783 ctl, igu_addr_ctl); 7784 REG_WR(bp, igu_addr_ctl, ctl); 7785 barrier(); 7786 7787 /* wait for clean up to finish */ 7788 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 7789 msleep(20); 7790 7791 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 7792 DP(NETIF_MSG_HW, 7793 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n", 7794 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 7795 } 7796} 7797 7798static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) 7799{ 7800 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); 7801} 7802 7803static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) 7804{ 7805 u32 i, base = FUNC_ILT_BASE(func); 7806 for (i = base; i < base + ILT_PER_FUNC; i++) 7807 bnx2x_ilt_wr(bp, i, 0); 7808} 7809 7810static void bnx2x_init_searcher(struct bnx2x *bp) 7811{ 7812 int port = BP_PORT(bp); 7813 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); 7814 /* T1 hash bits value determines the T1 number of entries */ 7815 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 7816} 7817 7818static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) 7819{ 7820 int rc; 7821 struct bnx2x_func_state_params func_params = {NULL}; 7822 struct bnx2x_func_switch_update_params *switch_update_params = 7823 &func_params.params.switch_update; 7824 7825 /* Prepare parameters for function state transitions */ 7826 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 7827 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 7828 7829 func_params.f_obj = &bp->func_obj; 7830 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 7831 7832 /* Function parameters */ 7833 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 7834 &switch_update_params->changes); 7835 if (suspend) 7836 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND, 7837 &switch_update_params->changes); 7838 7839 rc = bnx2x_func_state_change(bp, &func_params); 7840 7841 return rc; 7842} 7843 7844static int bnx2x_reset_nic_mode(struct bnx2x *bp) 7845{ 7846 int rc, i, port = BP_PORT(bp); 7847 int vlan_en = 0, mac_en[NUM_MACS]; 7848 7849 /* Close input from network */ 7850 if (bp->mf_mode == SINGLE_FUNCTION) { 7851 bnx2x_set_rx_filter(&bp->link_params, 0); 7852 } else { 7853 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : 7854 NIG_REG_LLH0_FUNC_EN); 7855 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7856 NIG_REG_LLH0_FUNC_EN, 0); 7857 for (i = 0; i < NUM_MACS; i++) { 7858 mac_en[i] = REG_RD(bp, port ? 7859 (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7860 4 * i) : 7861 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 7862 4 * i)); 7863 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7864 4 * i) : 7865 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0); 7866 } 7867 } 7868 7869 /* Close BMC to host */ 7870 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7871 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0); 7872 7873 /* Suspend Tx switching to the PF. Completion of this ramrod 7874 * further guarantees that all the packets of that PF / child 7875 * VFs in BRB were processed by the Parser, so it is safe to 7876 * change the NIC_MODE register. 7877 */ 7878 rc = bnx2x_func_switch_update(bp, 1); 7879 if (rc) { 7880 BNX2X_ERR("Can't suspend tx-switching!\n"); 7881 return rc; 7882 } 7883 7884 /* Change NIC_MODE register */ 7885 REG_WR(bp, PRS_REG_NIC_MODE, 0); 7886 7887 /* Open input from network */ 7888 if (bp->mf_mode == SINGLE_FUNCTION) { 7889 bnx2x_set_rx_filter(&bp->link_params, 1); 7890 } else { 7891 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : 7892 NIG_REG_LLH0_FUNC_EN, vlan_en); 7893 for (i = 0; i < NUM_MACS; i++) { 7894 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + 7895 4 * i) : 7896 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 7897 mac_en[i]); 7898 } 7899 } 7900 7901 /* Enable BMC to host */ 7902 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : 7903 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1); 7904 7905 /* Resume Tx switching to the PF */ 7906 rc = bnx2x_func_switch_update(bp, 0); 7907 if (rc) { 7908 BNX2X_ERR("Can't resume tx-switching!\n"); 7909 return rc; 7910 } 7911 7912 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 7913 return 0; 7914} 7915 7916int bnx2x_init_hw_func_cnic(struct bnx2x *bp) 7917{ 7918 int rc; 7919 7920 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); 7921 7922 if (CONFIGURE_NIC_MODE(bp)) { 7923 /* Configure searcher as part of function hw init */ 7924 bnx2x_init_searcher(bp); 7925 7926 /* Reset NIC mode */ 7927 rc = bnx2x_reset_nic_mode(bp); 7928 if (rc) 7929 BNX2X_ERR("Can't change NIC mode!\n"); 7930 return rc; 7931 } 7932 7933 return 0; 7934} 7935 7936/* previous driver DMAE transaction may have occurred when pre-boot stage ended 7937 * and boot began, or when kdump kernel was loaded. Either case would invalidate 7938 * the addresses of the transaction, resulting in was-error bit set in the pci 7939 * causing all hw-to-host pcie transactions to timeout. If this happened we want 7940 * to clear the interrupt which detected this from the pglueb and the was done 7941 * bit 7942 */ 7943static void bnx2x_clean_pglue_errors(struct bnx2x *bp) 7944{ 7945 if (!CHIP_IS_E1x(bp)) 7946 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 7947 1 << BP_ABS_FUNC(bp)); 7948} 7949 7950static int bnx2x_init_hw_func(struct bnx2x *bp) 7951{ 7952 int port = BP_PORT(bp); 7953 int func = BP_FUNC(bp); 7954 int init_phase = PHASE_PF0 + func; 7955 struct bnx2x_ilt *ilt = BP_ILT(bp); 7956 u16 cdu_ilt_start; 7957 u32 addr, val; 7958 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 7959 int i, main_mem_width, rc; 7960 7961 DP(NETIF_MSG_HW, "starting func init func %d\n", func); 7962 7963 /* FLR cleanup - hmmm */ 7964 if (!CHIP_IS_E1x(bp)) { 7965 rc = bnx2x_pf_flr_clnup(bp); 7966 if (rc) { 7967 bnx2x_fw_dump(bp); 7968 return rc; 7969 } 7970 } 7971 7972 /* set MSI reconfigure capability */ 7973 if (bp->common.int_block == INT_BLOCK_HC) { 7974 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 7975 val = REG_RD(bp, addr); 7976 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 7977 REG_WR(bp, addr, val); 7978 } 7979 7980 bnx2x_init_block(bp, BLOCK_PXP, init_phase); 7981 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); 7982 7983 ilt = BP_ILT(bp); 7984 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7985 7986 if (IS_SRIOV(bp)) 7987 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS; 7988 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); 7989 7990 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes 7991 * those of the VFs, so start line should be reset 7992 */ 7993 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 7994 for (i = 0; i < L2_ILT_LINES(bp); i++) { 7995 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; 7996 ilt->lines[cdu_ilt_start + i].page_mapping = 7997 bp->context[i].cxt_mapping; 7998 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; 7999 } 8000 8001 bnx2x_ilt_init_op(bp, INITOP_SET); 8002 8003 if (!CONFIGURE_NIC_MODE(bp)) { 8004 bnx2x_init_searcher(bp); 8005 REG_WR(bp, PRS_REG_NIC_MODE, 0); 8006 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n"); 8007 } else { 8008 /* Set NIC mode */ 8009 REG_WR(bp, PRS_REG_NIC_MODE, 1); 8010 DP(NETIF_MSG_IFUP, "NIC MODE configured\n"); 8011 } 8012 8013 if (!CHIP_IS_E1x(bp)) { 8014 u32 pf_conf = IGU_PF_CONF_FUNC_EN; 8015 8016 /* Turn on a single ISR mode in IGU if driver is going to use 8017 * INT#x or MSI 8018 */ 8019 if (!(bp->flags & USING_MSIX_FLAG)) 8020 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 8021 /* 8022 * Timers workaround bug: function init part. 8023 * Need to wait 20msec after initializing ILT, 8024 * needed to make sure there are no requests in 8025 * one of the PXP internal queues with "old" ILT addresses 8026 */ 8027 msleep(20); 8028 /* 8029 * Master enable - Due to WB DMAE writes performed before this 8030 * register is re-initialized as part of the regular function 8031 * init 8032 */ 8033 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 8034 /* Enable the function in IGU */ 8035 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); 8036 } 8037 8038 bp->dmae_ready = 1; 8039 8040 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); 8041 8042 bnx2x_clean_pglue_errors(bp); 8043 8044 bnx2x_init_block(bp, BLOCK_ATC, init_phase); 8045 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); 8046 bnx2x_init_block(bp, BLOCK_NIG, init_phase); 8047 bnx2x_init_block(bp, BLOCK_SRC, init_phase); 8048 bnx2x_init_block(bp, BLOCK_MISC, init_phase); 8049 bnx2x_init_block(bp, BLOCK_TCM, init_phase); 8050 bnx2x_init_block(bp, BLOCK_UCM, init_phase); 8051 bnx2x_init_block(bp, BLOCK_CCM, init_phase); 8052 bnx2x_init_block(bp, BLOCK_XCM, init_phase); 8053 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); 8054 bnx2x_init_block(bp, BLOCK_USEM, init_phase); 8055 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); 8056 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); 8057 8058 if (!CHIP_IS_E1x(bp)) 8059 REG_WR(bp, QM_REG_PF_EN, 1); 8060 8061 if (!CHIP_IS_E1x(bp)) { 8062 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8063 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8064 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8065 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); 8066 } 8067 bnx2x_init_block(bp, BLOCK_QM, init_phase); 8068 8069 bnx2x_init_block(bp, BLOCK_TM, init_phase); 8070 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); 8071 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ 8072 8073 bnx2x_iov_init_dq(bp); 8074 8075 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); 8076 bnx2x_init_block(bp, BLOCK_PRS, init_phase); 8077 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); 8078 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); 8079 bnx2x_init_block(bp, BLOCK_USDM, init_phase); 8080 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); 8081 bnx2x_init_block(bp, BLOCK_UPB, init_phase); 8082 bnx2x_init_block(bp, BLOCK_XPB, init_phase); 8083 bnx2x_init_block(bp, BLOCK_PBF, init_phase); 8084 if (!CHIP_IS_E1x(bp)) 8085 REG_WR(bp, PBF_REG_DISABLE_PF, 0); 8086 8087 bnx2x_init_block(bp, BLOCK_CDU, init_phase); 8088 8089 bnx2x_init_block(bp, BLOCK_CFC, init_phase); 8090 8091 if (!CHIP_IS_E1x(bp)) 8092 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); 8093 8094 if (IS_MF(bp)) { 8095 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { 8096 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); 8097 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, 8098 bp->mf_ov); 8099 } 8100 } 8101 8102 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); 8103 8104 /* HC init per function */ 8105 if (bp->common.int_block == INT_BLOCK_HC) { 8106 if (CHIP_IS_E1H(bp)) { 8107 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8108 8109 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 8110 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 8111 } 8112 bnx2x_init_block(bp, BLOCK_HC, init_phase); 8113 8114 } else { 8115 int num_segs, sb_idx, prod_offset; 8116 8117 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8118 8119 if (!CHIP_IS_E1x(bp)) { 8120 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 8121 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 8122 } 8123 8124 bnx2x_init_block(bp, BLOCK_IGU, init_phase); 8125 8126 if (!CHIP_IS_E1x(bp)) { 8127 int dsb_idx = 0; 8128 /** 8129 * Producer memory: 8130 * E2 mode: address 0-135 match to the mapping memory; 8131 * 136 - PF0 default prod; 137 - PF1 default prod; 8132 * 138 - PF2 default prod; 139 - PF3 default prod; 8133 * 140 - PF0 attn prod; 141 - PF1 attn prod; 8134 * 142 - PF2 attn prod; 143 - PF3 attn prod; 8135 * 144-147 reserved. 8136 * 8137 * E1.5 mode - In backward compatible mode; 8138 * for non default SB; each even line in the memory 8139 * holds the U producer and each odd line hold 8140 * the C producer. The first 128 producers are for 8141 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 8142 * producers are for the DSB for each PF. 8143 * Each PF has five segments: (the order inside each 8144 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 8145 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 8146 * 144-147 attn prods; 8147 */ 8148 /* non-default-status-blocks */ 8149 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 8150 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 8151 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { 8152 prod_offset = (bp->igu_base_sb + sb_idx) * 8153 num_segs; 8154 8155 for (i = 0; i < num_segs; i++) { 8156 addr = IGU_REG_PROD_CONS_MEMORY + 8157 (prod_offset + i) * 4; 8158 REG_WR(bp, addr, 0); 8159 } 8160 /* send consumer update with value 0 */ 8161 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, 8162 USTORM_ID, 0, IGU_INT_NOP, 1); 8163 bnx2x_igu_clear_sb(bp, 8164 bp->igu_base_sb + sb_idx); 8165 } 8166 8167 /* default-status-blocks */ 8168 num_segs = CHIP_INT_MODE_IS_BC(bp) ? 8169 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 8170 8171 if (CHIP_MODE_IS_4_PORT(bp)) 8172 dsb_idx = BP_FUNC(bp); 8173 else 8174 dsb_idx = BP_VN(bp); 8175 8176 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 8177 IGU_BC_BASE_DSB_PROD + dsb_idx : 8178 IGU_NORM_BASE_DSB_PROD + dsb_idx); 8179 8180 /* 8181 * igu prods come in chunks of E1HVN_MAX (4) - 8182 * does not matters what is the current chip mode 8183 */ 8184 for (i = 0; i < (num_segs * E1HVN_MAX); 8185 i += E1HVN_MAX) { 8186 addr = IGU_REG_PROD_CONS_MEMORY + 8187 (prod_offset + i)*4; 8188 REG_WR(bp, addr, 0); 8189 } 8190 /* send consumer update with 0 */ 8191 if (CHIP_INT_MODE_IS_BC(bp)) { 8192 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8193 USTORM_ID, 0, IGU_INT_NOP, 1); 8194 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8195 CSTORM_ID, 0, IGU_INT_NOP, 1); 8196 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8197 XSTORM_ID, 0, IGU_INT_NOP, 1); 8198 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8199 TSTORM_ID, 0, IGU_INT_NOP, 1); 8200 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8201 ATTENTION_ID, 0, IGU_INT_NOP, 1); 8202 } else { 8203 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8204 USTORM_ID, 0, IGU_INT_NOP, 1); 8205 bnx2x_ack_sb(bp, bp->igu_dsb_id, 8206 ATTENTION_ID, 0, IGU_INT_NOP, 1); 8207 } 8208 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); 8209 8210 /* !!! These should become driver const once 8211 rf-tool supports split-68 const */ 8212 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 8213 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 8214 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); 8215 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); 8216 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); 8217 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); 8218 } 8219 } 8220 8221 /* Reset PCIE errors for debug */ 8222 REG_WR(bp, 0x2114, 0xffffffff); 8223 REG_WR(bp, 0x2120, 0xffffffff); 8224 8225 if (CHIP_IS_E1x(bp)) { 8226 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 8227 main_mem_base = HC_REG_MAIN_MEMORY + 8228 BP_PORT(bp) * (main_mem_size * 4); 8229 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 8230 main_mem_width = 8; 8231 8232 val = REG_RD(bp, main_mem_prty_clr); 8233 if (val) 8234 DP(NETIF_MSG_HW, 8235 "Hmmm... Parity errors in HC block during function init (0x%x)!\n", 8236 val); 8237 8238 /* Clear "false" parity errors in MSI-X table */ 8239 for (i = main_mem_base; 8240 i < main_mem_base + main_mem_size * 4; 8241 i += main_mem_width) { 8242 bnx2x_read_dmae(bp, i, main_mem_width / 4); 8243 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), 8244 i, main_mem_width / 4); 8245 } 8246 /* Clear HC parity attention */ 8247 REG_RD(bp, main_mem_prty_clr); 8248 } 8249 8250#ifdef BNX2X_STOP_ON_ERROR 8251 /* Enable STORMs SP logging */ 8252 REG_WR8(bp, BAR_USTRORM_INTMEM + 8253 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8254 REG_WR8(bp, BAR_TSTRORM_INTMEM + 8255 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8256 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8257 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8258 REG_WR8(bp, BAR_XSTRORM_INTMEM + 8259 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); 8260#endif 8261 8262 bnx2x_phy_probe(&bp->link_params); 8263 8264 return 0; 8265} 8266 8267void bnx2x_free_mem_cnic(struct bnx2x *bp) 8268{ 8269 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); 8270 8271 if (!CHIP_IS_E1x(bp)) 8272 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, 8273 sizeof(struct host_hc_status_block_e2)); 8274 else 8275 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, 8276 sizeof(struct host_hc_status_block_e1x)); 8277 8278 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 8279} 8280 8281void bnx2x_free_mem(struct bnx2x *bp) 8282{ 8283 int i; 8284 8285 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 8286 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 8287 8288 if (IS_VF(bp)) 8289 return; 8290 8291 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, 8292 sizeof(struct host_sp_status_block)); 8293 8294 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, 8295 sizeof(struct bnx2x_slowpath)); 8296 8297 for (i = 0; i < L2_ILT_LINES(bp); i++) 8298 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, 8299 bp->context[i].size); 8300 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); 8301 8302 BNX2X_FREE(bp->ilt->lines); 8303 8304 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); 8305 8306 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, 8307 BCM_PAGE_SIZE * NUM_EQ_PAGES); 8308 8309 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); 8310 8311 bnx2x_iov_free_mem(bp); 8312} 8313 8314int bnx2x_alloc_mem_cnic(struct bnx2x *bp) 8315{ 8316 if (!CHIP_IS_E1x(bp)) { 8317 /* size = the status block + ramrod buffers */ 8318 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, 8319 sizeof(struct host_hc_status_block_e2)); 8320 if (!bp->cnic_sb.e2_sb) 8321 goto alloc_mem_err; 8322 } else { 8323 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, 8324 sizeof(struct host_hc_status_block_e1x)); 8325 if (!bp->cnic_sb.e1x_sb) 8326 goto alloc_mem_err; 8327 } 8328 8329 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { 8330 /* allocate searcher T2 table, as it wasn't allocated before */ 8331 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); 8332 if (!bp->t2) 8333 goto alloc_mem_err; 8334 } 8335 8336 /* write address to which L5 should insert its values */ 8337 bp->cnic_eth_dev.addr_drv_info_to_mcp = 8338 &bp->slowpath->drv_info_to_mcp; 8339 8340 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) 8341 goto alloc_mem_err; 8342 8343 return 0; 8344 8345alloc_mem_err: 8346 bnx2x_free_mem_cnic(bp); 8347 BNX2X_ERR("Can't allocate memory\n"); 8348 return -ENOMEM; 8349} 8350 8351int bnx2x_alloc_mem(struct bnx2x *bp) 8352{ 8353 int i, allocated, context_size; 8354 8355 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { 8356 /* allocate searcher T2 table */ 8357 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); 8358 if (!bp->t2) 8359 goto alloc_mem_err; 8360 } 8361 8362 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, 8363 sizeof(struct host_sp_status_block)); 8364 if (!bp->def_status_blk) 8365 goto alloc_mem_err; 8366 8367 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, 8368 sizeof(struct bnx2x_slowpath)); 8369 if (!bp->slowpath) 8370 goto alloc_mem_err; 8371 8372 /* Allocate memory for CDU context: 8373 * This memory is allocated separately and not in the generic ILT 8374 * functions because CDU differs in few aspects: 8375 * 1. There are multiple entities allocating memory for context - 8376 * 'regular' driver, CNIC and SRIOV driver. Each separately controls 8377 * its own ILT lines. 8378 * 2. Since CDU page-size is not a single 4KB page (which is the case 8379 * for the other ILT clients), to be efficient we want to support 8380 * allocation of sub-page-size in the last entry. 8381 * 3. Context pointers are used by the driver to pass to FW / update 8382 * the context (for the other ILT clients the pointers are used just to 8383 * free the memory during unload). 8384 */ 8385 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); 8386 8387 for (i = 0, allocated = 0; allocated < context_size; i++) { 8388 bp->context[i].size = min(CDU_ILT_PAGE_SZ, 8389 (context_size - allocated)); 8390 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, 8391 bp->context[i].size); 8392 if (!bp->context[i].vcxt) 8393 goto alloc_mem_err; 8394 allocated += bp->context[i].size; 8395 } 8396 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), 8397 GFP_KERNEL); 8398 if (!bp->ilt->lines) 8399 goto alloc_mem_err; 8400 8401 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) 8402 goto alloc_mem_err; 8403 8404 if (bnx2x_iov_alloc_mem(bp)) 8405 goto alloc_mem_err; 8406 8407 /* Slow path ring */ 8408 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); 8409 if (!bp->spq) 8410 goto alloc_mem_err; 8411 8412 /* EQ */ 8413 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, 8414 BCM_PAGE_SIZE * NUM_EQ_PAGES); 8415 if (!bp->eq_ring) 8416 goto alloc_mem_err; 8417 8418 return 0; 8419 8420alloc_mem_err: 8421 bnx2x_free_mem(bp); 8422 BNX2X_ERR("Can't allocate memory\n"); 8423 return -ENOMEM; 8424} 8425 8426/* 8427 * Init service functions 8428 */ 8429 8430int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac, 8431 struct bnx2x_vlan_mac_obj *obj, bool set, 8432 int mac_type, unsigned long *ramrod_flags) 8433{ 8434 int rc; 8435 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 8436 8437 memset(&ramrod_param, 0, sizeof(ramrod_param)); 8438 8439 /* Fill general parameters */ 8440 ramrod_param.vlan_mac_obj = obj; 8441 ramrod_param.ramrod_flags = *ramrod_flags; 8442 8443 /* Fill a user request section if needed */ 8444 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 8445 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 8446 8447 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 8448 8449 /* Set the command: ADD or DEL */ 8450 if (set) 8451 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 8452 else 8453 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 8454 } 8455 8456 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 8457 8458 if (rc == -EEXIST) { 8459 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 8460 /* do not treat adding same MAC as error */ 8461 rc = 0; 8462 } else if (rc < 0) 8463 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del")); 8464 8465 return rc; 8466} 8467 8468int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan, 8469 struct bnx2x_vlan_mac_obj *obj, bool set, 8470 unsigned long *ramrod_flags) 8471{ 8472 int rc; 8473 struct bnx2x_vlan_mac_ramrod_params ramrod_param; 8474 8475 memset(&ramrod_param, 0, sizeof(ramrod_param)); 8476 8477 /* Fill general parameters */ 8478 ramrod_param.vlan_mac_obj = obj; 8479 ramrod_param.ramrod_flags = *ramrod_flags; 8480 8481 /* Fill a user request section if needed */ 8482 if (!test_bit(RAMROD_CONT, ramrod_flags)) { 8483 ramrod_param.user_req.u.vlan.vlan = vlan; 8484 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags); 8485 /* Set the command: ADD or DEL */ 8486 if (set) 8487 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD; 8488 else 8489 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL; 8490 } 8491 8492 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); 8493 8494 if (rc == -EEXIST) { 8495 /* Do not treat adding same vlan as error. */ 8496 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc); 8497 rc = 0; 8498 } else if (rc < 0) { 8499 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del")); 8500 } 8501 8502 return rc; 8503} 8504 8505void bnx2x_clear_vlan_info(struct bnx2x *bp) 8506{ 8507 struct bnx2x_vlan_entry *vlan; 8508 8509 /* Mark that hw forgot all entries */ 8510 list_for_each_entry(vlan, &bp->vlan_reg, link) 8511 vlan->hw = false; 8512 8513 bp->vlan_cnt = 0; 8514} 8515 8516static int bnx2x_del_all_vlans(struct bnx2x *bp) 8517{ 8518 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj; 8519 unsigned long ramrod_flags = 0, vlan_flags = 0; 8520 int rc; 8521 8522 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8523 __set_bit(BNX2X_VLAN, &vlan_flags); 8524 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags); 8525 if (rc) 8526 return rc; 8527 8528 bnx2x_clear_vlan_info(bp); 8529 8530 return 0; 8531} 8532 8533int bnx2x_del_all_macs(struct bnx2x *bp, 8534 struct bnx2x_vlan_mac_obj *mac_obj, 8535 int mac_type, bool wait_for_comp) 8536{ 8537 int rc; 8538 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 8539 8540 /* Wait for completion of requested */ 8541 if (wait_for_comp) 8542 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8543 8544 /* Set the mac type of addresses we want to clear */ 8545 __set_bit(mac_type, &vlan_mac_flags); 8546 8547 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); 8548 if (rc < 0) 8549 BNX2X_ERR("Failed to delete MACs: %d\n", rc); 8550 8551 return rc; 8552} 8553 8554int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) 8555{ 8556 if (IS_PF(bp)) { 8557 unsigned long ramrod_flags = 0; 8558 8559 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n"); 8560 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 8561 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, 8562 &bp->sp_objs->mac_obj, set, 8563 BNX2X_ETH_MAC, &ramrod_flags); 8564 } else { /* vf */ 8565 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, 8566 bp->fp->index, set); 8567 } 8568} 8569 8570int bnx2x_setup_leading(struct bnx2x *bp) 8571{ 8572 if (IS_PF(bp)) 8573 return bnx2x_setup_queue(bp, &bp->fp[0], true); 8574 else /* VF */ 8575 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); 8576} 8577 8578/** 8579 * bnx2x_set_int_mode - configure interrupt mode 8580 * 8581 * @bp: driver handle 8582 * 8583 * In case of MSI-X it will also try to enable MSI-X. 8584 */ 8585int bnx2x_set_int_mode(struct bnx2x *bp) 8586{ 8587 int rc = 0; 8588 8589 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { 8590 BNX2X_ERR("VF not loaded since interrupt mode not msix\n"); 8591 return -EINVAL; 8592 } 8593 8594 switch (int_mode) { 8595 case BNX2X_INT_MODE_MSIX: 8596 /* attempt to enable msix */ 8597 rc = bnx2x_enable_msix(bp); 8598 8599 /* msix attained */ 8600 if (!rc) 8601 return 0; 8602 8603 /* vfs use only msix */ 8604 if (rc && IS_VF(bp)) 8605 return rc; 8606 8607 /* failed to enable multiple MSI-X */ 8608 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n", 8609 bp->num_queues, 8610 1 + bp->num_cnic_queues); 8611 8612 fallthrough; 8613 case BNX2X_INT_MODE_MSI: 8614 bnx2x_enable_msi(bp); 8615 8616 fallthrough; 8617 case BNX2X_INT_MODE_INTX: 8618 bp->num_ethernet_queues = 1; 8619 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; 8620 BNX2X_DEV_INFO("set number of queues to 1\n"); 8621 break; 8622 default: 8623 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n"); 8624 return -EINVAL; 8625 } 8626 return 0; 8627} 8628 8629/* must be called prior to any HW initializations */ 8630static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) 8631{ 8632 if (IS_SRIOV(bp)) 8633 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS; 8634 return L2_ILT_LINES(bp); 8635} 8636 8637void bnx2x_ilt_set_info(struct bnx2x *bp) 8638{ 8639 struct ilt_client_info *ilt_client; 8640 struct bnx2x_ilt *ilt = BP_ILT(bp); 8641 u16 line = 0; 8642 8643 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); 8644 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line); 8645 8646 /* CDU */ 8647 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 8648 ilt_client->client_num = ILT_CLIENT_CDU; 8649 ilt_client->page_size = CDU_ILT_PAGE_SZ; 8650 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 8651 ilt_client->start = line; 8652 line += bnx2x_cid_ilt_lines(bp); 8653 8654 if (CNIC_SUPPORT(bp)) 8655 line += CNIC_ILT_LINES; 8656 ilt_client->end = line - 1; 8657 8658 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8659 ilt_client->start, 8660 ilt_client->end, 8661 ilt_client->page_size, 8662 ilt_client->flags, 8663 ilog2(ilt_client->page_size >> 12)); 8664 8665 /* QM */ 8666 if (QM_INIT(bp->qm_cid_count)) { 8667 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 8668 ilt_client->client_num = ILT_CLIENT_QM; 8669 ilt_client->page_size = QM_ILT_PAGE_SZ; 8670 ilt_client->flags = 0; 8671 ilt_client->start = line; 8672 8673 /* 4 bytes for each cid */ 8674 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 8675 QM_ILT_PAGE_SZ); 8676 8677 ilt_client->end = line - 1; 8678 8679 DP(NETIF_MSG_IFUP, 8680 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8681 ilt_client->start, 8682 ilt_client->end, 8683 ilt_client->page_size, 8684 ilt_client->flags, 8685 ilog2(ilt_client->page_size >> 12)); 8686 } 8687 8688 if (CNIC_SUPPORT(bp)) { 8689 /* SRC */ 8690 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 8691 ilt_client->client_num = ILT_CLIENT_SRC; 8692 ilt_client->page_size = SRC_ILT_PAGE_SZ; 8693 ilt_client->flags = 0; 8694 ilt_client->start = line; 8695 line += SRC_ILT_LINES; 8696 ilt_client->end = line - 1; 8697 8698 DP(NETIF_MSG_IFUP, 8699 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8700 ilt_client->start, 8701 ilt_client->end, 8702 ilt_client->page_size, 8703 ilt_client->flags, 8704 ilog2(ilt_client->page_size >> 12)); 8705 8706 /* TM */ 8707 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 8708 ilt_client->client_num = ILT_CLIENT_TM; 8709 ilt_client->page_size = TM_ILT_PAGE_SZ; 8710 ilt_client->flags = 0; 8711 ilt_client->start = line; 8712 line += TM_ILT_LINES; 8713 ilt_client->end = line - 1; 8714 8715 DP(NETIF_MSG_IFUP, 8716 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n", 8717 ilt_client->start, 8718 ilt_client->end, 8719 ilt_client->page_size, 8720 ilt_client->flags, 8721 ilog2(ilt_client->page_size >> 12)); 8722 } 8723 8724 BUG_ON(line > ILT_MAX_LINES); 8725} 8726 8727/** 8728 * bnx2x_pf_q_prep_init - prepare INIT transition parameters 8729 * 8730 * @bp: driver handle 8731 * @fp: pointer to fastpath 8732 * @init_params: pointer to parameters structure 8733 * 8734 * parameters configured: 8735 * - HC configuration 8736 * - Queue's CDU context 8737 */ 8738static void bnx2x_pf_q_prep_init(struct bnx2x *bp, 8739 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params) 8740{ 8741 u8 cos; 8742 int cxt_index, cxt_offset; 8743 8744 /* FCoE Queue uses Default SB, thus has no HC capabilities */ 8745 if (!IS_FCOE_FP(fp)) { 8746 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags); 8747 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags); 8748 8749 /* If HC is supported, enable host coalescing in the transition 8750 * to INIT state. 8751 */ 8752 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags); 8753 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags); 8754 8755 /* HC rate */ 8756 init_params->rx.hc_rate = bp->rx_ticks ? 8757 (1000000 / bp->rx_ticks) : 0; 8758 init_params->tx.hc_rate = bp->tx_ticks ? 8759 (1000000 / bp->tx_ticks) : 0; 8760 8761 /* FW SB ID */ 8762 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = 8763 fp->fw_sb_id; 8764 8765 /* 8766 * CQ index among the SB indices: FCoE clients uses the default 8767 * SB, therefore it's different. 8768 */ 8769 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 8770 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 8771 } 8772 8773 /* set maximum number of COSs supported by this queue */ 8774 init_params->max_cos = fp->max_cos; 8775 8776 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n", 8777 fp->index, init_params->max_cos); 8778 8779 /* set the context pointers queue object */ 8780 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 8781 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS; 8782 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index * 8783 ILT_PAGE_CIDS); 8784 init_params->cxts[cos] = 8785 &bp->context[cxt_index].vcxt[cxt_offset].eth; 8786 } 8787} 8788 8789static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8790 struct bnx2x_queue_state_params *q_params, 8791 struct bnx2x_queue_setup_tx_only_params *tx_only_params, 8792 int tx_index, bool leading) 8793{ 8794 memset(tx_only_params, 0, sizeof(*tx_only_params)); 8795 8796 /* Set the command */ 8797 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 8798 8799 /* Set tx-only QUEUE flags: don't zero statistics */ 8800 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); 8801 8802 /* choose the index of the cid to send the slow path on */ 8803 tx_only_params->cid_index = tx_index; 8804 8805 /* Set general TX_ONLY_SETUP parameters */ 8806 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); 8807 8808 /* Set Tx TX_ONLY_SETUP parameters */ 8809 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 8810 8811 DP(NETIF_MSG_IFUP, 8812 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n", 8813 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 8814 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 8815 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 8816 8817 /* send the ramrod */ 8818 return bnx2x_queue_state_change(bp, q_params); 8819} 8820 8821/** 8822 * bnx2x_setup_queue - setup queue 8823 * 8824 * @bp: driver handle 8825 * @fp: pointer to fastpath 8826 * @leading: is leading 8827 * 8828 * This function performs 2 steps in a Queue state machine 8829 * actually: 1) RESET->INIT 2) INIT->SETUP 8830 */ 8831 8832int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 8833 bool leading) 8834{ 8835 struct bnx2x_queue_state_params q_params = {NULL}; 8836 struct bnx2x_queue_setup_params *setup_params = 8837 &q_params.params.setup; 8838 struct bnx2x_queue_setup_tx_only_params *tx_only_params = 8839 &q_params.params.tx_only; 8840 int rc; 8841 u8 tx_index; 8842 8843 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index); 8844 8845 /* reset IGU state skip FCoE L2 queue */ 8846 if (!IS_FCOE_FP(fp)) 8847 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, 8848 IGU_INT_ENABLE, 0); 8849 8850 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8851 /* We want to wait for completion in this context */ 8852 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8853 8854 /* Prepare the INIT parameters */ 8855 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); 8856 8857 /* Set the command */ 8858 q_params.cmd = BNX2X_Q_CMD_INIT; 8859 8860 /* Change the state to INIT */ 8861 rc = bnx2x_queue_state_change(bp, &q_params); 8862 if (rc) { 8863 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index); 8864 return rc; 8865 } 8866 8867 DP(NETIF_MSG_IFUP, "init complete\n"); 8868 8869 /* Now move the Queue to the SETUP state... */ 8870 memset(setup_params, 0, sizeof(*setup_params)); 8871 8872 /* Set QUEUE flags */ 8873 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); 8874 8875 /* Set general SETUP parameters */ 8876 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, 8877 FIRST_TX_COS_INDEX); 8878 8879 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, 8880 &setup_params->rxq_params); 8881 8882 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, 8883 FIRST_TX_COS_INDEX); 8884 8885 /* Set the command */ 8886 q_params.cmd = BNX2X_Q_CMD_SETUP; 8887 8888 if (IS_FCOE_FP(fp)) 8889 bp->fcoe_init = true; 8890 8891 /* Change the state to SETUP */ 8892 rc = bnx2x_queue_state_change(bp, &q_params); 8893 if (rc) { 8894 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index); 8895 return rc; 8896 } 8897 8898 /* loop through the relevant tx-only indices */ 8899 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8900 tx_index < fp->max_cos; 8901 tx_index++) { 8902 8903 /* prepare and send tx-only ramrod*/ 8904 rc = bnx2x_setup_tx_only(bp, fp, &q_params, 8905 tx_only_params, tx_index, leading); 8906 if (rc) { 8907 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n", 8908 fp->index, tx_index); 8909 return rc; 8910 } 8911 } 8912 8913 return rc; 8914} 8915 8916static int bnx2x_stop_queue(struct bnx2x *bp, int index) 8917{ 8918 struct bnx2x_fastpath *fp = &bp->fp[index]; 8919 struct bnx2x_fp_txdata *txdata; 8920 struct bnx2x_queue_state_params q_params = {NULL}; 8921 int rc, tx_index; 8922 8923 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid); 8924 8925 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 8926 /* We want to wait for completion in this context */ 8927 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 8928 8929 /* close tx-only connections */ 8930 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 8931 tx_index < fp->max_cos; 8932 tx_index++){ 8933 8934 /* ascertain this is a normal queue*/ 8935 txdata = fp->txdata_ptr[tx_index]; 8936 8937 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n", 8938 txdata->txq_index); 8939 8940 /* send halt terminate on tx-only connection */ 8941 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8942 memset(&q_params.params.terminate, 0, 8943 sizeof(q_params.params.terminate)); 8944 q_params.params.terminate.cid_index = tx_index; 8945 8946 rc = bnx2x_queue_state_change(bp, &q_params); 8947 if (rc) 8948 return rc; 8949 8950 /* send halt terminate on tx-only connection */ 8951 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8952 memset(&q_params.params.cfc_del, 0, 8953 sizeof(q_params.params.cfc_del)); 8954 q_params.params.cfc_del.cid_index = tx_index; 8955 rc = bnx2x_queue_state_change(bp, &q_params); 8956 if (rc) 8957 return rc; 8958 } 8959 /* Stop the primary connection: */ 8960 /* ...halt the connection */ 8961 q_params.cmd = BNX2X_Q_CMD_HALT; 8962 rc = bnx2x_queue_state_change(bp, &q_params); 8963 if (rc) 8964 return rc; 8965 8966 /* ...terminate the connection */ 8967 q_params.cmd = BNX2X_Q_CMD_TERMINATE; 8968 memset(&q_params.params.terminate, 0, 8969 sizeof(q_params.params.terminate)); 8970 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 8971 rc = bnx2x_queue_state_change(bp, &q_params); 8972 if (rc) 8973 return rc; 8974 /* ...delete cfc entry */ 8975 q_params.cmd = BNX2X_Q_CMD_CFC_DEL; 8976 memset(&q_params.params.cfc_del, 0, 8977 sizeof(q_params.params.cfc_del)); 8978 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 8979 return bnx2x_queue_state_change(bp, &q_params); 8980} 8981 8982static void bnx2x_reset_func(struct bnx2x *bp) 8983{ 8984 int port = BP_PORT(bp); 8985 int func = BP_FUNC(bp); 8986 int i; 8987 8988 /* Disable the function in the FW */ 8989 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 8990 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 8991 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 8992 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 8993 8994 /* FP SBs */ 8995 for_each_eth_queue(bp, i) { 8996 struct bnx2x_fastpath *fp = &bp->fp[i]; 8997 REG_WR8(bp, BAR_CSTRORM_INTMEM + 8998 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 8999 SB_DISABLED); 9000 } 9001 9002 if (CNIC_LOADED(bp)) 9003 /* CNIC SB */ 9004 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9005 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 9006 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); 9007 9008 /* SP SB */ 9009 REG_WR8(bp, BAR_CSTRORM_INTMEM + 9010 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 9011 SB_DISABLED); 9012 9013 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) 9014 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 9015 0); 9016 9017 /* Configure IGU */ 9018 if (bp->common.int_block == INT_BLOCK_HC) { 9019 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); 9020 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); 9021 } else { 9022 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); 9023 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); 9024 } 9025 9026 if (CNIC_LOADED(bp)) { 9027 /* Disable Timer scan */ 9028 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 9029 /* 9030 * Wait for at least 10ms and up to 2 second for the timers 9031 * scan to complete 9032 */ 9033 for (i = 0; i < 200; i++) { 9034 usleep_range(10000, 20000); 9035 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) 9036 break; 9037 } 9038 } 9039 /* Clear ILT */ 9040 bnx2x_clear_func_ilt(bp, func); 9041 9042 /* Timers workaround bug for E2: if this is vnic-3, 9043 * we need to set the entire ilt range for this timers. 9044 */ 9045 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { 9046 struct ilt_client_info ilt_cli; 9047 /* use dummy TM client */ 9048 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 9049 ilt_cli.start = 0; 9050 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 9051 ilt_cli.client_num = ILT_CLIENT_TM; 9052 9053 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); 9054 } 9055 9056 /* this assumes that reset_port() called before reset_func()*/ 9057 if (!CHIP_IS_E1x(bp)) 9058 bnx2x_pf_disable(bp); 9059 9060 bp->dmae_ready = 0; 9061} 9062 9063static void bnx2x_reset_port(struct bnx2x *bp) 9064{ 9065 int port = BP_PORT(bp); 9066 u32 val; 9067 9068 /* Reset physical Link */ 9069 bnx2x__link_reset(bp); 9070 9071 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 9072 9073 /* Do not rcv packets to BRB */ 9074 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 9075 /* Do not direct rcv packets that are not for MCP to the BRB */ 9076 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 9077 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 9078 9079 /* Configure AEU */ 9080 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 9081 9082 msleep(100); 9083 /* Check for BRB port occupancy */ 9084 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 9085 if (val) 9086 DP(NETIF_MSG_IFDOWN, 9087 "BRB1 is not empty %d blocks are occupied\n", val); 9088 9089 /* TODO: Close Doorbell port? */ 9090} 9091 9092static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) 9093{ 9094 struct bnx2x_func_state_params func_params = {NULL}; 9095 9096 /* Prepare parameters for function state transitions */ 9097 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 9098 9099 func_params.f_obj = &bp->func_obj; 9100 func_params.cmd = BNX2X_F_CMD_HW_RESET; 9101 9102 func_params.params.hw_init.load_phase = load_code; 9103 9104 return bnx2x_func_state_change(bp, &func_params); 9105} 9106 9107static int bnx2x_func_stop(struct bnx2x *bp) 9108{ 9109 struct bnx2x_func_state_params func_params = {NULL}; 9110 int rc; 9111 9112 /* Prepare parameters for function state transitions */ 9113 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 9114 func_params.f_obj = &bp->func_obj; 9115 func_params.cmd = BNX2X_F_CMD_STOP; 9116 9117 /* 9118 * Try to stop the function the 'good way'. If fails (in case 9119 * of a parity error during bnx2x_chip_cleanup()) and we are 9120 * not in a debug mode, perform a state transaction in order to 9121 * enable further HW_RESET transaction. 9122 */ 9123 rc = bnx2x_func_state_change(bp, &func_params); 9124 if (rc) { 9125#ifdef BNX2X_STOP_ON_ERROR 9126 return rc; 9127#else 9128 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n"); 9129 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 9130 return bnx2x_func_state_change(bp, &func_params); 9131#endif 9132 } 9133 9134 return 0; 9135} 9136 9137/** 9138 * bnx2x_send_unload_req - request unload mode from the MCP. 9139 * 9140 * @bp: driver handle 9141 * @unload_mode: requested function's unload mode 9142 * 9143 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 9144 */ 9145u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) 9146{ 9147 u32 reset_code = 0; 9148 int port = BP_PORT(bp); 9149 9150 /* Select the UNLOAD request mode */ 9151 if (unload_mode == UNLOAD_NORMAL) 9152 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9153 9154 else if (bp->flags & NO_WOL_FLAG) 9155 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 9156 9157 else if (bp->wol) { 9158 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 9159 const u8 *mac_addr = bp->dev->dev_addr; 9160 struct pci_dev *pdev = bp->pdev; 9161 u32 val; 9162 u16 pmc; 9163 9164 /* The mac address is written to entries 1-4 to 9165 * preserve entry 0 which is used by the PMF 9166 */ 9167 u8 entry = (BP_VN(bp) + 1)*8; 9168 9169 val = (mac_addr[0] << 8) | mac_addr[1]; 9170 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 9171 9172 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 9173 (mac_addr[4] << 8) | mac_addr[5]; 9174 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 9175 9176 /* Enable the PME and clear the status */ 9177 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc); 9178 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS; 9179 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); 9180 9181 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 9182 9183 } else 9184 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 9185 9186 /* Send the request to the MCP */ 9187 if (!BP_NOMCP(bp)) 9188 reset_code = bnx2x_fw_command(bp, reset_code, 0); 9189 else { 9190 int path = BP_PATH(bp); 9191 9192 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n", 9193 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], 9194 bnx2x_load_count[path][2]); 9195 bnx2x_load_count[path][0]--; 9196 bnx2x_load_count[path][1 + port]--; 9197 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n", 9198 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1], 9199 bnx2x_load_count[path][2]); 9200 if (bnx2x_load_count[path][0] == 0) 9201 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; 9202 else if (bnx2x_load_count[path][1 + port] == 0) 9203 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT; 9204 else 9205 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION; 9206 } 9207 9208 return reset_code; 9209} 9210 9211/** 9212 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 9213 * 9214 * @bp: driver handle 9215 * @keep_link: true iff link should be kept up 9216 */ 9217void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) 9218{ 9219 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 9220 9221 /* Report UNLOAD_DONE to MCP */ 9222 if (!BP_NOMCP(bp)) 9223 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 9224} 9225 9226static int bnx2x_func_wait_started(struct bnx2x *bp) 9227{ 9228 int tout = 50; 9229 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; 9230 9231 if (!bp->port.pmf) 9232 return 0; 9233 9234 /* 9235 * (assumption: No Attention from MCP at this stage) 9236 * PMF probably in the middle of TX disable/enable transaction 9237 * 1. Sync IRS for default SB 9238 * 2. Sync SP queue - this guarantees us that attention handling started 9239 * 3. Wait, that TX disable/enable transaction completes 9240 * 9241 * 1+2 guarantee that if DCBx attention was scheduled it already changed 9242 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 9243 * received completion for the transaction the state is TX_STOPPED. 9244 * State will return to STARTED after completion of TX_STOPPED-->STARTED 9245 * transaction. 9246 */ 9247 9248 /* make sure default SB ISR is done */ 9249 if (msix) 9250 synchronize_irq(bp->msix_table[0].vector); 9251 else 9252 synchronize_irq(bp->pdev->irq); 9253 9254 flush_workqueue(bnx2x_wq); 9255 flush_workqueue(bnx2x_iov_wq); 9256 9257 while (bnx2x_func_get_state(bp, &bp->func_obj) != 9258 BNX2X_F_STATE_STARTED && tout--) 9259 msleep(20); 9260 9261 if (bnx2x_func_get_state(bp, &bp->func_obj) != 9262 BNX2X_F_STATE_STARTED) { 9263#ifdef BNX2X_STOP_ON_ERROR 9264 BNX2X_ERR("Wrong function state\n"); 9265 return -EBUSY; 9266#else 9267 /* 9268 * Failed to complete the transaction in a "good way" 9269 * Force both transactions with CLR bit 9270 */ 9271 struct bnx2x_func_state_params func_params = {NULL}; 9272 9273 DP(NETIF_MSG_IFDOWN, 9274 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n"); 9275 9276 func_params.f_obj = &bp->func_obj; 9277 __set_bit(RAMROD_DRV_CLR_ONLY, 9278 &func_params.ramrod_flags); 9279 9280 /* STARTED-->TX_ST0PPED */ 9281 func_params.cmd = BNX2X_F_CMD_TX_STOP; 9282 bnx2x_func_state_change(bp, &func_params); 9283 9284 /* TX_ST0PPED-->STARTED */ 9285 func_params.cmd = BNX2X_F_CMD_TX_START; 9286 return bnx2x_func_state_change(bp, &func_params); 9287#endif 9288 } 9289 9290 return 0; 9291} 9292 9293static void bnx2x_disable_ptp(struct bnx2x *bp) 9294{ 9295 int port = BP_PORT(bp); 9296 9297 /* Disable sending PTP packets to host */ 9298 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 9299 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); 9300 9301 /* Reset PTP event detection rules */ 9302 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 9303 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); 9304 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 9305 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); 9306 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 9307 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); 9308 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 9309 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); 9310 9311 /* Disable the PTP feature */ 9312 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : 9313 NIG_REG_P0_PTP_EN, 0x0); 9314} 9315 9316/* Called during unload, to stop PTP-related stuff */ 9317static void bnx2x_stop_ptp(struct bnx2x *bp) 9318{ 9319 /* Cancel PTP work queue. Should be done after the Tx queues are 9320 * drained to prevent additional scheduling. 9321 */ 9322 cancel_work_sync(&bp->ptp_task); 9323 9324 if (bp->ptp_tx_skb) { 9325 dev_kfree_skb_any(bp->ptp_tx_skb); 9326 bp->ptp_tx_skb = NULL; 9327 } 9328 9329 /* Disable PTP in HW */ 9330 bnx2x_disable_ptp(bp); 9331 9332 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n"); 9333} 9334 9335void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) 9336{ 9337 int port = BP_PORT(bp); 9338 int i, rc = 0; 9339 u8 cos; 9340 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 9341 u32 reset_code; 9342 9343 /* Wait until tx fastpath tasks complete */ 9344 for_each_tx_queue(bp, i) { 9345 struct bnx2x_fastpath *fp = &bp->fp[i]; 9346 9347 for_each_cos_in_tx_queue(fp, cos) 9348 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); 9349#ifdef BNX2X_STOP_ON_ERROR 9350 if (rc) 9351 return; 9352#endif 9353 } 9354 9355 /* Give HW time to discard old tx messages */ 9356 usleep_range(1000, 2000); 9357 9358 /* Clean all ETH MACs */ 9359 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, 9360 false); 9361 if (rc < 0) 9362 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc); 9363 9364 /* Clean up UC list */ 9365 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, 9366 true); 9367 if (rc < 0) 9368 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n", 9369 rc); 9370 9371 /* The whole *vlan_obj structure may be not initialized if VLAN 9372 * filtering offload is not supported by hardware. Currently this is 9373 * true for all hardware covered by CHIP_IS_E1x(). 9374 */ 9375 if (!CHIP_IS_E1x(bp)) { 9376 /* Remove all currently configured VLANs */ 9377 rc = bnx2x_del_all_vlans(bp); 9378 if (rc < 0) 9379 BNX2X_ERR("Failed to delete all VLANs\n"); 9380 } 9381 9382 /* Disable LLH */ 9383 if (!CHIP_IS_E1(bp)) 9384 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); 9385 9386 /* Set "drop all" (stop Rx). 9387 * We need to take a netif_addr_lock() here in order to prevent 9388 * a race between the completion code and this code. 9389 */ 9390 netif_addr_lock_bh(bp->dev); 9391 /* Schedule the rx_mode command */ 9392 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 9393 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 9394 else if (bp->slowpath) 9395 bnx2x_set_storm_rx_mode(bp); 9396 9397 /* Cleanup multicast configuration */ 9398 rparam.mcast_obj = &bp->mcast_obj; 9399 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 9400 if (rc < 0) 9401 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc); 9402 9403 netif_addr_unlock_bh(bp->dev); 9404 9405 bnx2x_iov_chip_cleanup(bp); 9406 9407 /* 9408 * Send the UNLOAD_REQUEST to the MCP. This will return if 9409 * this function should perform FUNC, PORT or COMMON HW 9410 * reset. 9411 */ 9412 reset_code = bnx2x_send_unload_req(bp, unload_mode); 9413 9414 /* 9415 * (assumption: No Attention from MCP at this stage) 9416 * PMF probably in the middle of TX disable/enable transaction 9417 */ 9418 rc = bnx2x_func_wait_started(bp); 9419 if (rc) { 9420 BNX2X_ERR("bnx2x_func_wait_started failed\n"); 9421#ifdef BNX2X_STOP_ON_ERROR 9422 return; 9423#endif 9424 } 9425 9426 /* Close multi and leading connections 9427 * Completions for ramrods are collected in a synchronous way 9428 */ 9429 for_each_eth_queue(bp, i) 9430 if (bnx2x_stop_queue(bp, i)) 9431#ifdef BNX2X_STOP_ON_ERROR 9432 return; 9433#else 9434 goto unload_error; 9435#endif 9436 9437 if (CNIC_LOADED(bp)) { 9438 for_each_cnic_queue(bp, i) 9439 if (bnx2x_stop_queue(bp, i)) 9440#ifdef BNX2X_STOP_ON_ERROR 9441 return; 9442#else 9443 goto unload_error; 9444#endif 9445 } 9446 9447 /* If SP settings didn't get completed so far - something 9448 * very wrong has happen. 9449 */ 9450 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) 9451 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n"); 9452 9453#ifndef BNX2X_STOP_ON_ERROR 9454unload_error: 9455#endif 9456 rc = bnx2x_func_stop(bp); 9457 if (rc) { 9458 BNX2X_ERR("Function stop failed!\n"); 9459#ifdef BNX2X_STOP_ON_ERROR 9460 return; 9461#endif 9462 } 9463 9464 /* stop_ptp should be after the Tx queues are drained to prevent 9465 * scheduling to the cancelled PTP work queue. It should also be after 9466 * function stop ramrod is sent, since as part of this ramrod FW access 9467 * PTP registers. 9468 */ 9469 if (bp->flags & PTP_SUPPORTED) { 9470 bnx2x_stop_ptp(bp); 9471 if (bp->ptp_clock) { 9472 ptp_clock_unregister(bp->ptp_clock); 9473 bp->ptp_clock = NULL; 9474 } 9475 } 9476 9477 if (!bp->nic_stopped) { 9478 /* Disable HW interrupts, NAPI */ 9479 bnx2x_netif_stop(bp, 1); 9480 /* Delete all NAPI objects */ 9481 bnx2x_del_all_napi(bp); 9482 if (CNIC_LOADED(bp)) 9483 bnx2x_del_all_napi_cnic(bp); 9484 9485 /* Release IRQs */ 9486 bnx2x_free_irq(bp); 9487 bp->nic_stopped = true; 9488 } 9489 9490 /* Reset the chip, unless PCI function is offline. If we reach this 9491 * point following a PCI error handling, it means device is really 9492 * in a bad state and we're about to remove it, so reset the chip 9493 * is not a good idea. 9494 */ 9495 if (!pci_channel_offline(bp->pdev)) { 9496 rc = bnx2x_reset_hw(bp, reset_code); 9497 if (rc) 9498 BNX2X_ERR("HW_RESET failed\n"); 9499 } 9500 9501 /* Report UNLOAD_DONE to MCP */ 9502 bnx2x_send_unload_done(bp, keep_link); 9503} 9504 9505void bnx2x_disable_close_the_gate(struct bnx2x *bp) 9506{ 9507 u32 val; 9508 9509 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n"); 9510 9511 if (CHIP_IS_E1(bp)) { 9512 int port = BP_PORT(bp); 9513 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 9514 MISC_REG_AEU_MASK_ATTN_FUNC_0; 9515 9516 val = REG_RD(bp, addr); 9517 val &= ~(0x300); 9518 REG_WR(bp, addr, val); 9519 } else { 9520 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); 9521 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 9522 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 9523 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); 9524 } 9525} 9526 9527/* Close gates #2, #3 and #4: */ 9528static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 9529{ 9530 u32 val; 9531 9532 /* Gates #2 and #4a are closed/opened for "not E1" only */ 9533 if (!CHIP_IS_E1(bp)) { 9534 /* #4 */ 9535 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 9536 /* #2 */ 9537 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 9538 } 9539 9540 /* #3 */ 9541 if (CHIP_IS_E1x(bp)) { 9542 /* Prevent interrupts from HC on both ports */ 9543 val = REG_RD(bp, HC_REG_CONFIG_1); 9544 REG_WR(bp, HC_REG_CONFIG_1, 9545 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 9546 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 9547 9548 val = REG_RD(bp, HC_REG_CONFIG_0); 9549 REG_WR(bp, HC_REG_CONFIG_0, 9550 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 9551 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 9552 } else { 9553 /* Prevent incoming interrupts in IGU */ 9554 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 9555 9556 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, 9557 (!close) ? 9558 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 9559 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 9560 } 9561 9562 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n", 9563 close ? "closing" : "opening"); 9564} 9565 9566#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */ 9567 9568static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) 9569{ 9570 /* Do some magic... */ 9571 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 9572 *magic_val = val & SHARED_MF_CLP_MAGIC; 9573 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 9574} 9575 9576/** 9577 * bnx2x_clp_reset_done - restore the value of the `magic' bit. 9578 * 9579 * @bp: driver handle 9580 * @magic_val: old value of the `magic' bit. 9581 */ 9582static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) 9583{ 9584 /* Restore the `magic' bit value... */ 9585 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); 9586 MF_CFG_WR(bp, shared_mf_config.clp_mb, 9587 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 9588} 9589 9590/** 9591 * bnx2x_reset_mcp_prep - prepare for MCP reset. 9592 * 9593 * @bp: driver handle 9594 * @magic_val: old value of 'magic' bit. 9595 * 9596 * Takes care of CLP configurations. 9597 */ 9598static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) 9599{ 9600 u32 shmem; 9601 u32 validity_offset; 9602 9603 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n"); 9604 9605 /* Set `magic' bit in order to save MF config */ 9606 if (!CHIP_IS_E1(bp)) 9607 bnx2x_clp_reset_prep(bp, magic_val); 9608 9609 /* Get shmem offset */ 9610 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9611 validity_offset = 9612 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); 9613 9614 /* Clear validity map flags */ 9615 if (shmem > 0) 9616 REG_WR(bp, shmem + validity_offset, 0); 9617} 9618 9619#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 9620#define MCP_ONE_TIMEOUT 100 /* 100 ms */ 9621 9622/** 9623 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT 9624 * 9625 * @bp: driver handle 9626 */ 9627static void bnx2x_mcp_wait_one(struct bnx2x *bp) 9628{ 9629 /* special handling for emulation and FPGA, 9630 wait 10 times longer */ 9631 if (CHIP_REV_IS_SLOW(bp)) 9632 msleep(MCP_ONE_TIMEOUT*10); 9633 else 9634 msleep(MCP_ONE_TIMEOUT); 9635} 9636 9637/* 9638 * initializes bp->common.shmem_base and waits for validity signature to appear 9639 */ 9640static int bnx2x_init_shmem(struct bnx2x *bp) 9641{ 9642 int cnt = 0; 9643 u32 val = 0; 9644 9645 do { 9646 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 9647 9648 /* If we read all 0xFFs, means we are in PCI error state and 9649 * should bail out to avoid crashes on adapter's FW reads. 9650 */ 9651 if (bp->common.shmem_base == 0xFFFFFFFF) { 9652 bp->flags |= NO_MCP_FLAG; 9653 return -ENODEV; 9654 } 9655 9656 if (bp->common.shmem_base) { 9657 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); 9658 if (val & SHR_MEM_VALIDITY_MB) 9659 return 0; 9660 } 9661 9662 bnx2x_mcp_wait_one(bp); 9663 9664 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 9665 9666 BNX2X_ERR("BAD MCP validity signature\n"); 9667 9668 return -ENODEV; 9669} 9670 9671static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) 9672{ 9673 int rc = bnx2x_init_shmem(bp); 9674 9675 /* Restore the `magic' bit value */ 9676 if (!CHIP_IS_E1(bp)) 9677 bnx2x_clp_reset_done(bp, magic_val); 9678 9679 return rc; 9680} 9681 9682static void bnx2x_pxp_prep(struct bnx2x *bp) 9683{ 9684 if (!CHIP_IS_E1(bp)) { 9685 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 9686 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 9687 } 9688} 9689 9690/* 9691 * Reset the whole chip except for: 9692 * - PCIE core 9693 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by 9694 * one reset bit) 9695 * - IGU 9696 * - MISC (including AEU) 9697 * - GRC 9698 * - RBCN, RBCP 9699 */ 9700static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) 9701{ 9702 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 9703 u32 global_bits2, stay_reset2; 9704 9705 /* 9706 * Bits that have to be set in reset_mask2 if we want to reset 'global' 9707 * (per chip) blocks. 9708 */ 9709 global_bits2 = 9710 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 9711 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 9712 9713 /* Don't reset the following blocks. 9714 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 9715 * reset, as in 4 port device they might still be owned 9716 * by the MCP (there is only one leader per path). 9717 */ 9718 not_reset_mask1 = 9719 MISC_REGISTERS_RESET_REG_1_RST_HC | 9720 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 9721 MISC_REGISTERS_RESET_REG_1_RST_PXP; 9722 9723 not_reset_mask2 = 9724 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 9725 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 9726 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 9727 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 9728 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 9729 MISC_REGISTERS_RESET_REG_2_RST_GRC | 9730 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 9731 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 9732 MISC_REGISTERS_RESET_REG_2_RST_ATC | 9733 MISC_REGISTERS_RESET_REG_2_PGLC | 9734 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 9735 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 9736 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 9737 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 9738 MISC_REGISTERS_RESET_REG_2_UMAC0 | 9739 MISC_REGISTERS_RESET_REG_2_UMAC1; 9740 9741 /* 9742 * Keep the following blocks in reset: 9743 * - all xxMACs are handled by the bnx2x_link code. 9744 */ 9745 stay_reset2 = 9746 MISC_REGISTERS_RESET_REG_2_XMAC | 9747 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 9748 9749 /* Full reset masks according to the chip */ 9750 reset_mask1 = 0xffffffff; 9751 9752 if (CHIP_IS_E1(bp)) 9753 reset_mask2 = 0xffff; 9754 else if (CHIP_IS_E1H(bp)) 9755 reset_mask2 = 0x1ffff; 9756 else if (CHIP_IS_E2(bp)) 9757 reset_mask2 = 0xfffff; 9758 else /* CHIP_IS_E3 */ 9759 reset_mask2 = 0x3ffffff; 9760 9761 /* Don't reset global blocks unless we need to */ 9762 if (!global) 9763 reset_mask2 &= ~global_bits2; 9764 9765 /* 9766 * In case of attention in the QM, we need to reset PXP 9767 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 9768 * because otherwise QM reset would release 'close the gates' shortly 9769 * before resetting the PXP, then the PSWRQ would send a write 9770 * request to PGLUE. Then when PXP is reset, PGLUE would try to 9771 * read the payload data from PSWWR, but PSWWR would not 9772 * respond. The write queue in PGLUE would stuck, dmae commands 9773 * would not return. Therefore it's important to reset the second 9774 * reset register (containing the 9775 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 9776 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 9777 * bit). 9778 */ 9779 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 9780 reset_mask2 & (~not_reset_mask2)); 9781 9782 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 9783 reset_mask1 & (~not_reset_mask1)); 9784 9785 barrier(); 9786 9787 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 9788 reset_mask2 & (~stay_reset2)); 9789 9790 barrier(); 9791 9792 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 9793} 9794 9795/** 9796 * bnx2x_er_poll_igu_vq - poll for pending writes bit. 9797 * It should get cleared in no more than 1s. 9798 * 9799 * @bp: driver handle 9800 * 9801 * It should get cleared in no more than 1s. Returns 0 if 9802 * pending writes bit gets cleared. 9803 */ 9804static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) 9805{ 9806 u32 cnt = 1000; 9807 u32 pend_bits = 0; 9808 9809 do { 9810 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); 9811 9812 if (pend_bits == 0) 9813 break; 9814 9815 usleep_range(1000, 2000); 9816 } while (cnt-- > 0); 9817 9818 if (cnt <= 0) { 9819 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n", 9820 pend_bits); 9821 return -EBUSY; 9822 } 9823 9824 return 0; 9825} 9826 9827static int bnx2x_process_kill(struct bnx2x *bp, bool global) 9828{ 9829 int cnt = 1000; 9830 u32 val = 0; 9831 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 9832 u32 tags_63_32 = 0; 9833 9834 /* Empty the Tetris buffer, wait for 1s */ 9835 do { 9836 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); 9837 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); 9838 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); 9839 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); 9840 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); 9841 if (CHIP_IS_E3(bp)) 9842 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); 9843 9844 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 9845 ((port_is_idle_0 & 0x1) == 0x1) && 9846 ((port_is_idle_1 & 0x1) == 0x1) && 9847 (pgl_exp_rom2 == 0xffffffff) && 9848 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) 9849 break; 9850 usleep_range(1000, 2000); 9851 } while (cnt-- > 0); 9852 9853 if (cnt <= 0) { 9854 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n"); 9855 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 9856 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 9857 pgl_exp_rom2); 9858 return -EAGAIN; 9859 } 9860 9861 barrier(); 9862 9863 /* Close gates #2, #3 and #4 */ 9864 bnx2x_set_234_gates(bp, true); 9865 9866 /* Poll for IGU VQs for 57712 and newer chips */ 9867 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) 9868 return -EAGAIN; 9869 9870 /* TBD: Indicate that "process kill" is in progress to MCP */ 9871 9872 /* Clear "unprepared" bit */ 9873 REG_WR(bp, MISC_REG_UNPREPARED, 0); 9874 barrier(); 9875 9876 /* Wait for 1ms to empty GLUE and PCI-E core queues, 9877 * PSWHST, GRC and PSWRD Tetris buffer. 9878 */ 9879 usleep_range(1000, 2000); 9880 9881 /* Prepare to chip reset: */ 9882 /* MCP */ 9883 if (global) 9884 bnx2x_reset_mcp_prep(bp, &val); 9885 9886 /* PXP */ 9887 bnx2x_pxp_prep(bp); 9888 barrier(); 9889 9890 /* reset the chip */ 9891 bnx2x_process_kill_chip_reset(bp, global); 9892 barrier(); 9893 9894 /* clear errors in PGB */ 9895 if (!CHIP_IS_E1x(bp)) 9896 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); 9897 9898 /* Recover after reset: */ 9899 /* MCP */ 9900 if (global && bnx2x_reset_mcp_comp(bp, val)) 9901 return -EAGAIN; 9902 9903 /* TBD: Add resetting the NO_MCP mode DB here */ 9904 9905 /* Open the gates #2, #3 and #4 */ 9906 bnx2x_set_234_gates(bp, false); 9907 9908 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a 9909 * reset state, re-enable attentions. */ 9910 9911 return 0; 9912} 9913 9914static int bnx2x_leader_reset(struct bnx2x *bp) 9915{ 9916 int rc = 0; 9917 bool global = bnx2x_reset_is_global(bp); 9918 u32 load_code; 9919 9920 /* if not going to reset MCP - load "fake" driver to reset HW while 9921 * driver is owner of the HW 9922 */ 9923 if (!global && !BP_NOMCP(bp)) { 9924 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 9925 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 9926 if (!load_code) { 9927 BNX2X_ERR("MCP response failure, aborting\n"); 9928 rc = -EAGAIN; 9929 goto exit_leader_reset; 9930 } 9931 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 9932 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 9933 BNX2X_ERR("MCP unexpected resp, aborting\n"); 9934 rc = -EAGAIN; 9935 goto exit_leader_reset2; 9936 } 9937 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 9938 if (!load_code) { 9939 BNX2X_ERR("MCP response failure, aborting\n"); 9940 rc = -EAGAIN; 9941 goto exit_leader_reset2; 9942 } 9943 } 9944 9945 /* Try to recover after the failure */ 9946 if (bnx2x_process_kill(bp, global)) { 9947 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n", 9948 BP_PATH(bp)); 9949 rc = -EAGAIN; 9950 goto exit_leader_reset2; 9951 } 9952 9953 /* 9954 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver 9955 * state. 9956 */ 9957 bnx2x_set_reset_done(bp); 9958 if (global) 9959 bnx2x_clear_reset_global(bp); 9960 9961exit_leader_reset2: 9962 /* unload "fake driver" if it was loaded */ 9963 if (!global && !BP_NOMCP(bp)) { 9964 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 9965 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); 9966 } 9967exit_leader_reset: 9968 bp->is_leader = 0; 9969 bnx2x_release_leader_lock(bp); 9970 smp_mb(); 9971 return rc; 9972} 9973 9974static void bnx2x_recovery_failed(struct bnx2x *bp) 9975{ 9976 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); 9977 9978 /* Disconnect this device */ 9979 netif_device_detach(bp->dev); 9980 9981 /* 9982 * Block ifup for all function on this engine until "process kill" 9983 * or power cycle. 9984 */ 9985 bnx2x_set_reset_in_progress(bp); 9986 9987 /* Shut down the power */ 9988 bnx2x_set_power_state(bp, PCI_D3hot); 9989 9990 bp->recovery_state = BNX2X_RECOVERY_FAILED; 9991 9992 smp_mb(); 9993} 9994 9995/* 9996 * Assumption: runs under rtnl lock. This together with the fact 9997 * that it's called only from bnx2x_sp_rtnl() ensure that it 9998 * will never be called when netif_running(bp->dev) is false. 9999 */ 10000static void bnx2x_parity_recover(struct bnx2x *bp) 10001{ 10002 u32 error_recovered, error_unrecovered; 10003 bool is_parity, global = false; 10004#ifdef CONFIG_BNX2X_SRIOV 10005 int vf_idx; 10006 10007 for (vf_idx = 0; vf_idx < bp->requested_nr_virtfn; vf_idx++) { 10008 struct bnx2x_virtf *vf = BP_VF(bp, vf_idx); 10009 10010 if (vf) 10011 vf->state = VF_LOST; 10012 } 10013#endif 10014 DP(NETIF_MSG_HW, "Handling parity\n"); 10015 while (1) { 10016 switch (bp->recovery_state) { 10017 case BNX2X_RECOVERY_INIT: 10018 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 10019 is_parity = bnx2x_chk_parity_attn(bp, &global, false); 10020 WARN_ON(!is_parity); 10021 10022 /* Try to get a LEADER_LOCK HW lock */ 10023 if (bnx2x_trylock_leader_lock(bp)) { 10024 bnx2x_set_reset_in_progress(bp); 10025 /* 10026 * Check if there is a global attention and if 10027 * there was a global attention, set the global 10028 * reset bit. 10029 */ 10030 10031 if (global) 10032 bnx2x_set_reset_global(bp); 10033 10034 bp->is_leader = 1; 10035 } 10036 10037 /* Stop the driver */ 10038 /* If interface has been removed - break */ 10039 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) 10040 return; 10041 10042 bp->recovery_state = BNX2X_RECOVERY_WAIT; 10043 10044 /* Ensure "is_leader", MCP command sequence and 10045 * "recovery_state" update values are seen on other 10046 * CPUs. 10047 */ 10048 smp_mb(); 10049 break; 10050 10051 case BNX2X_RECOVERY_WAIT: 10052 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 10053 if (bp->is_leader) { 10054 int other_engine = BP_PATH(bp) ? 0 : 1; 10055 bool other_load_status = 10056 bnx2x_get_load_status(bp, other_engine); 10057 bool load_status = 10058 bnx2x_get_load_status(bp, BP_PATH(bp)); 10059 global = bnx2x_reset_is_global(bp); 10060 10061 /* 10062 * In case of a parity in a global block, let 10063 * the first leader that performs a 10064 * leader_reset() reset the global blocks in 10065 * order to clear global attentions. Otherwise 10066 * the gates will remain closed for that 10067 * engine. 10068 */ 10069 if (load_status || 10070 (global && other_load_status)) { 10071 /* Wait until all other functions get 10072 * down. 10073 */ 10074 schedule_delayed_work(&bp->sp_rtnl_task, 10075 HZ/10); 10076 return; 10077 } else { 10078 /* If all other functions got down - 10079 * try to bring the chip back to 10080 * normal. In any case it's an exit 10081 * point for a leader. 10082 */ 10083 if (bnx2x_leader_reset(bp)) { 10084 bnx2x_recovery_failed(bp); 10085 return; 10086 } 10087 10088 /* If we are here, means that the 10089 * leader has succeeded and doesn't 10090 * want to be a leader any more. Try 10091 * to continue as a none-leader. 10092 */ 10093 break; 10094 } 10095 } else { /* non-leader */ 10096 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { 10097 /* Try to get a LEADER_LOCK HW lock as 10098 * long as a former leader may have 10099 * been unloaded by the user or 10100 * released a leadership by another 10101 * reason. 10102 */ 10103 if (bnx2x_trylock_leader_lock(bp)) { 10104 /* I'm a leader now! Restart a 10105 * switch case. 10106 */ 10107 bp->is_leader = 1; 10108 break; 10109 } 10110 10111 schedule_delayed_work(&bp->sp_rtnl_task, 10112 HZ/10); 10113 return; 10114 10115 } else { 10116 /* 10117 * If there was a global attention, wait 10118 * for it to be cleared. 10119 */ 10120 if (bnx2x_reset_is_global(bp)) { 10121 schedule_delayed_work( 10122 &bp->sp_rtnl_task, 10123 HZ/10); 10124 return; 10125 } 10126 10127 error_recovered = 10128 bp->eth_stats.recoverable_error; 10129 error_unrecovered = 10130 bp->eth_stats.unrecoverable_error; 10131 bp->recovery_state = 10132 BNX2X_RECOVERY_NIC_LOADING; 10133 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 10134 error_unrecovered++; 10135 netdev_err(bp->dev, 10136 "Recovery failed. Power cycle needed\n"); 10137 /* Disconnect this device */ 10138 netif_device_detach(bp->dev); 10139 /* Shut down the power */ 10140 bnx2x_set_power_state( 10141 bp, PCI_D3hot); 10142 smp_mb(); 10143 } else { 10144 bp->recovery_state = 10145 BNX2X_RECOVERY_DONE; 10146 error_recovered++; 10147 smp_mb(); 10148 } 10149 bp->eth_stats.recoverable_error = 10150 error_recovered; 10151 bp->eth_stats.unrecoverable_error = 10152 error_unrecovered; 10153 10154 return; 10155 } 10156 } 10157 default: 10158 return; 10159 } 10160 } 10161} 10162 10163static int bnx2x_udp_port_update(struct bnx2x *bp) 10164{ 10165 struct bnx2x_func_switch_update_params *switch_update_params; 10166 struct bnx2x_func_state_params func_params = {NULL}; 10167 u16 vxlan_port = 0, geneve_port = 0; 10168 int rc; 10169 10170 switch_update_params = &func_params.params.switch_update; 10171 10172 /* Prepare parameters for function state transitions */ 10173 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 10174 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 10175 10176 func_params.f_obj = &bp->func_obj; 10177 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE; 10178 10179 /* Function parameters */ 10180 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG, 10181 &switch_update_params->changes); 10182 10183 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { 10184 geneve_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; 10185 switch_update_params->geneve_dst_port = geneve_port; 10186 } 10187 10188 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { 10189 vxlan_port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; 10190 switch_update_params->vxlan_dst_port = vxlan_port; 10191 } 10192 10193 /* Re-enable inner-rss for the offloaded UDP tunnels */ 10194 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS, 10195 &switch_update_params->changes); 10196 10197 rc = bnx2x_func_state_change(bp, &func_params); 10198 if (rc) 10199 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n", 10200 vxlan_port, geneve_port, rc); 10201 else 10202 DP(BNX2X_MSG_SP, 10203 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n", 10204 vxlan_port, geneve_port); 10205 10206 return rc; 10207} 10208 10209static int bnx2x_udp_tunnel_sync(struct net_device *netdev, unsigned int table) 10210{ 10211 struct bnx2x *bp = netdev_priv(netdev); 10212 struct udp_tunnel_info ti; 10213 10214 udp_tunnel_nic_get_port(netdev, table, 0, &ti); 10215 bp->udp_tunnel_ports[table] = be16_to_cpu(ti.port); 10216 10217 return bnx2x_udp_port_update(bp); 10218} 10219 10220static const struct udp_tunnel_nic_info bnx2x_udp_tunnels = { 10221 .sync_table = bnx2x_udp_tunnel_sync, 10222 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 10223 UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 10224 .tables = { 10225 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 10226 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 10227 }, 10228}; 10229 10230static int bnx2x_close(struct net_device *dev); 10231 10232/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is 10233 * scheduled on a general queue in order to prevent a dead lock. 10234 */ 10235static void bnx2x_sp_rtnl_task(struct work_struct *work) 10236{ 10237 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); 10238 10239 rtnl_lock(); 10240 10241 if (!netif_running(bp->dev)) { 10242 rtnl_unlock(); 10243 return; 10244 } 10245 10246 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { 10247#ifdef BNX2X_STOP_ON_ERROR 10248 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 10249 "you will need to reboot when done\n"); 10250 goto sp_rtnl_not_reset; 10251#endif 10252 /* 10253 * Clear all pending SP commands as we are going to reset the 10254 * function anyway. 10255 */ 10256 bp->sp_rtnl_state = 0; 10257 smp_mb(); 10258 10259 bnx2x_parity_recover(bp); 10260 10261 rtnl_unlock(); 10262 return; 10263 } 10264 10265 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { 10266#ifdef BNX2X_STOP_ON_ERROR 10267 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n" 10268 "you will need to reboot when done\n"); 10269 goto sp_rtnl_not_reset; 10270#endif 10271 10272 /* 10273 * Clear all pending SP commands as we are going to reset the 10274 * function anyway. 10275 */ 10276 bp->sp_rtnl_state = 0; 10277 smp_mb(); 10278 10279 /* Immediately indicate link as down */ 10280 bp->link_vars.link_up = 0; 10281 bp->force_link_down = true; 10282 netif_carrier_off(bp->dev); 10283 BNX2X_ERR("Indicating link is down due to Tx-timeout\n"); 10284 10285 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 10286 /* When ret value shows failure of allocation failure, 10287 * the nic is rebooted again. If open still fails, a error 10288 * message to notify the user. 10289 */ 10290 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) { 10291 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); 10292 if (bnx2x_nic_load(bp, LOAD_NORMAL)) 10293 BNX2X_ERR("Open the NIC fails again!\n"); 10294 } 10295 rtnl_unlock(); 10296 return; 10297 } 10298#ifdef BNX2X_STOP_ON_ERROR 10299sp_rtnl_not_reset: 10300#endif 10301 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) 10302 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); 10303 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) 10304 bnx2x_after_function_update(bp); 10305 /* 10306 * in case of fan failure we need to reset id if the "stop on error" 10307 * debug flag is set, since we trying to prevent permanent overheating 10308 * damage 10309 */ 10310 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 10311 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n"); 10312 netif_device_detach(bp->dev); 10313 bnx2x_close(bp->dev); 10314 rtnl_unlock(); 10315 return; 10316 } 10317 10318 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { 10319 DP(BNX2X_MSG_SP, 10320 "sending set mcast vf pf channel message from rtnl sp-task\n"); 10321 bnx2x_vfpf_set_mcast(bp->dev); 10322 } 10323 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 10324 &bp->sp_rtnl_state)){ 10325 if (netif_carrier_ok(bp->dev)) { 10326 bnx2x_tx_disable(bp); 10327 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n"); 10328 } 10329 } 10330 10331 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { 10332 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n"); 10333 bnx2x_set_rx_mode_inner(bp); 10334 } 10335 10336 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN, 10337 &bp->sp_rtnl_state)) 10338 bnx2x_pf_set_vfs_vlan(bp); 10339 10340 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { 10341 bnx2x_dcbx_stop_hw_tx(bp); 10342 bnx2x_dcbx_resume_hw_tx(bp); 10343 } 10344 10345 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION, 10346 &bp->sp_rtnl_state)) 10347 bnx2x_update_mng_version(bp); 10348 10349 if (test_and_clear_bit(BNX2X_SP_RTNL_UPDATE_SVID, &bp->sp_rtnl_state)) 10350 bnx2x_handle_update_svid_cmd(bp); 10351 10352 /* work which needs rtnl lock not-taken (as it takes the lock itself and 10353 * can be called from other contexts as well) 10354 */ 10355 rtnl_unlock(); 10356 10357 /* enable SR-IOV if applicable */ 10358 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, 10359 &bp->sp_rtnl_state)) { 10360 bnx2x_disable_sriov(bp); 10361 bnx2x_enable_sriov(bp); 10362 } 10363} 10364 10365static void bnx2x_period_task(struct work_struct *work) 10366{ 10367 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); 10368 10369 if (!netif_running(bp->dev)) 10370 goto period_task_exit; 10371 10372 if (CHIP_REV_IS_SLOW(bp)) { 10373 BNX2X_ERR("period task called on emulation, ignoring\n"); 10374 goto period_task_exit; 10375 } 10376 10377 bnx2x_acquire_phy_lock(bp); 10378 /* 10379 * The barrier is needed to ensure the ordering between the writing to 10380 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and 10381 * the reading here. 10382 */ 10383 smp_mb(); 10384 if (bp->port.pmf) { 10385 bnx2x_period_func(&bp->link_params, &bp->link_vars); 10386 10387 /* Re-queue task in 1 sec */ 10388 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); 10389 } 10390 10391 bnx2x_release_phy_lock(bp); 10392period_task_exit: 10393 return; 10394} 10395 10396/* 10397 * Init service functions 10398 */ 10399 10400static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) 10401{ 10402 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0; 10403 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base; 10404 return base + (BP_ABS_FUNC(bp)) * stride; 10405} 10406 10407static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, 10408 u8 port, u32 reset_reg, 10409 struct bnx2x_mac_vals *vals) 10410{ 10411 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 10412 u32 base_addr; 10413 10414 if (!(mask & reset_reg)) 10415 return false; 10416 10417 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port); 10418 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 10419 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG; 10420 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); 10421 REG_WR(bp, vals->umac_addr[port], 0); 10422 10423 return true; 10424} 10425 10426static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, 10427 struct bnx2x_mac_vals *vals) 10428{ 10429 u32 val, base_addr, offset, mask, reset_reg; 10430 bool mac_stopped = false; 10431 u8 port = BP_PORT(bp); 10432 10433 /* reset addresses as they also mark which values were changed */ 10434 memset(vals, 0, sizeof(*vals)); 10435 10436 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); 10437 10438 if (!CHIP_IS_E3(bp)) { 10439 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 10440 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 10441 if ((mask & reset_reg) && val) { 10442 u32 wb_data[2]; 10443 BNX2X_DEV_INFO("Disable bmac Rx\n"); 10444 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM 10445 : NIG_REG_INGRESS_BMAC0_MEM; 10446 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL 10447 : BIGMAC_REGISTER_BMAC_CONTROL; 10448 10449 /* 10450 * use rd/wr since we cannot use dmae. This is safe 10451 * since MCP won't access the bus due to the request 10452 * to unload, and no function on the path can be 10453 * loaded at this time. 10454 */ 10455 wb_data[0] = REG_RD(bp, base_addr + offset); 10456 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); 10457 vals->bmac_addr = base_addr + offset; 10458 vals->bmac_val[0] = wb_data[0]; 10459 vals->bmac_val[1] = wb_data[1]; 10460 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; 10461 REG_WR(bp, vals->bmac_addr, wb_data[0]); 10462 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); 10463 } 10464 BNX2X_DEV_INFO("Disable emac Rx\n"); 10465 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; 10466 vals->emac_val = REG_RD(bp, vals->emac_addr); 10467 REG_WR(bp, vals->emac_addr, 0); 10468 mac_stopped = true; 10469 } else { 10470 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 10471 BNX2X_DEV_INFO("Disable xmac Rx\n"); 10472 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 10473 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); 10474 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 10475 val & ~(1 << 1)); 10476 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, 10477 val | (1 << 1)); 10478 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 10479 vals->xmac_val = REG_RD(bp, vals->xmac_addr); 10480 REG_WR(bp, vals->xmac_addr, 0); 10481 mac_stopped = true; 10482 } 10483 10484 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, 10485 reset_reg, vals); 10486 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, 10487 reset_reg, vals); 10488 } 10489 10490 if (mac_stopped) 10491 msleep(20); 10492} 10493 10494#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 10495#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \ 10496 0x1848 + ((f) << 4)) 10497#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff) 10498#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 10499#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 10500 10501#define BCM_5710_UNDI_FW_MF_MAJOR (0x07) 10502#define BCM_5710_UNDI_FW_MF_MINOR (0x08) 10503#define BCM_5710_UNDI_FW_MF_VERS (0x05) 10504 10505static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) 10506{ 10507 /* UNDI marks its presence in DORQ - 10508 * it initializes CID offset for normal bell to 0x7 10509 */ 10510 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & 10511 MISC_REGISTERS_RESET_REG_1_RST_DORQ)) 10512 return false; 10513 10514 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { 10515 BNX2X_DEV_INFO("UNDI previously loaded\n"); 10516 return true; 10517 } 10518 10519 return false; 10520} 10521 10522static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) 10523{ 10524 u16 rcq, bd; 10525 u32 addr, tmp_reg; 10526 10527 if (BP_FUNC(bp) < 2) 10528 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); 10529 else 10530 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); 10531 10532 tmp_reg = REG_RD(bp, addr); 10533 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc; 10534 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc; 10535 10536 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd); 10537 REG_WR(bp, addr, tmp_reg); 10538 10539 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n", 10540 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); 10541} 10542 10543static int bnx2x_prev_mcp_done(struct bnx2x *bp) 10544{ 10545 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 10546 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 10547 if (!rc) { 10548 BNX2X_ERR("MCP response failure, aborting\n"); 10549 return -EBUSY; 10550 } 10551 10552 return 0; 10553} 10554 10555static struct bnx2x_prev_path_list * 10556 bnx2x_prev_path_get_entry(struct bnx2x *bp) 10557{ 10558 struct bnx2x_prev_path_list *tmp_list; 10559 10560 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) 10561 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && 10562 bp->pdev->bus->number == tmp_list->bus && 10563 BP_PATH(bp) == tmp_list->path) 10564 return tmp_list; 10565 10566 return NULL; 10567} 10568 10569static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) 10570{ 10571 struct bnx2x_prev_path_list *tmp_list; 10572 int rc; 10573 10574 rc = down_interruptible(&bnx2x_prev_sem); 10575 if (rc) { 10576 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10577 return rc; 10578 } 10579 10580 tmp_list = bnx2x_prev_path_get_entry(bp); 10581 if (tmp_list) { 10582 tmp_list->aer = 1; 10583 rc = 0; 10584 } else { 10585 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n", 10586 BP_PATH(bp)); 10587 } 10588 10589 up(&bnx2x_prev_sem); 10590 10591 return rc; 10592} 10593 10594static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) 10595{ 10596 struct bnx2x_prev_path_list *tmp_list; 10597 bool rc = false; 10598 10599 if (down_trylock(&bnx2x_prev_sem)) 10600 return false; 10601 10602 tmp_list = bnx2x_prev_path_get_entry(bp); 10603 if (tmp_list) { 10604 if (tmp_list->aer) { 10605 DP(NETIF_MSG_HW, "Path %d was marked by AER\n", 10606 BP_PATH(bp)); 10607 } else { 10608 rc = true; 10609 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n", 10610 BP_PATH(bp)); 10611 } 10612 } 10613 10614 up(&bnx2x_prev_sem); 10615 10616 return rc; 10617} 10618 10619bool bnx2x_port_after_undi(struct bnx2x *bp) 10620{ 10621 struct bnx2x_prev_path_list *entry; 10622 bool val; 10623 10624 down(&bnx2x_prev_sem); 10625 10626 entry = bnx2x_prev_path_get_entry(bp); 10627 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); 10628 10629 up(&bnx2x_prev_sem); 10630 10631 return val; 10632} 10633 10634static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) 10635{ 10636 struct bnx2x_prev_path_list *tmp_list; 10637 int rc; 10638 10639 rc = down_interruptible(&bnx2x_prev_sem); 10640 if (rc) { 10641 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10642 return rc; 10643 } 10644 10645 /* Check whether the entry for this path already exists */ 10646 tmp_list = bnx2x_prev_path_get_entry(bp); 10647 if (tmp_list) { 10648 if (!tmp_list->aer) { 10649 BNX2X_ERR("Re-Marking the path.\n"); 10650 } else { 10651 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n", 10652 BP_PATH(bp)); 10653 tmp_list->aer = 0; 10654 } 10655 up(&bnx2x_prev_sem); 10656 return 0; 10657 } 10658 up(&bnx2x_prev_sem); 10659 10660 /* Create an entry for this path and add it */ 10661 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL); 10662 if (!tmp_list) { 10663 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n"); 10664 return -ENOMEM; 10665 } 10666 10667 tmp_list->bus = bp->pdev->bus->number; 10668 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); 10669 tmp_list->path = BP_PATH(bp); 10670 tmp_list->aer = 0; 10671 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; 10672 10673 rc = down_interruptible(&bnx2x_prev_sem); 10674 if (rc) { 10675 BNX2X_ERR("Received %d when tried to take lock\n", rc); 10676 kfree(tmp_list); 10677 } else { 10678 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n", 10679 BP_PATH(bp)); 10680 list_add(&tmp_list->list, &bnx2x_prev_list); 10681 up(&bnx2x_prev_sem); 10682 } 10683 10684 return rc; 10685} 10686 10687static int bnx2x_do_flr(struct bnx2x *bp) 10688{ 10689 struct pci_dev *dev = bp->pdev; 10690 10691 if (CHIP_IS_E1x(bp)) { 10692 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n"); 10693 return -EINVAL; 10694 } 10695 10696 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 10697 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 10698 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n", 10699 bp->common.bc_ver); 10700 return -EINVAL; 10701 } 10702 10703 if (!pci_wait_for_pending_transaction(dev)) 10704 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); 10705 10706 BNX2X_DEV_INFO("Initiating FLR\n"); 10707 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); 10708 10709 return 0; 10710} 10711 10712static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) 10713{ 10714 int rc; 10715 10716 BNX2X_DEV_INFO("Uncommon unload Flow\n"); 10717 10718 /* Test if previous unload process was already finished for this path */ 10719 if (bnx2x_prev_is_path_marked(bp)) 10720 return bnx2x_prev_mcp_done(bp); 10721 10722 BNX2X_DEV_INFO("Path is unmarked\n"); 10723 10724 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */ 10725 if (bnx2x_prev_is_after_undi(bp)) 10726 goto out; 10727 10728 /* If function has FLR capabilities, and existing FW version matches 10729 * the one required, then FLR will be sufficient to clean any residue 10730 * left by previous driver 10731 */ 10732 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); 10733 10734 if (!rc) { 10735 /* fw version is good */ 10736 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n"); 10737 rc = bnx2x_do_flr(bp); 10738 } 10739 10740 if (!rc) { 10741 /* FLR was performed */ 10742 BNX2X_DEV_INFO("FLR successful\n"); 10743 return 0; 10744 } 10745 10746 BNX2X_DEV_INFO("Could not FLR\n"); 10747 10748out: 10749 /* Close the MCP request, return failure*/ 10750 rc = bnx2x_prev_mcp_done(bp); 10751 if (!rc) 10752 rc = BNX2X_PREV_WAIT_NEEDED; 10753 10754 return rc; 10755} 10756 10757static int bnx2x_prev_unload_common(struct bnx2x *bp) 10758{ 10759 u32 reset_reg, tmp_reg = 0, rc; 10760 bool prev_undi = false; 10761 struct bnx2x_mac_vals mac_vals; 10762 10763 /* It is possible a previous function received 'common' answer, 10764 * but hasn't loaded yet, therefore creating a scenario of 10765 * multiple functions receiving 'common' on the same path. 10766 */ 10767 BNX2X_DEV_INFO("Common unload Flow\n"); 10768 10769 memset(&mac_vals, 0, sizeof(mac_vals)); 10770 10771 if (bnx2x_prev_is_path_marked(bp)) 10772 return bnx2x_prev_mcp_done(bp); 10773 10774 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); 10775 10776 /* Reset should be performed after BRB is emptied */ 10777 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 10778 u32 timer_count = 1000; 10779 10780 /* Close the MAC Rx to prevent BRB from filling up */ 10781 bnx2x_prev_unload_close_mac(bp, &mac_vals); 10782 10783 /* close LLH filters for both ports towards the BRB */ 10784 bnx2x_set_rx_filter(&bp->link_params, 0); 10785 bp->link_params.port ^= 1; 10786 bnx2x_set_rx_filter(&bp->link_params, 0); 10787 bp->link_params.port ^= 1; 10788 10789 /* Check if the UNDI driver was previously loaded */ 10790 if (bnx2x_prev_is_after_undi(bp)) { 10791 prev_undi = true; 10792 /* clear the UNDI indication */ 10793 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 10794 /* clear possible idle check errors */ 10795 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); 10796 } 10797 if (!CHIP_IS_E1x(bp)) 10798 /* block FW from writing to host */ 10799 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 10800 10801 /* wait until BRB is empty */ 10802 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10803 while (timer_count) { 10804 u32 prev_brb = tmp_reg; 10805 10806 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); 10807 if (!tmp_reg) 10808 break; 10809 10810 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg); 10811 10812 /* reset timer as long as BRB actually gets emptied */ 10813 if (prev_brb > tmp_reg) 10814 timer_count = 1000; 10815 else 10816 timer_count--; 10817 10818 /* If UNDI resides in memory, manually increment it */ 10819 if (prev_undi) 10820 bnx2x_prev_unload_undi_inc(bp, 1); 10821 10822 udelay(10); 10823 } 10824 10825 if (!timer_count) 10826 BNX2X_ERR("Failed to empty BRB, hope for the best\n"); 10827 } 10828 10829 /* No packets are in the pipeline, path is ready for reset */ 10830 bnx2x_reset_common(bp); 10831 10832 if (mac_vals.xmac_addr) 10833 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); 10834 if (mac_vals.umac_addr[0]) 10835 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); 10836 if (mac_vals.umac_addr[1]) 10837 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); 10838 if (mac_vals.emac_addr) 10839 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); 10840 if (mac_vals.bmac_addr) { 10841 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 10842 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 10843 } 10844 10845 rc = bnx2x_prev_mark_path(bp, prev_undi); 10846 if (rc) { 10847 bnx2x_prev_mcp_done(bp); 10848 return rc; 10849 } 10850 10851 return bnx2x_prev_mcp_done(bp); 10852} 10853 10854static int bnx2x_prev_unload(struct bnx2x *bp) 10855{ 10856 int time_counter = 10; 10857 u32 rc, fw, hw_lock_reg, hw_lock_val; 10858 BNX2X_DEV_INFO("Entering Previous Unload Flow\n"); 10859 10860 /* clear hw from errors which may have resulted from an interrupted 10861 * dmae transaction. 10862 */ 10863 bnx2x_clean_pglue_errors(bp); 10864 10865 /* Release previously held locks */ 10866 hw_lock_reg = (BP_FUNC(bp) <= 5) ? 10867 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : 10868 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); 10869 10870 hw_lock_val = REG_RD(bp, hw_lock_reg); 10871 if (hw_lock_val) { 10872 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 10873 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n"); 10874 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, 10875 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); 10876 } 10877 10878 BNX2X_DEV_INFO("Release Previously held hw lock\n"); 10879 REG_WR(bp, hw_lock_reg, 0xffffffff); 10880 } else 10881 BNX2X_DEV_INFO("No need to release hw/nvram locks\n"); 10882 10883 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { 10884 BNX2X_DEV_INFO("Release previously held alr\n"); 10885 bnx2x_release_alr(bp); 10886 } 10887 10888 do { 10889 int aer = 0; 10890 /* Lock MCP using an unload request */ 10891 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 10892 if (!fw) { 10893 BNX2X_ERR("MCP response failure, aborting\n"); 10894 rc = -EBUSY; 10895 break; 10896 } 10897 10898 rc = down_interruptible(&bnx2x_prev_sem); 10899 if (rc) { 10900 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n", 10901 rc); 10902 } else { 10903 /* If Path is marked by EEH, ignore unload status */ 10904 aer = !!(bnx2x_prev_path_get_entry(bp) && 10905 bnx2x_prev_path_get_entry(bp)->aer); 10906 up(&bnx2x_prev_sem); 10907 } 10908 10909 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) { 10910 rc = bnx2x_prev_unload_common(bp); 10911 break; 10912 } 10913 10914 /* non-common reply from MCP might require looping */ 10915 rc = bnx2x_prev_unload_uncommon(bp); 10916 if (rc != BNX2X_PREV_WAIT_NEEDED) 10917 break; 10918 10919 msleep(20); 10920 } while (--time_counter); 10921 10922 if (!time_counter || rc) { 10923 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n"); 10924 rc = -EPROBE_DEFER; 10925 } 10926 10927 /* Mark function if its port was used to boot from SAN */ 10928 if (bnx2x_port_after_undi(bp)) 10929 bp->link_params.feature_config_flags |= 10930 FEATURE_CONFIG_BOOT_FROM_SAN; 10931 10932 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc); 10933 10934 return rc; 10935} 10936 10937static void bnx2x_get_common_hwinfo(struct bnx2x *bp) 10938{ 10939 u32 val, val2, val3, val4, id, boot_mode; 10940 u16 pmc; 10941 10942 /* Get the chip revision id and number. */ 10943 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 10944 val = REG_RD(bp, MISC_REG_CHIP_NUM); 10945 id = ((val & 0xffff) << 16); 10946 val = REG_RD(bp, MISC_REG_CHIP_REV); 10947 id |= ((val & 0xf) << 12); 10948 10949 /* Metal is read from PCI regs, but we can't access >=0x400 from 10950 * the configuration space (so we need to reg_rd) 10951 */ 10952 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); 10953 id |= (((val >> 24) & 0xf) << 4); 10954 val = REG_RD(bp, MISC_REG_BOND_ID); 10955 id |= (val & 0xf); 10956 bp->common.chip_id = id; 10957 10958 /* force 57811 according to MISC register */ 10959 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 10960 if (CHIP_IS_57810(bp)) 10961 bp->common.chip_id = (CHIP_NUM_57811 << 16) | 10962 (bp->common.chip_id & 0x0000FFFF); 10963 else if (CHIP_IS_57810_MF(bp)) 10964 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | 10965 (bp->common.chip_id & 0x0000FFFF); 10966 bp->common.chip_id |= 0x1; 10967 } 10968 10969 /* Set doorbell size */ 10970 bp->db_size = (1 << BNX2X_DB_SHIFT); 10971 10972 if (!CHIP_IS_E1x(bp)) { 10973 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); 10974 if ((val & 1) == 0) 10975 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); 10976 else 10977 val = (val >> 1) & 1; 10978 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" : 10979 "2_PORT_MODE"); 10980 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : 10981 CHIP_2_PORT_MODE; 10982 10983 if (CHIP_MODE_IS_4_PORT(bp)) 10984 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ 10985 else 10986 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ 10987 } else { 10988 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ 10989 bp->pfid = bp->pf_num; /* 0..7 */ 10990 } 10991 10992 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); 10993 10994 bp->link_params.chip_id = bp->common.chip_id; 10995 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 10996 10997 val = (REG_RD(bp, 0x2874) & 0x55); 10998 if ((bp->common.chip_id & 0x1) || 10999 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { 11000 bp->flags |= ONE_PORT_FLAG; 11001 BNX2X_DEV_INFO("single port device\n"); 11002 } 11003 11004 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); 11005 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << 11006 (val & MCPR_NVM_CFG4_FLASH_SIZE)); 11007 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n", 11008 bp->common.flash_size, bp->common.flash_size); 11009 11010 bnx2x_init_shmem(bp); 11011 11012 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? 11013 MISC_REG_GENERIC_CR_1 : 11014 MISC_REG_GENERIC_CR_0)); 11015 11016 bp->link_params.shmem_base = bp->common.shmem_base; 11017 bp->link_params.shmem2_base = bp->common.shmem2_base; 11018 if (SHMEM2_RD(bp, size) > 11019 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) 11020 bp->link_params.lfa_base = 11021 REG_RD(bp, bp->common.shmem2_base + 11022 (u32)offsetof(struct shmem2_region, 11023 lfa_host_addr[BP_PORT(bp)])); 11024 else 11025 bp->link_params.lfa_base = 0; 11026 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n", 11027 bp->common.shmem_base, bp->common.shmem2_base); 11028 11029 if (!bp->common.shmem_base) { 11030 BNX2X_DEV_INFO("MCP not active\n"); 11031 bp->flags |= NO_MCP_FLAG; 11032 return; 11033 } 11034 11035 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 11036 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); 11037 11038 bp->link_params.hw_led_mode = ((bp->common.hw_config & 11039 SHARED_HW_CFG_LED_MODE_MASK) >> 11040 SHARED_HW_CFG_LED_MODE_SHIFT); 11041 11042 bp->link_params.feature_config_flags = 0; 11043 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); 11044 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) 11045 bp->link_params.feature_config_flags |= 11046 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 11047 else 11048 bp->link_params.feature_config_flags &= 11049 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 11050 11051 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 11052 bp->common.bc_ver = val; 11053 BNX2X_DEV_INFO("bc_ver %X\n", val); 11054 if (val < BNX2X_BC_VER) { 11055 /* for now only warn 11056 * later we might need to enforce this */ 11057 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n", 11058 BNX2X_BC_VER, val); 11059 } 11060 bp->link_params.feature_config_flags |= 11061 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 11062 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0; 11063 11064 bp->link_params.feature_config_flags |= 11065 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ? 11066 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0; 11067 bp->link_params.feature_config_flags |= 11068 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ? 11069 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0; 11070 bp->link_params.feature_config_flags |= 11071 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ? 11072 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0; 11073 11074 bp->link_params.feature_config_flags |= 11075 (val >= REQ_BC_VER_4_MT_SUPPORTED) ? 11076 FEATURE_CONFIG_MT_SUPPORT : 0; 11077 11078 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? 11079 BC_SUPPORTS_PFC_STATS : 0; 11080 11081 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? 11082 BC_SUPPORTS_FCOE_FEATURES : 0; 11083 11084 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? 11085 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0; 11086 11087 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? 11088 BC_SUPPORTS_RMMOD_CMD : 0; 11089 11090 boot_mode = SHMEM_RD(bp, 11091 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & 11092 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK; 11093 switch (boot_mode) { 11094 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE: 11095 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; 11096 break; 11097 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB: 11098 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; 11099 break; 11100 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT: 11101 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; 11102 break; 11103 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE: 11104 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; 11105 break; 11106 } 11107 11108 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); 11109 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; 11110 11111 BNX2X_DEV_INFO("%sWoL capable\n", 11112 (bp->flags & NO_WOL_FLAG) ? "not " : ""); 11113 11114 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 11115 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); 11116 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); 11117 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); 11118 11119 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", 11120 val, val2, val3, val4); 11121} 11122 11123#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 11124#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 11125 11126static int bnx2x_get_igu_cam_info(struct bnx2x *bp) 11127{ 11128 int pfid = BP_FUNC(bp); 11129 int igu_sb_id; 11130 u32 val; 11131 u8 fid, igu_sb_cnt = 0; 11132 11133 bp->igu_base_sb = 0xff; 11134 if (CHIP_INT_MODE_IS_BC(bp)) { 11135 int vn = BP_VN(bp); 11136 igu_sb_cnt = bp->igu_sb_cnt; 11137 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 11138 FP_SB_MAX_E1x; 11139 11140 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + 11141 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); 11142 11143 return 0; 11144 } 11145 11146 /* IGU in normal mode - read CAM */ 11147 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 11148 igu_sb_id++) { 11149 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 11150 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) 11151 continue; 11152 fid = IGU_FID(val); 11153 if ((fid & IGU_FID_ENCODE_IS_PF)) { 11154 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) 11155 continue; 11156 if (IGU_VEC(val) == 0) 11157 /* default status block */ 11158 bp->igu_dsb_id = igu_sb_id; 11159 else { 11160 if (bp->igu_base_sb == 0xff) 11161 bp->igu_base_sb = igu_sb_id; 11162 igu_sb_cnt++; 11163 } 11164 } 11165 } 11166 11167#ifdef CONFIG_PCI_MSI 11168 /* Due to new PF resource allocation by MFW T7.4 and above, it's 11169 * optional that number of CAM entries will not be equal to the value 11170 * advertised in PCI. 11171 * Driver should use the minimal value of both as the actual status 11172 * block count 11173 */ 11174 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); 11175#endif 11176 11177 if (igu_sb_cnt == 0) { 11178 BNX2X_ERR("CAM configuration error\n"); 11179 return -EINVAL; 11180 } 11181 11182 return 0; 11183} 11184 11185static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) 11186{ 11187 int cfg_size = 0, idx, port = BP_PORT(bp); 11188 11189 /* Aggregation of supported attributes of all external phys */ 11190 bp->port.supported[0] = 0; 11191 bp->port.supported[1] = 0; 11192 switch (bp->link_params.num_phys) { 11193 case 1: 11194 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; 11195 cfg_size = 1; 11196 break; 11197 case 2: 11198 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; 11199 cfg_size = 1; 11200 break; 11201 case 3: 11202 if (bp->link_params.multi_phy_config & 11203 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 11204 bp->port.supported[1] = 11205 bp->link_params.phy[EXT_PHY1].supported; 11206 bp->port.supported[0] = 11207 bp->link_params.phy[EXT_PHY2].supported; 11208 } else { 11209 bp->port.supported[0] = 11210 bp->link_params.phy[EXT_PHY1].supported; 11211 bp->port.supported[1] = 11212 bp->link_params.phy[EXT_PHY2].supported; 11213 } 11214 cfg_size = 2; 11215 break; 11216 } 11217 11218 if (!(bp->port.supported[0] || bp->port.supported[1])) { 11219 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n", 11220 SHMEM_RD(bp, 11221 dev_info.port_hw_config[port].external_phy_config), 11222 SHMEM_RD(bp, 11223 dev_info.port_hw_config[port].external_phy_config2)); 11224 return; 11225 } 11226 11227 if (CHIP_IS_E3(bp)) 11228 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); 11229 else { 11230 switch (switch_cfg) { 11231 case SWITCH_CFG_1G: 11232 bp->port.phy_addr = REG_RD( 11233 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 11234 break; 11235 case SWITCH_CFG_10G: 11236 bp->port.phy_addr = REG_RD( 11237 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 11238 break; 11239 default: 11240 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n", 11241 bp->port.link_config[0]); 11242 return; 11243 } 11244 } 11245 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); 11246 /* mask what we support according to speed_cap_mask per configuration */ 11247 for (idx = 0; idx < cfg_size; idx++) { 11248 if (!(bp->link_params.speed_cap_mask[idx] & 11249 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 11250 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; 11251 11252 if (!(bp->link_params.speed_cap_mask[idx] & 11253 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 11254 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; 11255 11256 if (!(bp->link_params.speed_cap_mask[idx] & 11257 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 11258 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; 11259 11260 if (!(bp->link_params.speed_cap_mask[idx] & 11261 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 11262 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; 11263 11264 if (!(bp->link_params.speed_cap_mask[idx] & 11265 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 11266 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | 11267 SUPPORTED_1000baseT_Full); 11268 11269 if (!(bp->link_params.speed_cap_mask[idx] & 11270 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 11271 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; 11272 11273 if (!(bp->link_params.speed_cap_mask[idx] & 11274 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 11275 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; 11276 11277 if (!(bp->link_params.speed_cap_mask[idx] & 11278 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 11279 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; 11280 } 11281 11282 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], 11283 bp->port.supported[1]); 11284} 11285 11286static void bnx2x_link_settings_requested(struct bnx2x *bp) 11287{ 11288 u32 link_config, idx, cfg_size = 0; 11289 bp->port.advertising[0] = 0; 11290 bp->port.advertising[1] = 0; 11291 switch (bp->link_params.num_phys) { 11292 case 1: 11293 case 2: 11294 cfg_size = 1; 11295 break; 11296 case 3: 11297 cfg_size = 2; 11298 break; 11299 } 11300 for (idx = 0; idx < cfg_size; idx++) { 11301 bp->link_params.req_duplex[idx] = DUPLEX_FULL; 11302 link_config = bp->port.link_config[idx]; 11303 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 11304 case PORT_FEATURE_LINK_SPEED_AUTO: 11305 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { 11306 bp->link_params.req_line_speed[idx] = 11307 SPEED_AUTO_NEG; 11308 bp->port.advertising[idx] |= 11309 bp->port.supported[idx]; 11310 if (bp->link_params.phy[EXT_PHY1].type == 11311 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 11312 bp->port.advertising[idx] |= 11313 (SUPPORTED_100baseT_Half | 11314 SUPPORTED_100baseT_Full); 11315 } else { 11316 /* force 10G, no AN */ 11317 bp->link_params.req_line_speed[idx] = 11318 SPEED_10000; 11319 bp->port.advertising[idx] |= 11320 (ADVERTISED_10000baseT_Full | 11321 ADVERTISED_FIBRE); 11322 continue; 11323 } 11324 break; 11325 11326 case PORT_FEATURE_LINK_SPEED_10M_FULL: 11327 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { 11328 bp->link_params.req_line_speed[idx] = 11329 SPEED_10; 11330 bp->port.advertising[idx] |= 11331 (ADVERTISED_10baseT_Full | 11332 ADVERTISED_TP); 11333 } else { 11334 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11335 link_config, 11336 bp->link_params.speed_cap_mask[idx]); 11337 return; 11338 } 11339 break; 11340 11341 case PORT_FEATURE_LINK_SPEED_10M_HALF: 11342 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { 11343 bp->link_params.req_line_speed[idx] = 11344 SPEED_10; 11345 bp->link_params.req_duplex[idx] = 11346 DUPLEX_HALF; 11347 bp->port.advertising[idx] |= 11348 (ADVERTISED_10baseT_Half | 11349 ADVERTISED_TP); 11350 } else { 11351 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11352 link_config, 11353 bp->link_params.speed_cap_mask[idx]); 11354 return; 11355 } 11356 break; 11357 11358 case PORT_FEATURE_LINK_SPEED_100M_FULL: 11359 if (bp->port.supported[idx] & 11360 SUPPORTED_100baseT_Full) { 11361 bp->link_params.req_line_speed[idx] = 11362 SPEED_100; 11363 bp->port.advertising[idx] |= 11364 (ADVERTISED_100baseT_Full | 11365 ADVERTISED_TP); 11366 } else { 11367 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11368 link_config, 11369 bp->link_params.speed_cap_mask[idx]); 11370 return; 11371 } 11372 break; 11373 11374 case PORT_FEATURE_LINK_SPEED_100M_HALF: 11375 if (bp->port.supported[idx] & 11376 SUPPORTED_100baseT_Half) { 11377 bp->link_params.req_line_speed[idx] = 11378 SPEED_100; 11379 bp->link_params.req_duplex[idx] = 11380 DUPLEX_HALF; 11381 bp->port.advertising[idx] |= 11382 (ADVERTISED_100baseT_Half | 11383 ADVERTISED_TP); 11384 } else { 11385 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11386 link_config, 11387 bp->link_params.speed_cap_mask[idx]); 11388 return; 11389 } 11390 break; 11391 11392 case PORT_FEATURE_LINK_SPEED_1G: 11393 if (bp->port.supported[idx] & 11394 SUPPORTED_1000baseT_Full) { 11395 bp->link_params.req_line_speed[idx] = 11396 SPEED_1000; 11397 bp->port.advertising[idx] |= 11398 (ADVERTISED_1000baseT_Full | 11399 ADVERTISED_TP); 11400 } else if (bp->port.supported[idx] & 11401 SUPPORTED_1000baseKX_Full) { 11402 bp->link_params.req_line_speed[idx] = 11403 SPEED_1000; 11404 bp->port.advertising[idx] |= 11405 ADVERTISED_1000baseKX_Full; 11406 } else { 11407 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11408 link_config, 11409 bp->link_params.speed_cap_mask[idx]); 11410 return; 11411 } 11412 break; 11413 11414 case PORT_FEATURE_LINK_SPEED_2_5G: 11415 if (bp->port.supported[idx] & 11416 SUPPORTED_2500baseX_Full) { 11417 bp->link_params.req_line_speed[idx] = 11418 SPEED_2500; 11419 bp->port.advertising[idx] |= 11420 (ADVERTISED_2500baseX_Full | 11421 ADVERTISED_TP); 11422 } else { 11423 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11424 link_config, 11425 bp->link_params.speed_cap_mask[idx]); 11426 return; 11427 } 11428 break; 11429 11430 case PORT_FEATURE_LINK_SPEED_10G_CX4: 11431 if (bp->port.supported[idx] & 11432 SUPPORTED_10000baseT_Full) { 11433 bp->link_params.req_line_speed[idx] = 11434 SPEED_10000; 11435 bp->port.advertising[idx] |= 11436 (ADVERTISED_10000baseT_Full | 11437 ADVERTISED_FIBRE); 11438 } else if (bp->port.supported[idx] & 11439 SUPPORTED_10000baseKR_Full) { 11440 bp->link_params.req_line_speed[idx] = 11441 SPEED_10000; 11442 bp->port.advertising[idx] |= 11443 (ADVERTISED_10000baseKR_Full | 11444 ADVERTISED_FIBRE); 11445 } else { 11446 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", 11447 link_config, 11448 bp->link_params.speed_cap_mask[idx]); 11449 return; 11450 } 11451 break; 11452 case PORT_FEATURE_LINK_SPEED_20G: 11453 bp->link_params.req_line_speed[idx] = SPEED_20000; 11454 11455 break; 11456 default: 11457 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n", 11458 link_config); 11459 bp->link_params.req_line_speed[idx] = 11460 SPEED_AUTO_NEG; 11461 bp->port.advertising[idx] = 11462 bp->port.supported[idx]; 11463 break; 11464 } 11465 11466 bp->link_params.req_flow_ctrl[idx] = (link_config & 11467 PORT_FEATURE_FLOW_CONTROL_MASK); 11468 if (bp->link_params.req_flow_ctrl[idx] == 11469 BNX2X_FLOW_CTRL_AUTO) { 11470 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) 11471 bp->link_params.req_flow_ctrl[idx] = 11472 BNX2X_FLOW_CTRL_NONE; 11473 else 11474 bnx2x_set_requested_fc(bp); 11475 } 11476 11477 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n", 11478 bp->link_params.req_line_speed[idx], 11479 bp->link_params.req_duplex[idx], 11480 bp->link_params.req_flow_ctrl[idx], 11481 bp->port.advertising[idx]); 11482 } 11483} 11484 11485static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi) 11486{ 11487 __be16 mac_hi_be = cpu_to_be16(mac_hi); 11488 __be32 mac_lo_be = cpu_to_be32(mac_lo); 11489 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be)); 11490 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be)); 11491} 11492 11493static void bnx2x_get_port_hwinfo(struct bnx2x *bp) 11494{ 11495 int port = BP_PORT(bp); 11496 u32 config; 11497 u32 ext_phy_type, ext_phy_config, eee_mode; 11498 11499 bp->link_params.bp = bp; 11500 bp->link_params.port = port; 11501 11502 bp->link_params.lane_config = 11503 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 11504 11505 bp->link_params.speed_cap_mask[0] = 11506 SHMEM_RD(bp, 11507 dev_info.port_hw_config[port].speed_capability_mask) & 11508 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 11509 bp->link_params.speed_cap_mask[1] = 11510 SHMEM_RD(bp, 11511 dev_info.port_hw_config[port].speed_capability_mask2) & 11512 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK; 11513 bp->port.link_config[0] = 11514 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 11515 11516 bp->port.link_config[1] = 11517 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); 11518 11519 bp->link_params.multi_phy_config = 11520 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); 11521 /* If the device is capable of WoL, set the default state according 11522 * to the HW 11523 */ 11524 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 11525 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 11526 (config & PORT_FEATURE_WOL_ENABLED)); 11527 11528 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 11529 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) 11530 bp->flags |= NO_ISCSI_FLAG; 11531 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 11532 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) 11533 bp->flags |= NO_FCOE_FLAG; 11534 11535 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n", 11536 bp->link_params.lane_config, 11537 bp->link_params.speed_cap_mask[0], 11538 bp->port.link_config[0]); 11539 11540 bp->link_params.switch_cfg = (bp->port.link_config[0] & 11541 PORT_FEATURE_CONNECTED_SWITCH_MASK); 11542 bnx2x_phy_probe(&bp->link_params); 11543 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); 11544 11545 bnx2x_link_settings_requested(bp); 11546 11547 /* 11548 * If connected directly, work with the internal PHY, otherwise, work 11549 * with the external PHY 11550 */ 11551 ext_phy_config = 11552 SHMEM_RD(bp, 11553 dev_info.port_hw_config[port].external_phy_config); 11554 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config); 11555 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 11556 bp->mdio.prtad = bp->port.phy_addr; 11557 11558 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 11559 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 11560 bp->mdio.prtad = 11561 XGXS_EXT_PHY_ADDR(ext_phy_config); 11562 11563 /* Configure link feature according to nvram value */ 11564 eee_mode = (((SHMEM_RD(bp, dev_info. 11565 port_feature_config[port].eee_power_mode)) & 11566 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 11567 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 11568 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 11569 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | 11570 EEE_MODE_ENABLE_LPI | 11571 EEE_MODE_OUTPUT_TIME; 11572 } else { 11573 bp->link_params.eee_mode = 0; 11574 } 11575} 11576 11577void bnx2x_get_iscsi_info(struct bnx2x *bp) 11578{ 11579 u32 no_flags = NO_ISCSI_FLAG; 11580 int port = BP_PORT(bp); 11581 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 11582 drv_lic_key[port].max_iscsi_conn); 11583 11584 if (!CNIC_SUPPORT(bp)) { 11585 bp->flags |= no_flags; 11586 return; 11587 } 11588 11589 /* Get the number of maximum allowed iSCSI connections */ 11590 bp->cnic_eth_dev.max_iscsi_conn = 11591 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >> 11592 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT; 11593 11594 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n", 11595 bp->cnic_eth_dev.max_iscsi_conn); 11596 11597 /* 11598 * If maximum allowed number of connections is zero - 11599 * disable the feature. 11600 */ 11601 if (!bp->cnic_eth_dev.max_iscsi_conn) 11602 bp->flags |= no_flags; 11603} 11604 11605static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) 11606{ 11607 /* Port info */ 11608 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 11609 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); 11610 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 11611 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); 11612 11613 /* Node info */ 11614 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 11615 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); 11616 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 11617 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); 11618} 11619 11620static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) 11621{ 11622 u8 count = 0; 11623 11624 if (IS_MF(bp)) { 11625 u8 fid; 11626 11627 /* iterate over absolute function ids for this path: */ 11628 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { 11629 if (IS_MF_SD(bp)) { 11630 u32 cfg = MF_CFG_RD(bp, 11631 func_mf_config[fid].config); 11632 11633 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) && 11634 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) == 11635 FUNC_MF_CFG_PROTOCOL_FCOE)) 11636 count++; 11637 } else { 11638 u32 cfg = MF_CFG_RD(bp, 11639 func_ext_config[fid]. 11640 func_cfg); 11641 11642 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) && 11643 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)) 11644 count++; 11645 } 11646 } 11647 } else { /* SF */ 11648 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; 11649 11650 for (port = 0; port < port_cnt; port++) { 11651 u32 lic = SHMEM_RD(bp, 11652 drv_lic_key[port].max_fcoe_conn) ^ 11653 FW_ENCODE_32BIT_PATTERN; 11654 if (lic) 11655 count++; 11656 } 11657 } 11658 11659 return count; 11660} 11661 11662static void bnx2x_get_fcoe_info(struct bnx2x *bp) 11663{ 11664 int port = BP_PORT(bp); 11665 int func = BP_ABS_FUNC(bp); 11666 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, 11667 drv_lic_key[port].max_fcoe_conn); 11668 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); 11669 11670 if (!CNIC_SUPPORT(bp)) { 11671 bp->flags |= NO_FCOE_FLAG; 11672 return; 11673 } 11674 11675 /* Get the number of maximum allowed FCoE connections */ 11676 bp->cnic_eth_dev.max_fcoe_conn = 11677 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >> 11678 BNX2X_MAX_FCOE_INIT_CONN_SHIFT; 11679 11680 /* Calculate the number of maximum allowed FCoE tasks */ 11681 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; 11682 11683 /* check if FCoE resources must be shared between different functions */ 11684 if (num_fcoe_func) 11685 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; 11686 11687 /* Read the WWN: */ 11688 if (!IS_MF(bp)) { 11689 /* Port info */ 11690 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = 11691 SHMEM_RD(bp, 11692 dev_info.port_hw_config[port]. 11693 fcoe_wwn_port_name_upper); 11694 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = 11695 SHMEM_RD(bp, 11696 dev_info.port_hw_config[port]. 11697 fcoe_wwn_port_name_lower); 11698 11699 /* Node info */ 11700 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = 11701 SHMEM_RD(bp, 11702 dev_info.port_hw_config[port]. 11703 fcoe_wwn_node_name_upper); 11704 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = 11705 SHMEM_RD(bp, 11706 dev_info.port_hw_config[port]. 11707 fcoe_wwn_node_name_lower); 11708 } else if (!IS_MF_SD(bp)) { 11709 /* Read the WWN info only if the FCoE feature is enabled for 11710 * this function. 11711 */ 11712 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) 11713 bnx2x_get_ext_wwn_info(bp, func); 11714 } else { 11715 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) 11716 bnx2x_get_ext_wwn_info(bp, func); 11717 } 11718 11719 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); 11720 11721 /* 11722 * If maximum allowed number of connections is zero - 11723 * disable the feature. 11724 */ 11725 if (!bp->cnic_eth_dev.max_fcoe_conn) { 11726 bp->flags |= NO_FCOE_FLAG; 11727 eth_zero_addr(bp->fip_mac); 11728 } 11729} 11730 11731static void bnx2x_get_cnic_info(struct bnx2x *bp) 11732{ 11733 /* 11734 * iSCSI may be dynamically disabled but reading 11735 * info here we will decrease memory usage by driver 11736 * if the feature is disabled for good 11737 */ 11738 bnx2x_get_iscsi_info(bp); 11739 bnx2x_get_fcoe_info(bp); 11740} 11741 11742static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) 11743{ 11744 u32 val, val2; 11745 int func = BP_ABS_FUNC(bp); 11746 int port = BP_PORT(bp); 11747 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; 11748 u8 *fip_mac = bp->fip_mac; 11749 11750 if (IS_MF(bp)) { 11751 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or 11752 * FCoE MAC then the appropriate feature should be disabled. 11753 * In non SD mode features configuration comes from struct 11754 * func_ext_config. 11755 */ 11756 if (!IS_MF_SD(bp)) { 11757 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); 11758 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 11759 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11760 iscsi_mac_addr_upper); 11761 val = MF_CFG_RD(bp, func_ext_config[func]. 11762 iscsi_mac_addr_lower); 11763 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11764 BNX2X_DEV_INFO 11765 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11766 } else { 11767 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11768 } 11769 11770 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 11771 val2 = MF_CFG_RD(bp, func_ext_config[func]. 11772 fcoe_mac_addr_upper); 11773 val = MF_CFG_RD(bp, func_ext_config[func]. 11774 fcoe_mac_addr_lower); 11775 bnx2x_set_mac_buf(fip_mac, val, val2); 11776 BNX2X_DEV_INFO 11777 ("Read FCoE L2 MAC: %pM\n", fip_mac); 11778 } else { 11779 bp->flags |= NO_FCOE_FLAG; 11780 } 11781 11782 bp->mf_ext_config = cfg; 11783 11784 } else { /* SD MODE */ 11785 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { 11786 /* use primary mac as iscsi mac */ 11787 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); 11788 11789 BNX2X_DEV_INFO("SD ISCSI MODE\n"); 11790 BNX2X_DEV_INFO 11791 ("Read iSCSI MAC: %pM\n", iscsi_mac); 11792 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { 11793 /* use primary mac as fip mac */ 11794 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); 11795 BNX2X_DEV_INFO("SD FCoE MODE\n"); 11796 BNX2X_DEV_INFO 11797 ("Read FIP MAC: %pM\n", fip_mac); 11798 } 11799 } 11800 11801 /* If this is a storage-only interface, use SAN mac as 11802 * primary MAC. Notice that for SD this is already the case, 11803 * as the SAN mac was copied from the primary MAC. 11804 */ 11805 if (IS_MF_FCOE_AFEX(bp)) 11806 eth_hw_addr_set(bp->dev, fip_mac); 11807 } else { 11808 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11809 iscsi_mac_upper); 11810 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11811 iscsi_mac_lower); 11812 bnx2x_set_mac_buf(iscsi_mac, val, val2); 11813 11814 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11815 fcoe_fip_mac_upper); 11816 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. 11817 fcoe_fip_mac_lower); 11818 bnx2x_set_mac_buf(fip_mac, val, val2); 11819 } 11820 11821 /* Disable iSCSI OOO if MAC configuration is invalid. */ 11822 if (!is_valid_ether_addr(iscsi_mac)) { 11823 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; 11824 eth_zero_addr(iscsi_mac); 11825 } 11826 11827 /* Disable FCoE if MAC configuration is invalid. */ 11828 if (!is_valid_ether_addr(fip_mac)) { 11829 bp->flags |= NO_FCOE_FLAG; 11830 eth_zero_addr(bp->fip_mac); 11831 } 11832} 11833 11834static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) 11835{ 11836 u32 val, val2; 11837 int func = BP_ABS_FUNC(bp); 11838 int port = BP_PORT(bp); 11839 u8 addr[ETH_ALEN] = {}; 11840 11841 /* Zero primary MAC configuration */ 11842 eth_hw_addr_set(bp->dev, addr); 11843 11844 if (BP_NOMCP(bp)) { 11845 BNX2X_ERROR("warning: random MAC workaround active\n"); 11846 eth_hw_addr_random(bp->dev); 11847 } else if (IS_MF(bp)) { 11848 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11849 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); 11850 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) && 11851 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) { 11852 bnx2x_set_mac_buf(addr, val, val2); 11853 eth_hw_addr_set(bp->dev, addr); 11854 } 11855 11856 if (CNIC_SUPPORT(bp)) 11857 bnx2x_get_cnic_mac_hwinfo(bp); 11858 } else { 11859 /* in SF read MACs from port configuration */ 11860 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11861 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11862 bnx2x_set_mac_buf(addr, val, val2); 11863 eth_hw_addr_set(bp->dev, addr); 11864 11865 if (CNIC_SUPPORT(bp)) 11866 bnx2x_get_cnic_mac_hwinfo(bp); 11867 } 11868 11869 if (!BP_NOMCP(bp)) { 11870 /* Read physical port identifier from shmem */ 11871 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); 11872 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); 11873 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); 11874 bp->flags |= HAS_PHYS_PORT_ID; 11875 } 11876 11877 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); 11878 11879 if (!is_valid_ether_addr(bp->dev->dev_addr)) 11880 dev_err(&bp->pdev->dev, 11881 "bad Ethernet MAC address configuration: %pM\n" 11882 "change it manually before bringing up the appropriate network interface\n", 11883 bp->dev->dev_addr); 11884} 11885 11886static bool bnx2x_get_dropless_info(struct bnx2x *bp) 11887{ 11888 int tmp; 11889 u32 cfg; 11890 11891 if (IS_VF(bp)) 11892 return false; 11893 11894 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { 11895 /* Take function: tmp = func */ 11896 tmp = BP_ABS_FUNC(bp); 11897 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); 11898 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING); 11899 } else { 11900 /* Take port: tmp = port */ 11901 tmp = BP_PORT(bp); 11902 cfg = SHMEM_RD(bp, 11903 dev_info.port_hw_config[tmp].generic_features); 11904 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED); 11905 } 11906 return cfg; 11907} 11908 11909static void validate_set_si_mode(struct bnx2x *bp) 11910{ 11911 u8 func = BP_ABS_FUNC(bp); 11912 u32 val; 11913 11914 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); 11915 11916 /* check for legal mac (upper bytes) */ 11917 if (val != 0xffff) { 11918 bp->mf_mode = MULTI_FUNCTION_SI; 11919 bp->mf_config[BP_VN(bp)] = 11920 MF_CFG_RD(bp, func_mf_config[func].config); 11921 } else 11922 BNX2X_DEV_INFO("illegal MAC address for SI\n"); 11923} 11924 11925static int bnx2x_get_hwinfo(struct bnx2x *bp) 11926{ 11927 int /*abs*/func = BP_ABS_FUNC(bp); 11928 int vn; 11929 u32 val = 0, val2 = 0; 11930 int rc = 0; 11931 11932 /* Validate that chip access is feasible */ 11933 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { 11934 dev_err(&bp->pdev->dev, 11935 "Chip read returns all Fs. Preventing probe from continuing\n"); 11936 return -EINVAL; 11937 } 11938 11939 bnx2x_get_common_hwinfo(bp); 11940 11941 /* 11942 * initialize IGU parameters 11943 */ 11944 if (CHIP_IS_E1x(bp)) { 11945 bp->common.int_block = INT_BLOCK_HC; 11946 11947 bp->igu_dsb_id = DEF_SB_IGU_ID; 11948 bp->igu_base_sb = 0; 11949 } else { 11950 bp->common.int_block = INT_BLOCK_IGU; 11951 11952 /* do not allow device reset during IGU info processing */ 11953 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11954 11955 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); 11956 11957 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11958 int tout = 5000; 11959 11960 BNX2X_DEV_INFO("FORCING Normal Mode\n"); 11961 11962 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 11963 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); 11964 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); 11965 11966 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11967 tout--; 11968 usleep_range(1000, 2000); 11969 } 11970 11971 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { 11972 dev_err(&bp->pdev->dev, 11973 "FORCING Normal Mode failed!!!\n"); 11974 bnx2x_release_hw_lock(bp, 11975 HW_LOCK_RESOURCE_RESET); 11976 return -EPERM; 11977 } 11978 } 11979 11980 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 11981 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n"); 11982 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; 11983 } else 11984 BNX2X_DEV_INFO("IGU Normal Mode\n"); 11985 11986 rc = bnx2x_get_igu_cam_info(bp); 11987 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); 11988 if (rc) 11989 return rc; 11990 } 11991 11992 /* 11993 * set base FW non-default (fast path) status block id, this value is 11994 * used to initialize the fw_sb_id saved on the fp/queue structure to 11995 * determine the id used by the FW. 11996 */ 11997 if (CHIP_IS_E1x(bp)) 11998 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); 11999 else /* 12000 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of 12001 * the same queue are indicated on the same IGU SB). So we prefer 12002 * FW and IGU SBs to be the same value. 12003 */ 12004 bp->base_fw_ndsb = bp->igu_base_sb; 12005 12006 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n" 12007 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, 12008 bp->igu_sb_cnt, bp->base_fw_ndsb); 12009 12010 /* 12011 * Initialize MF configuration 12012 */ 12013 bp->mf_ov = 0; 12014 bp->mf_mode = 0; 12015 bp->mf_sub_mode = 0; 12016 vn = BP_VN(bp); 12017 12018 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 12019 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 12020 bp->common.shmem2_base, SHMEM2_RD(bp, size), 12021 (u32)offsetof(struct shmem2_region, mf_cfg_addr)); 12022 12023 if (SHMEM2_HAS(bp, mf_cfg_addr)) 12024 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); 12025 else 12026 bp->common.mf_cfg_base = bp->common.shmem_base + 12027 offsetof(struct shmem_region, func_mb) + 12028 E1H_FUNC_MAX * sizeof(struct drv_func_mb); 12029 /* 12030 * get mf configuration: 12031 * 1. Existence of MF configuration 12032 * 2. MAC address must be legal (check only upper bytes) 12033 * for Switch-Independent mode; 12034 * OVLAN must be legal for Switch-Dependent mode 12035 * 3. SF_MODE configures specific MF mode 12036 */ 12037 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 12038 /* get mf configuration */ 12039 val = SHMEM_RD(bp, 12040 dev_info.shared_feature_config.config); 12041 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK; 12042 12043 switch (val) { 12044 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 12045 validate_set_si_mode(bp); 12046 break; 12047 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 12048 if ((!CHIP_IS_E1x(bp)) && 12049 (MF_CFG_RD(bp, func_mf_config[func]. 12050 mac_upper) != 0xffff) && 12051 (SHMEM2_HAS(bp, 12052 afex_driver_support))) { 12053 bp->mf_mode = MULTI_FUNCTION_AFEX; 12054 bp->mf_config[vn] = MF_CFG_RD(bp, 12055 func_mf_config[func].config); 12056 } else { 12057 BNX2X_DEV_INFO("can not configure afex mode\n"); 12058 } 12059 break; 12060 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 12061 /* get OV configuration */ 12062 val = MF_CFG_RD(bp, 12063 func_mf_config[FUNC_0].e1hov_tag); 12064 val &= FUNC_MF_CFG_E1HOV_TAG_MASK; 12065 12066 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 12067 bp->mf_mode = MULTI_FUNCTION_SD; 12068 bp->mf_config[vn] = MF_CFG_RD(bp, 12069 func_mf_config[func].config); 12070 } else 12071 BNX2X_DEV_INFO("illegal OV for SD\n"); 12072 break; 12073 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE: 12074 bp->mf_mode = MULTI_FUNCTION_SD; 12075 bp->mf_sub_mode = SUB_MF_MODE_BD; 12076 bp->mf_config[vn] = 12077 MF_CFG_RD(bp, 12078 func_mf_config[func].config); 12079 12080 if (SHMEM2_HAS(bp, mtu_size)) { 12081 int mtu_idx = BP_FW_MB_IDX(bp); 12082 u16 mtu_size; 12083 u32 mtu; 12084 12085 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]); 12086 mtu_size = (u16)mtu; 12087 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n", 12088 mtu_size, mtu); 12089 12090 /* if valid: update device mtu */ 12091 if ((mtu_size >= ETH_MIN_PACKET_SIZE) && 12092 (mtu_size <= 12093 ETH_MAX_JUMBO_PACKET_SIZE)) 12094 bp->dev->mtu = mtu_size; 12095 } 12096 break; 12097 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE: 12098 bp->mf_mode = MULTI_FUNCTION_SD; 12099 bp->mf_sub_mode = SUB_MF_MODE_UFP; 12100 bp->mf_config[vn] = 12101 MF_CFG_RD(bp, 12102 func_mf_config[func].config); 12103 break; 12104 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 12105 bp->mf_config[vn] = 0; 12106 break; 12107 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE: 12108 val2 = SHMEM_RD(bp, 12109 dev_info.shared_hw_config.config_3); 12110 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK; 12111 switch (val2) { 12112 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5: 12113 validate_set_si_mode(bp); 12114 bp->mf_sub_mode = 12115 SUB_MF_MODE_NPAR1_DOT_5; 12116 break; 12117 default: 12118 /* Unknown configuration */ 12119 bp->mf_config[vn] = 0; 12120 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n", 12121 val); 12122 } 12123 break; 12124 default: 12125 /* Unknown configuration: reset mf_config */ 12126 bp->mf_config[vn] = 0; 12127 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val); 12128 } 12129 } 12130 12131 BNX2X_DEV_INFO("%s function mode\n", 12132 IS_MF(bp) ? "multi" : "single"); 12133 12134 switch (bp->mf_mode) { 12135 case MULTI_FUNCTION_SD: 12136 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & 12137 FUNC_MF_CFG_E1HOV_TAG_MASK; 12138 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 12139 bp->mf_ov = val; 12140 bp->path_has_ovlan = true; 12141 12142 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n", 12143 func, bp->mf_ov, bp->mf_ov); 12144 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) || 12145 (bp->mf_sub_mode == SUB_MF_MODE_BD)) { 12146 dev_err(&bp->pdev->dev, 12147 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n", 12148 func); 12149 bp->path_has_ovlan = true; 12150 } else { 12151 dev_err(&bp->pdev->dev, 12152 "No valid MF OV for func %d, aborting\n", 12153 func); 12154 return -EPERM; 12155 } 12156 break; 12157 case MULTI_FUNCTION_AFEX: 12158 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func); 12159 break; 12160 case MULTI_FUNCTION_SI: 12161 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n", 12162 func); 12163 break; 12164 default: 12165 if (vn) { 12166 dev_err(&bp->pdev->dev, 12167 "VN %d is in a single function mode, aborting\n", 12168 vn); 12169 return -EPERM; 12170 } 12171 break; 12172 } 12173 12174 /* check if other port on the path needs ovlan: 12175 * Since MF configuration is shared between ports 12176 * Possible mixed modes are only 12177 * {SF, SI} {SF, SD} {SD, SF} {SI, SF} 12178 */ 12179 if (CHIP_MODE_IS_4_PORT(bp) && 12180 !bp->path_has_ovlan && 12181 !IS_MF(bp) && 12182 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { 12183 u8 other_port = !BP_PORT(bp); 12184 u8 other_func = BP_PATH(bp) + 2*other_port; 12185 val = MF_CFG_RD(bp, 12186 func_mf_config[other_func].e1hov_tag); 12187 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) 12188 bp->path_has_ovlan = true; 12189 } 12190 } 12191 12192 /* adjust igu_sb_cnt to MF for E1H */ 12193 if (CHIP_IS_E1H(bp) && IS_MF(bp)) 12194 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); 12195 12196 /* port info */ 12197 bnx2x_get_port_hwinfo(bp); 12198 12199 /* Get MAC addresses */ 12200 bnx2x_get_mac_hwinfo(bp); 12201 12202 bnx2x_get_cnic_info(bp); 12203 12204 return rc; 12205} 12206 12207static void bnx2x_read_fwinfo(struct bnx2x *bp) 12208{ 12209 char str_id[VENDOR_ID_LEN + 1]; 12210 unsigned int vpd_len, kw_len; 12211 u8 *vpd_data; 12212 int rodi; 12213 12214 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); 12215 12216 vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len); 12217 if (IS_ERR(vpd_data)) 12218 return; 12219 12220 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, 12221 PCI_VPD_RO_KEYWORD_MFR_ID, &kw_len); 12222 if (rodi < 0 || kw_len != VENDOR_ID_LEN) 12223 goto out_not_found; 12224 12225 /* vendor specific info */ 12226 snprintf(str_id, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL); 12227 if (!strncasecmp(str_id, &vpd_data[rodi], VENDOR_ID_LEN)) { 12228 rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len, 12229 PCI_VPD_RO_KEYWORD_VENDOR0, 12230 &kw_len); 12231 if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) { 12232 memcpy(bp->fw_ver, &vpd_data[rodi], kw_len); 12233 bp->fw_ver[kw_len] = ' '; 12234 } 12235 } 12236out_not_found: 12237 kfree(vpd_data); 12238} 12239 12240static void bnx2x_set_modes_bitmap(struct bnx2x *bp) 12241{ 12242 u32 flags = 0; 12243 12244 if (CHIP_REV_IS_FPGA(bp)) 12245 SET_FLAGS(flags, MODE_FPGA); 12246 else if (CHIP_REV_IS_EMUL(bp)) 12247 SET_FLAGS(flags, MODE_EMUL); 12248 else 12249 SET_FLAGS(flags, MODE_ASIC); 12250 12251 if (CHIP_MODE_IS_4_PORT(bp)) 12252 SET_FLAGS(flags, MODE_PORT4); 12253 else 12254 SET_FLAGS(flags, MODE_PORT2); 12255 12256 if (CHIP_IS_E2(bp)) 12257 SET_FLAGS(flags, MODE_E2); 12258 else if (CHIP_IS_E3(bp)) { 12259 SET_FLAGS(flags, MODE_E3); 12260 if (CHIP_REV(bp) == CHIP_REV_Ax) 12261 SET_FLAGS(flags, MODE_E3_A0); 12262 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/ 12263 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 12264 } 12265 12266 if (IS_MF(bp)) { 12267 SET_FLAGS(flags, MODE_MF); 12268 switch (bp->mf_mode) { 12269 case MULTI_FUNCTION_SD: 12270 SET_FLAGS(flags, MODE_MF_SD); 12271 break; 12272 case MULTI_FUNCTION_SI: 12273 SET_FLAGS(flags, MODE_MF_SI); 12274 break; 12275 case MULTI_FUNCTION_AFEX: 12276 SET_FLAGS(flags, MODE_MF_AFEX); 12277 break; 12278 } 12279 } else 12280 SET_FLAGS(flags, MODE_SF); 12281 12282#if defined(__LITTLE_ENDIAN) 12283 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 12284#else /*(__BIG_ENDIAN)*/ 12285 SET_FLAGS(flags, MODE_BIG_ENDIAN); 12286#endif 12287 INIT_MODE_FLAGS(bp) = flags; 12288} 12289 12290static int bnx2x_init_bp(struct bnx2x *bp) 12291{ 12292 int func; 12293 int rc; 12294 12295 mutex_init(&bp->port.phy_mutex); 12296 mutex_init(&bp->fw_mb_mutex); 12297 mutex_init(&bp->drv_info_mutex); 12298 sema_init(&bp->stats_lock, 1); 12299 bp->drv_info_mng_owner = false; 12300 INIT_LIST_HEAD(&bp->vlan_reg); 12301 12302 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); 12303 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); 12304 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); 12305 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); 12306 if (IS_PF(bp)) { 12307 rc = bnx2x_get_hwinfo(bp); 12308 if (rc) 12309 return rc; 12310 } else { 12311 static const u8 zero_addr[ETH_ALEN] = {}; 12312 12313 eth_hw_addr_set(bp->dev, zero_addr); 12314 } 12315 12316 bnx2x_set_modes_bitmap(bp); 12317 12318 rc = bnx2x_alloc_mem_bp(bp); 12319 if (rc) 12320 return rc; 12321 12322 bnx2x_read_fwinfo(bp); 12323 12324 func = BP_FUNC(bp); 12325 12326 /* need to reset chip if undi was active */ 12327 if (IS_PF(bp) && !BP_NOMCP(bp)) { 12328 /* init fw_seq */ 12329 bp->fw_seq = 12330 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 12331 DRV_MSG_SEQ_NUMBER_MASK; 12332 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); 12333 12334 rc = bnx2x_prev_unload(bp); 12335 if (rc) { 12336 bnx2x_free_mem_bp(bp); 12337 return rc; 12338 } 12339 } 12340 12341 if (CHIP_REV_IS_FPGA(bp)) 12342 dev_err(&bp->pdev->dev, "FPGA detected\n"); 12343 12344 if (BP_NOMCP(bp) && (func == 0)) 12345 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); 12346 12347 bp->disable_tpa = disable_tpa; 12348 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); 12349 /* Reduce memory usage in kdump environment by disabling TPA */ 12350 bp->disable_tpa |= is_kdump_kernel(); 12351 12352 /* Set TPA flags */ 12353 if (bp->disable_tpa) { 12354 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 12355 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW); 12356 } 12357 12358 if (CHIP_IS_E1(bp)) 12359 bp->dropless_fc = false; 12360 else 12361 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); 12362 12363 bp->mrrs = mrrs; 12364 12365 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; 12366 if (IS_VF(bp)) 12367 bp->rx_ring_size = MAX_RX_AVAIL; 12368 12369 /* make sure that the numbers are in the right granularity */ 12370 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; 12371 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; 12372 12373 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; 12374 12375 timer_setup(&bp->timer, bnx2x_timer, 0); 12376 bp->timer.expires = jiffies + bp->current_interval; 12377 12378 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && 12379 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && 12380 SHMEM2_HAS(bp, dcbx_en) && 12381 SHMEM2_RD(bp, dcbx_lldp_params_offset) && 12382 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) && 12383 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) { 12384 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); 12385 bnx2x_dcbx_init_params(bp); 12386 } else { 12387 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); 12388 } 12389 12390 if (CHIP_IS_E1x(bp)) 12391 bp->cnic_base_cl_id = FP_SB_MAX_E1x; 12392 else 12393 bp->cnic_base_cl_id = FP_SB_MAX_E2; 12394 12395 /* multiple tx priority */ 12396 if (IS_VF(bp)) 12397 bp->max_cos = 1; 12398 else if (CHIP_IS_E1x(bp)) 12399 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; 12400 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) 12401 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; 12402 else if (CHIP_IS_E3B0(bp)) 12403 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; 12404 else 12405 BNX2X_ERR("unknown chip %x revision %x\n", 12406 CHIP_NUM(bp), CHIP_REV(bp)); 12407 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); 12408 12409 /* We need at least one default status block for slow-path events, 12410 * second status block for the L2 queue, and a third status block for 12411 * CNIC if supported. 12412 */ 12413 if (IS_VF(bp)) 12414 bp->min_msix_vec_cnt = 1; 12415 else if (CNIC_SUPPORT(bp)) 12416 bp->min_msix_vec_cnt = 3; 12417 else /* PF w/o cnic */ 12418 bp->min_msix_vec_cnt = 2; 12419 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); 12420 12421 bp->dump_preset_idx = 1; 12422 12423 return rc; 12424} 12425 12426/**************************************************************************** 12427* General service functions 12428****************************************************************************/ 12429 12430/* 12431 * net_device service functions 12432 */ 12433 12434/* called with rtnl_lock */ 12435static int bnx2x_open(struct net_device *dev) 12436{ 12437 struct bnx2x *bp = netdev_priv(dev); 12438 int rc; 12439 12440 bp->stats_init = true; 12441 12442 netif_carrier_off(dev); 12443 12444 bnx2x_set_power_state(bp, PCI_D0); 12445 12446 /* If parity had happen during the unload, then attentions 12447 * and/or RECOVERY_IN_PROGRES may still be set. In this case we 12448 * want the first function loaded on the current engine to 12449 * complete the recovery. 12450 * Parity recovery is only relevant for PF driver. 12451 */ 12452 if (IS_PF(bp)) { 12453 int other_engine = BP_PATH(bp) ? 0 : 1; 12454 bool other_load_status, load_status; 12455 bool global = false; 12456 12457 other_load_status = bnx2x_get_load_status(bp, other_engine); 12458 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); 12459 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || 12460 bnx2x_chk_parity_attn(bp, &global, true)) { 12461 do { 12462 /* If there are attentions and they are in a 12463 * global blocks, set the GLOBAL_RESET bit 12464 * regardless whether it will be this function 12465 * that will complete the recovery or not. 12466 */ 12467 if (global) 12468 bnx2x_set_reset_global(bp); 12469 12470 /* Only the first function on the current 12471 * engine should try to recover in open. In case 12472 * of attentions in global blocks only the first 12473 * in the chip should try to recover. 12474 */ 12475 if ((!load_status && 12476 (!global || !other_load_status)) && 12477 bnx2x_trylock_leader_lock(bp) && 12478 !bnx2x_leader_reset(bp)) { 12479 netdev_info(bp->dev, 12480 "Recovered in open\n"); 12481 break; 12482 } 12483 12484 /* recovery has failed... */ 12485 bnx2x_set_power_state(bp, PCI_D3hot); 12486 bp->recovery_state = BNX2X_RECOVERY_FAILED; 12487 12488 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n" 12489 "If you still see this message after a few retries then power cycle is required.\n"); 12490 12491 return -EAGAIN; 12492 } while (0); 12493 } 12494 } 12495 12496 bp->recovery_state = BNX2X_RECOVERY_DONE; 12497 rc = bnx2x_nic_load(bp, LOAD_OPEN); 12498 if (rc) 12499 return rc; 12500 12501 return 0; 12502} 12503 12504/* called with rtnl_lock */ 12505static int bnx2x_close(struct net_device *dev) 12506{ 12507 struct bnx2x *bp = netdev_priv(dev); 12508 12509 /* Unload the driver, release IRQs */ 12510 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); 12511 12512 return 0; 12513} 12514 12515struct bnx2x_mcast_list_elem_group 12516{ 12517 struct list_head mcast_group_link; 12518 struct bnx2x_mcast_list_elem mcast_elems[]; 12519}; 12520 12521#define MCAST_ELEMS_PER_PG \ 12522 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \ 12523 sizeof(struct bnx2x_mcast_list_elem)) 12524 12525static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list) 12526{ 12527 struct bnx2x_mcast_list_elem_group *current_mcast_group; 12528 12529 while (!list_empty(mcast_group_list)) { 12530 current_mcast_group = list_first_entry(mcast_group_list, 12531 struct bnx2x_mcast_list_elem_group, 12532 mcast_group_link); 12533 list_del(¤t_mcast_group->mcast_group_link); 12534 free_page((unsigned long)current_mcast_group); 12535 } 12536} 12537 12538static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, 12539 struct bnx2x_mcast_ramrod_params *p, 12540 struct list_head *mcast_group_list) 12541{ 12542 struct bnx2x_mcast_list_elem *mc_mac; 12543 struct netdev_hw_addr *ha; 12544 struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL; 12545 int mc_count = netdev_mc_count(bp->dev); 12546 int offset = 0; 12547 12548 INIT_LIST_HEAD(&p->mcast_list); 12549 netdev_for_each_mc_addr(ha, bp->dev) { 12550 if (!offset) { 12551 current_mcast_group = 12552 (struct bnx2x_mcast_list_elem_group *) 12553 __get_free_page(GFP_ATOMIC); 12554 if (!current_mcast_group) { 12555 bnx2x_free_mcast_macs_list(mcast_group_list); 12556 BNX2X_ERR("Failed to allocate mc MAC list\n"); 12557 return -ENOMEM; 12558 } 12559 list_add(¤t_mcast_group->mcast_group_link, 12560 mcast_group_list); 12561 } 12562 mc_mac = ¤t_mcast_group->mcast_elems[offset]; 12563 mc_mac->mac = bnx2x_mc_addr(ha); 12564 list_add_tail(&mc_mac->link, &p->mcast_list); 12565 offset++; 12566 if (offset == MCAST_ELEMS_PER_PG) 12567 offset = 0; 12568 } 12569 p->mcast_list_len = mc_count; 12570 return 0; 12571} 12572 12573/** 12574 * bnx2x_set_uc_list - configure a new unicast MACs list. 12575 * 12576 * @bp: driver handle 12577 * 12578 * We will use zero (0) as a MAC type for these MACs. 12579 */ 12580static int bnx2x_set_uc_list(struct bnx2x *bp) 12581{ 12582 int rc; 12583 struct net_device *dev = bp->dev; 12584 struct netdev_hw_addr *ha; 12585 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; 12586 unsigned long ramrod_flags = 0; 12587 12588 /* First schedule a cleanup up of old configuration */ 12589 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); 12590 if (rc < 0) { 12591 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc); 12592 return rc; 12593 } 12594 12595 netdev_for_each_uc_addr(ha, dev) { 12596 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, 12597 BNX2X_UC_LIST_MAC, &ramrod_flags); 12598 if (rc == -EEXIST) { 12599 DP(BNX2X_MSG_SP, 12600 "Failed to schedule ADD operations: %d\n", rc); 12601 /* do not treat adding same MAC as error */ 12602 rc = 0; 12603 12604 } else if (rc < 0) { 12605 12606 BNX2X_ERR("Failed to schedule ADD operations: %d\n", 12607 rc); 12608 return rc; 12609 } 12610 } 12611 12612 /* Execute the pending commands */ 12613 __set_bit(RAMROD_CONT, &ramrod_flags); 12614 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, 12615 BNX2X_UC_LIST_MAC, &ramrod_flags); 12616} 12617 12618static int bnx2x_set_mc_list_e1x(struct bnx2x *bp) 12619{ 12620 LIST_HEAD(mcast_group_list); 12621 struct net_device *dev = bp->dev; 12622 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 12623 int rc = 0; 12624 12625 rparam.mcast_obj = &bp->mcast_obj; 12626 12627 /* first, clear all configured multicast MACs */ 12628 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 12629 if (rc < 0) { 12630 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc); 12631 return rc; 12632 } 12633 12634 /* then, configure a new MACs list */ 12635 if (netdev_mc_count(dev)) { 12636 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); 12637 if (rc) 12638 return rc; 12639 12640 /* Now add the new MACs */ 12641 rc = bnx2x_config_mcast(bp, &rparam, 12642 BNX2X_MCAST_CMD_ADD); 12643 if (rc < 0) 12644 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 12645 rc); 12646 12647 bnx2x_free_mcast_macs_list(&mcast_group_list); 12648 } 12649 12650 return rc; 12651} 12652 12653static int bnx2x_set_mc_list(struct bnx2x *bp) 12654{ 12655 LIST_HEAD(mcast_group_list); 12656 struct bnx2x_mcast_ramrod_params rparam = {NULL}; 12657 struct net_device *dev = bp->dev; 12658 int rc = 0; 12659 12660 /* On older adapters, we need to flush and re-add filters */ 12661 if (CHIP_IS_E1x(bp)) 12662 return bnx2x_set_mc_list_e1x(bp); 12663 12664 rparam.mcast_obj = &bp->mcast_obj; 12665 12666 if (netdev_mc_count(dev)) { 12667 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list); 12668 if (rc) 12669 return rc; 12670 12671 /* Override the curently configured set of mc filters */ 12672 rc = bnx2x_config_mcast(bp, &rparam, 12673 BNX2X_MCAST_CMD_SET); 12674 if (rc < 0) 12675 BNX2X_ERR("Failed to set a new multicast configuration: %d\n", 12676 rc); 12677 12678 bnx2x_free_mcast_macs_list(&mcast_group_list); 12679 } else { 12680 /* If no mc addresses are required, flush the configuration */ 12681 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 12682 if (rc < 0) 12683 BNX2X_ERR("Failed to clear multicast configuration %d\n", 12684 rc); 12685 } 12686 12687 return rc; 12688} 12689 12690/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */ 12691static void bnx2x_set_rx_mode(struct net_device *dev) 12692{ 12693 struct bnx2x *bp = netdev_priv(dev); 12694 12695 if (bp->state != BNX2X_STATE_OPEN) { 12696 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); 12697 return; 12698 } else { 12699 /* Schedule an SP task to handle rest of change */ 12700 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, 12701 NETIF_MSG_IFUP); 12702 } 12703} 12704 12705void bnx2x_set_rx_mode_inner(struct bnx2x *bp) 12706{ 12707 u32 rx_mode = BNX2X_RX_MODE_NORMAL; 12708 12709 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); 12710 12711 netif_addr_lock_bh(bp->dev); 12712 12713 if (bp->dev->flags & IFF_PROMISC) { 12714 rx_mode = BNX2X_RX_MODE_PROMISC; 12715 } else if ((bp->dev->flags & IFF_ALLMULTI) || 12716 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && 12717 CHIP_IS_E1(bp))) { 12718 rx_mode = BNX2X_RX_MODE_ALLMULTI; 12719 } else { 12720 if (IS_PF(bp)) { 12721 /* some multicasts */ 12722 if (bnx2x_set_mc_list(bp) < 0) 12723 rx_mode = BNX2X_RX_MODE_ALLMULTI; 12724 12725 /* release bh lock, as bnx2x_set_uc_list might sleep */ 12726 netif_addr_unlock_bh(bp->dev); 12727 if (bnx2x_set_uc_list(bp) < 0) 12728 rx_mode = BNX2X_RX_MODE_PROMISC; 12729 netif_addr_lock_bh(bp->dev); 12730 } else { 12731 /* configuring mcast to a vf involves sleeping (when we 12732 * wait for the pf's response). 12733 */ 12734 bnx2x_schedule_sp_rtnl(bp, 12735 BNX2X_SP_RTNL_VFPF_MCAST, 0); 12736 } 12737 } 12738 12739 bp->rx_mode = rx_mode; 12740 /* handle ISCSI SD mode */ 12741 if (IS_MF_ISCSI_ONLY(bp)) 12742 bp->rx_mode = BNX2X_RX_MODE_NONE; 12743 12744 /* Schedule the rx_mode command */ 12745 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { 12746 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); 12747 netif_addr_unlock_bh(bp->dev); 12748 return; 12749 } 12750 12751 if (IS_PF(bp)) { 12752 bnx2x_set_storm_rx_mode(bp); 12753 netif_addr_unlock_bh(bp->dev); 12754 } else { 12755 /* VF will need to request the PF to make this change, and so 12756 * the VF needs to release the bottom-half lock prior to the 12757 * request (as it will likely require sleep on the VF side) 12758 */ 12759 netif_addr_unlock_bh(bp->dev); 12760 bnx2x_vfpf_storm_rx_mode(bp); 12761 } 12762} 12763 12764/* called with rtnl_lock */ 12765static int bnx2x_mdio_read(struct net_device *netdev, int prtad, 12766 int devad, u16 addr) 12767{ 12768 struct bnx2x *bp = netdev_priv(netdev); 12769 u16 value; 12770 int rc; 12771 12772 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n", 12773 prtad, devad, addr); 12774 12775 /* The HW expects different devad if CL22 is used */ 12776 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 12777 12778 bnx2x_acquire_phy_lock(bp); 12779 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); 12780 bnx2x_release_phy_lock(bp); 12781 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc); 12782 12783 if (!rc) 12784 rc = value; 12785 return rc; 12786} 12787 12788/* called with rtnl_lock */ 12789static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad, 12790 u16 addr, u16 value) 12791{ 12792 struct bnx2x *bp = netdev_priv(netdev); 12793 int rc; 12794 12795 DP(NETIF_MSG_LINK, 12796 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n", 12797 prtad, devad, addr, value); 12798 12799 /* The HW expects different devad if CL22 is used */ 12800 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 12801 12802 bnx2x_acquire_phy_lock(bp); 12803 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); 12804 bnx2x_release_phy_lock(bp); 12805 return rc; 12806} 12807 12808/* called with rtnl_lock */ 12809static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 12810{ 12811 struct bnx2x *bp = netdev_priv(dev); 12812 struct mii_ioctl_data *mdio = if_mii(ifr); 12813 12814 if (!netif_running(dev)) 12815 return -EAGAIN; 12816 12817 switch (cmd) { 12818 case SIOCSHWTSTAMP: 12819 return bnx2x_hwtstamp_ioctl(bp, ifr); 12820 default: 12821 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n", 12822 mdio->phy_id, mdio->reg_num, mdio->val_in); 12823 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); 12824 } 12825} 12826 12827static int bnx2x_validate_addr(struct net_device *dev) 12828{ 12829 struct bnx2x *bp = netdev_priv(dev); 12830 12831 /* query the bulletin board for mac address configured by the PF */ 12832 if (IS_VF(bp)) 12833 bnx2x_sample_bulletin(bp); 12834 12835 if (!is_valid_ether_addr(dev->dev_addr)) { 12836 BNX2X_ERR("Non-valid Ethernet address\n"); 12837 return -EADDRNOTAVAIL; 12838 } 12839 return 0; 12840} 12841 12842static int bnx2x_get_phys_port_id(struct net_device *netdev, 12843 struct netdev_phys_item_id *ppid) 12844{ 12845 struct bnx2x *bp = netdev_priv(netdev); 12846 12847 if (!(bp->flags & HAS_PHYS_PORT_ID)) 12848 return -EOPNOTSUPP; 12849 12850 ppid->id_len = sizeof(bp->phys_port_id); 12851 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); 12852 12853 return 0; 12854} 12855 12856static netdev_features_t bnx2x_features_check(struct sk_buff *skb, 12857 struct net_device *dev, 12858 netdev_features_t features) 12859{ 12860 /* 12861 * A skb with gso_size + header length > 9700 will cause a 12862 * firmware panic. Drop GSO support. 12863 * 12864 * Eventually the upper layer should not pass these packets down. 12865 * 12866 * For speed, if the gso_size is <= 9000, assume there will 12867 * not be 700 bytes of headers and pass it through. Only do a 12868 * full (slow) validation if the gso_size is > 9000. 12869 * 12870 * (Due to the way SKB_BY_FRAGS works this will also do a full 12871 * validation in that case.) 12872 */ 12873 if (unlikely(skb_is_gso(skb) && 12874 (skb_shinfo(skb)->gso_size > 9000) && 12875 !skb_gso_validate_mac_len(skb, 9700))) 12876 features &= ~NETIF_F_GSO_MASK; 12877 12878 features = vlan_features_check(skb, features); 12879 return vxlan_features_check(skb, features); 12880} 12881 12882static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add) 12883{ 12884 int rc; 12885 12886 if (IS_PF(bp)) { 12887 unsigned long ramrod_flags = 0; 12888 12889 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 12890 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj, 12891 add, &ramrod_flags); 12892 } else { 12893 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add); 12894 } 12895 12896 return rc; 12897} 12898 12899static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp) 12900{ 12901 struct bnx2x_vlan_entry *vlan; 12902 int rc = 0; 12903 12904 /* Configure all non-configured entries */ 12905 list_for_each_entry(vlan, &bp->vlan_reg, link) { 12906 if (vlan->hw) 12907 continue; 12908 12909 if (bp->vlan_cnt >= bp->vlan_credit) 12910 return -ENOBUFS; 12911 12912 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true); 12913 if (rc) { 12914 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid); 12915 return rc; 12916 } 12917 12918 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid); 12919 vlan->hw = true; 12920 bp->vlan_cnt++; 12921 } 12922 12923 return 0; 12924} 12925 12926static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode) 12927{ 12928 bool need_accept_any_vlan; 12929 12930 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp); 12931 12932 if (bp->accept_any_vlan != need_accept_any_vlan) { 12933 bp->accept_any_vlan = need_accept_any_vlan; 12934 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n", 12935 bp->accept_any_vlan ? "raised" : "cleared"); 12936 if (set_rx_mode) { 12937 if (IS_PF(bp)) 12938 bnx2x_set_rx_mode_inner(bp); 12939 else 12940 bnx2x_vfpf_storm_rx_mode(bp); 12941 } 12942 } 12943} 12944 12945int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp) 12946{ 12947 /* Don't set rx mode here. Our caller will do it. */ 12948 bnx2x_vlan_configure(bp, false); 12949 12950 return 0; 12951} 12952 12953static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 12954{ 12955 struct bnx2x *bp = netdev_priv(dev); 12956 struct bnx2x_vlan_entry *vlan; 12957 12958 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid); 12959 12960 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL); 12961 if (!vlan) 12962 return -ENOMEM; 12963 12964 vlan->vid = vid; 12965 vlan->hw = false; 12966 list_add_tail(&vlan->link, &bp->vlan_reg); 12967 12968 if (netif_running(dev)) 12969 bnx2x_vlan_configure(bp, true); 12970 12971 return 0; 12972} 12973 12974static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 12975{ 12976 struct bnx2x *bp = netdev_priv(dev); 12977 struct bnx2x_vlan_entry *vlan; 12978 bool found = false; 12979 int rc = 0; 12980 12981 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid); 12982 12983 list_for_each_entry(vlan, &bp->vlan_reg, link) 12984 if (vlan->vid == vid) { 12985 found = true; 12986 break; 12987 } 12988 12989 if (!found) { 12990 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid); 12991 return -EINVAL; 12992 } 12993 12994 if (netif_running(dev) && vlan->hw) { 12995 rc = __bnx2x_vlan_configure_vid(bp, vid, false); 12996 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid); 12997 bp->vlan_cnt--; 12998 } 12999 13000 list_del(&vlan->link); 13001 kfree(vlan); 13002 13003 if (netif_running(dev)) 13004 bnx2x_vlan_configure(bp, true); 13005 13006 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc); 13007 13008 return rc; 13009} 13010 13011static const struct net_device_ops bnx2x_netdev_ops = { 13012 .ndo_open = bnx2x_open, 13013 .ndo_stop = bnx2x_close, 13014 .ndo_start_xmit = bnx2x_start_xmit, 13015 .ndo_select_queue = bnx2x_select_queue, 13016 .ndo_set_rx_mode = bnx2x_set_rx_mode, 13017 .ndo_set_mac_address = bnx2x_change_mac_addr, 13018 .ndo_validate_addr = bnx2x_validate_addr, 13019 .ndo_eth_ioctl = bnx2x_ioctl, 13020 .ndo_change_mtu = bnx2x_change_mtu, 13021 .ndo_fix_features = bnx2x_fix_features, 13022 .ndo_set_features = bnx2x_set_features, 13023 .ndo_tx_timeout = bnx2x_tx_timeout, 13024 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid, 13025 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid, 13026 .ndo_setup_tc = __bnx2x_setup_tc, 13027#ifdef CONFIG_BNX2X_SRIOV 13028 .ndo_set_vf_mac = bnx2x_set_vf_mac, 13029 .ndo_set_vf_vlan = bnx2x_set_vf_vlan, 13030 .ndo_get_vf_config = bnx2x_get_vf_config, 13031 .ndo_set_vf_spoofchk = bnx2x_set_vf_spoofchk, 13032#endif 13033#ifdef NETDEV_FCOE_WWNN 13034 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn, 13035#endif 13036 13037 .ndo_get_phys_port_id = bnx2x_get_phys_port_id, 13038 .ndo_set_vf_link_state = bnx2x_set_vf_link_state, 13039 .ndo_features_check = bnx2x_features_check, 13040}; 13041 13042static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, 13043 struct net_device *dev, unsigned long board_type) 13044{ 13045 int rc; 13046 u32 pci_cfg_dword; 13047 bool chip_is_e1x = (board_type == BCM57710 || 13048 board_type == BCM57711 || 13049 board_type == BCM57711E); 13050 13051 SET_NETDEV_DEV(dev, &pdev->dev); 13052 13053 bp->dev = dev; 13054 bp->pdev = pdev; 13055 13056 rc = pci_enable_device(pdev); 13057 if (rc) { 13058 dev_err(&bp->pdev->dev, 13059 "Cannot enable PCI device, aborting\n"); 13060 goto err_out; 13061 } 13062 13063 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 13064 dev_err(&bp->pdev->dev, 13065 "Cannot find PCI device base address, aborting\n"); 13066 rc = -ENODEV; 13067 goto err_out_disable; 13068 } 13069 13070 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 13071 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); 13072 rc = -ENODEV; 13073 goto err_out_disable; 13074 } 13075 13076 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword); 13077 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) == 13078 PCICFG_REVESION_ID_ERROR_VAL) { 13079 pr_err("PCI device error, probably due to fan failure, aborting\n"); 13080 rc = -ENODEV; 13081 goto err_out_disable; 13082 } 13083 13084 if (atomic_read(&pdev->enable_cnt) == 1) { 13085 rc = pci_request_regions(pdev, DRV_MODULE_NAME); 13086 if (rc) { 13087 dev_err(&bp->pdev->dev, 13088 "Cannot obtain PCI resources, aborting\n"); 13089 goto err_out_disable; 13090 } 13091 13092 pci_set_master(pdev); 13093 pci_save_state(pdev); 13094 } 13095 13096 if (IS_PF(bp)) { 13097 if (!pdev->pm_cap) { 13098 dev_err(&bp->pdev->dev, 13099 "Cannot find power management capability, aborting\n"); 13100 rc = -EIO; 13101 goto err_out_release; 13102 } 13103 } 13104 13105 if (!pci_is_pcie(pdev)) { 13106 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 13107 rc = -EIO; 13108 goto err_out_release; 13109 } 13110 13111 rc = dma_set_mask_and_coherent(&bp->pdev->dev, DMA_BIT_MASK(64)); 13112 if (rc) { 13113 dev_err(&bp->pdev->dev, "System does not support DMA, aborting\n"); 13114 goto err_out_release; 13115 } 13116 13117 dev->mem_start = pci_resource_start(pdev, 0); 13118 dev->base_addr = dev->mem_start; 13119 dev->mem_end = pci_resource_end(pdev, 0); 13120 13121 dev->irq = pdev->irq; 13122 13123 bp->regview = pci_ioremap_bar(pdev, 0); 13124 if (!bp->regview) { 13125 dev_err(&bp->pdev->dev, 13126 "Cannot map register space, aborting\n"); 13127 rc = -ENOMEM; 13128 goto err_out_release; 13129 } 13130 13131 /* In E1/E1H use pci device function given by kernel. 13132 * In E2/E3 read physical function from ME register since these chips 13133 * support Physical Device Assignment where kernel BDF maybe arbitrary 13134 * (depending on hypervisor). 13135 */ 13136 if (chip_is_e1x) { 13137 bp->pf_num = PCI_FUNC(pdev->devfn); 13138 } else { 13139 /* chip is E2/3*/ 13140 pci_read_config_dword(bp->pdev, 13141 PCICFG_ME_REGISTER, &pci_cfg_dword); 13142 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 13143 ME_REG_ABS_PF_NUM_SHIFT); 13144 } 13145 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); 13146 13147 /* clean indirect addresses */ 13148 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, 13149 PCICFG_VENDOR_ID_OFFSET); 13150 13151 /* Set PCIe reset type to fundamental for EEH recovery */ 13152 pdev->needs_freset = 1; 13153 13154 /* 13155 * Clean the following indirect addresses for all functions since it 13156 * is not used by the driver. 13157 */ 13158 if (IS_PF(bp)) { 13159 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); 13160 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); 13161 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); 13162 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); 13163 13164 if (chip_is_e1x) { 13165 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); 13166 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); 13167 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); 13168 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); 13169 } 13170 13171 /* Enable internal target-read (in case we are probed after PF 13172 * FLR). Must be done prior to any BAR read access. Only for 13173 * 57712 and up 13174 */ 13175 if (!chip_is_e1x) 13176 REG_WR(bp, 13177 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 13178 } 13179 13180 dev->watchdog_timeo = TX_TIMEOUT; 13181 13182 dev->netdev_ops = &bnx2x_netdev_ops; 13183 bnx2x_set_ethtool_ops(bp, dev); 13184 13185 dev->priv_flags |= IFF_UNICAST_FLT; 13186 13187 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 13188 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 13189 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW | 13190 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX; 13191 if (!chip_is_e1x) { 13192 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | 13193 NETIF_F_GSO_IPXIP4 | 13194 NETIF_F_GSO_UDP_TUNNEL | 13195 NETIF_F_GSO_UDP_TUNNEL_CSUM | 13196 NETIF_F_GSO_PARTIAL; 13197 13198 dev->hw_enc_features = 13199 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | 13200 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | 13201 NETIF_F_GSO_IPXIP4 | 13202 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM | 13203 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | 13204 NETIF_F_GSO_PARTIAL; 13205 13206 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM | 13207 NETIF_F_GSO_UDP_TUNNEL_CSUM; 13208 13209 if (IS_PF(bp)) 13210 dev->udp_tunnel_nic_info = &bnx2x_udp_tunnels; 13211 } 13212 13213 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 13214 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA; 13215 13216 if (IS_PF(bp)) { 13217 if (chip_is_e1x) 13218 bp->accept_any_vlan = true; 13219 else 13220 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13221 } 13222 /* For VF we'll know whether to enable VLAN filtering after 13223 * getting a response to CHANNEL_TLV_ACQUIRE from PF. 13224 */ 13225 13226 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX; 13227 dev->features |= NETIF_F_HIGHDMA; 13228 if (dev->features & NETIF_F_LRO) 13229 dev->features &= ~NETIF_F_GRO_HW; 13230 13231 /* Add Loopback capability to the device */ 13232 dev->hw_features |= NETIF_F_LOOPBACK; 13233 13234#ifdef BCM_DCBNL 13235 dev->dcbnl_ops = &bnx2x_dcbnl_ops; 13236#endif 13237 13238 /* MTU range, 46 - 9600 */ 13239 dev->min_mtu = ETH_MIN_PACKET_SIZE; 13240 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE; 13241 13242 /* get_port_hwinfo() will set prtad and mmds properly */ 13243 bp->mdio.prtad = MDIO_PRTAD_NONE; 13244 bp->mdio.mmds = 0; 13245 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 13246 bp->mdio.dev = dev; 13247 bp->mdio.mdio_read = bnx2x_mdio_read; 13248 bp->mdio.mdio_write = bnx2x_mdio_write; 13249 13250 return 0; 13251 13252err_out_release: 13253 if (atomic_read(&pdev->enable_cnt) == 1) 13254 pci_release_regions(pdev); 13255 13256err_out_disable: 13257 pci_disable_device(pdev); 13258 13259err_out: 13260 return rc; 13261} 13262 13263static int bnx2x_check_firmware(struct bnx2x *bp) 13264{ 13265 const struct firmware *firmware = bp->firmware; 13266 struct bnx2x_fw_file_hdr *fw_hdr; 13267 struct bnx2x_fw_file_section *sections; 13268 u32 offset, len, num_ops; 13269 __be16 *ops_offsets; 13270 int i; 13271 const u8 *fw_ver; 13272 13273 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) { 13274 BNX2X_ERR("Wrong FW size\n"); 13275 return -EINVAL; 13276 } 13277 13278 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 13279 sections = (struct bnx2x_fw_file_section *)fw_hdr; 13280 13281 /* Make sure none of the offsets and sizes make us read beyond 13282 * the end of the firmware data */ 13283 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) { 13284 offset = be32_to_cpu(sections[i].offset); 13285 len = be32_to_cpu(sections[i].len); 13286 if (offset + len > firmware->size) { 13287 BNX2X_ERR("Section %d length is out of bounds\n", i); 13288 return -EINVAL; 13289 } 13290 } 13291 13292 /* Likewise for the init_ops offsets */ 13293 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset); 13294 ops_offsets = (__force __be16 *)(firmware->data + offset); 13295 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op); 13296 13297 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 13298 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 13299 BNX2X_ERR("Section offset %d is out of bounds\n", i); 13300 return -EINVAL; 13301 } 13302 } 13303 13304 /* Check FW version */ 13305 offset = be32_to_cpu(fw_hdr->fw_version.offset); 13306 fw_ver = firmware->data + offset; 13307 if (fw_ver[0] != bp->fw_major || fw_ver[1] != bp->fw_minor || 13308 fw_ver[2] != bp->fw_rev || fw_ver[3] != bp->fw_eng) { 13309 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 13310 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3], 13311 bp->fw_major, bp->fw_minor, bp->fw_rev, bp->fw_eng); 13312 return -EINVAL; 13313 } 13314 13315 return 0; 13316} 13317 13318static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 13319{ 13320 const __be32 *source = (const __be32 *)_source; 13321 u32 *target = (u32 *)_target; 13322 u32 i; 13323 13324 for (i = 0; i < n/4; i++) 13325 target[i] = be32_to_cpu(source[i]); 13326} 13327 13328/* 13329 Ops array is stored in the following format: 13330 {op(8bit), offset(24bit, big endian), data(32bit, big endian)} 13331 */ 13332static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n) 13333{ 13334 const __be32 *source = (const __be32 *)_source; 13335 struct raw_op *target = (struct raw_op *)_target; 13336 u32 i, j, tmp; 13337 13338 for (i = 0, j = 0; i < n/8; i++, j += 2) { 13339 tmp = be32_to_cpu(source[j]); 13340 target[i].op = (tmp >> 24) & 0xff; 13341 target[i].offset = tmp & 0xffffff; 13342 target[i].raw_data = be32_to_cpu(source[j + 1]); 13343 } 13344} 13345 13346/* IRO array is stored in the following format: 13347 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) } 13348 */ 13349static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n) 13350{ 13351 const __be32 *source = (const __be32 *)_source; 13352 struct iro *target = (struct iro *)_target; 13353 u32 i, j, tmp; 13354 13355 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) { 13356 target[i].base = be32_to_cpu(source[j]); 13357 j++; 13358 tmp = be32_to_cpu(source[j]); 13359 target[i].m1 = (tmp >> 16) & 0xffff; 13360 target[i].m2 = tmp & 0xffff; 13361 j++; 13362 tmp = be32_to_cpu(source[j]); 13363 target[i].m3 = (tmp >> 16) & 0xffff; 13364 target[i].size = tmp & 0xffff; 13365 j++; 13366 } 13367} 13368 13369static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n) 13370{ 13371 const __be16 *source = (const __be16 *)_source; 13372 u16 *target = (u16 *)_target; 13373 u32 i; 13374 13375 for (i = 0; i < n/2; i++) 13376 target[i] = be16_to_cpu(source[i]); 13377} 13378 13379#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \ 13380do { \ 13381 u32 len = be32_to_cpu(fw_hdr->arr.len); \ 13382 bp->arr = kmalloc(len, GFP_KERNEL); \ 13383 if (!bp->arr) \ 13384 goto lbl; \ 13385 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \ 13386 (u8 *)bp->arr, len); \ 13387} while (0) 13388 13389static int bnx2x_init_firmware(struct bnx2x *bp) 13390{ 13391 const char *fw_file_name, *fw_file_name_v15; 13392 struct bnx2x_fw_file_hdr *fw_hdr; 13393 int rc; 13394 13395 if (bp->firmware) 13396 return 0; 13397 13398 if (CHIP_IS_E1(bp)) { 13399 fw_file_name = FW_FILE_NAME_E1; 13400 fw_file_name_v15 = FW_FILE_NAME_E1_V15; 13401 } else if (CHIP_IS_E1H(bp)) { 13402 fw_file_name = FW_FILE_NAME_E1H; 13403 fw_file_name_v15 = FW_FILE_NAME_E1H_V15; 13404 } else if (!CHIP_IS_E1x(bp)) { 13405 fw_file_name = FW_FILE_NAME_E2; 13406 fw_file_name_v15 = FW_FILE_NAME_E2_V15; 13407 } else { 13408 BNX2X_ERR("Unsupported chip revision\n"); 13409 return -EINVAL; 13410 } 13411 13412 BNX2X_DEV_INFO("Loading %s\n", fw_file_name); 13413 13414 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); 13415 if (rc) { 13416 BNX2X_DEV_INFO("Trying to load older fw %s\n", fw_file_name_v15); 13417 13418 /* try to load prev version */ 13419 rc = request_firmware(&bp->firmware, fw_file_name_v15, &bp->pdev->dev); 13420 13421 if (rc) 13422 goto request_firmware_exit; 13423 13424 bp->fw_rev = BCM_5710_FW_REVISION_VERSION_V15; 13425 } else { 13426 bp->fw_cap |= FW_CAP_INVALIDATE_VF_FP_HSI; 13427 bp->fw_rev = BCM_5710_FW_REVISION_VERSION; 13428 } 13429 13430 bp->fw_major = BCM_5710_FW_MAJOR_VERSION; 13431 bp->fw_minor = BCM_5710_FW_MINOR_VERSION; 13432 bp->fw_eng = BCM_5710_FW_ENGINEERING_VERSION; 13433 13434 rc = bnx2x_check_firmware(bp); 13435 if (rc) { 13436 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name); 13437 goto request_firmware_exit; 13438 } 13439 13440 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; 13441 13442 /* Initialize the pointers to the init arrays */ 13443 /* Blob */ 13444 rc = -ENOMEM; 13445 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n); 13446 13447 /* Opcodes */ 13448 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops); 13449 13450 /* Offsets */ 13451 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err, 13452 be16_to_cpu_n); 13453 13454 /* STORMs firmware */ 13455 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13456 be32_to_cpu(fw_hdr->tsem_int_table_data.offset); 13457 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + 13458 be32_to_cpu(fw_hdr->tsem_pram_data.offset); 13459 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13460 be32_to_cpu(fw_hdr->usem_int_table_data.offset); 13461 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + 13462 be32_to_cpu(fw_hdr->usem_pram_data.offset); 13463 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13464 be32_to_cpu(fw_hdr->xsem_int_table_data.offset); 13465 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + 13466 be32_to_cpu(fw_hdr->xsem_pram_data.offset); 13467 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + 13468 be32_to_cpu(fw_hdr->csem_int_table_data.offset); 13469 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + 13470 be32_to_cpu(fw_hdr->csem_pram_data.offset); 13471 /* IRO */ 13472 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro); 13473 13474 return 0; 13475 13476iro_alloc_err: 13477 kfree(bp->init_ops_offsets); 13478init_offsets_alloc_err: 13479 kfree(bp->init_ops); 13480init_ops_alloc_err: 13481 kfree(bp->init_data); 13482request_firmware_exit: 13483 release_firmware(bp->firmware); 13484 bp->firmware = NULL; 13485 13486 return rc; 13487} 13488 13489static void bnx2x_release_firmware(struct bnx2x *bp) 13490{ 13491 kfree(bp->init_ops_offsets); 13492 kfree(bp->init_ops); 13493 kfree(bp->init_data); 13494 release_firmware(bp->firmware); 13495 bp->firmware = NULL; 13496} 13497 13498static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = { 13499 .init_hw_cmn_chip = bnx2x_init_hw_common_chip, 13500 .init_hw_cmn = bnx2x_init_hw_common, 13501 .init_hw_port = bnx2x_init_hw_port, 13502 .init_hw_func = bnx2x_init_hw_func, 13503 13504 .reset_hw_cmn = bnx2x_reset_common, 13505 .reset_hw_port = bnx2x_reset_port, 13506 .reset_hw_func = bnx2x_reset_func, 13507 13508 .gunzip_init = bnx2x_gunzip_init, 13509 .gunzip_end = bnx2x_gunzip_end, 13510 13511 .init_fw = bnx2x_init_firmware, 13512 .release_fw = bnx2x_release_firmware, 13513}; 13514 13515void bnx2x__init_func_obj(struct bnx2x *bp) 13516{ 13517 /* Prepare DMAE related driver resources */ 13518 bnx2x_setup_dmae(bp); 13519 13520 bnx2x_init_func_obj(bp, &bp->func_obj, 13521 bnx2x_sp(bp, func_rdata), 13522 bnx2x_sp_mapping(bp, func_rdata), 13523 bnx2x_sp(bp, func_afex_rdata), 13524 bnx2x_sp_mapping(bp, func_afex_rdata), 13525 &bnx2x_func_sp_drv); 13526} 13527 13528/* must be called after sriov-enable */ 13529static int bnx2x_set_qm_cid_count(struct bnx2x *bp) 13530{ 13531 int cid_count = BNX2X_L2_MAX_CID(bp); 13532 13533 if (IS_SRIOV(bp)) 13534 cid_count += BNX2X_VF_CIDS; 13535 13536 if (CNIC_SUPPORT(bp)) 13537 cid_count += CNIC_CID_MAX; 13538 13539 return roundup(cid_count, QM_CID_ROUND); 13540} 13541 13542/** 13543 * bnx2x_get_num_non_def_sbs - return the number of none default SBs 13544 * @pdev: pci device 13545 * @cnic_cnt: count 13546 * 13547 */ 13548static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt) 13549{ 13550 int index; 13551 u16 control = 0; 13552 13553 /* 13554 * If MSI-X is not supported - return number of SBs needed to support 13555 * one fast path queue: one FP queue + SB for CNIC 13556 */ 13557 if (!pdev->msix_cap) { 13558 dev_info(&pdev->dev, "no msix capability found\n"); 13559 return 1 + cnic_cnt; 13560 } 13561 dev_info(&pdev->dev, "msix capability found\n"); 13562 13563 /* 13564 * The value in the PCI configuration space is the index of the last 13565 * entry, namely one less than the actual size of the table, which is 13566 * exactly what we want to return from this function: number of all SBs 13567 * without the default SB. 13568 * For VFs there is no default SB, then we return (index+1). 13569 */ 13570 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control); 13571 13572 index = control & PCI_MSIX_FLAGS_QSIZE; 13573 13574 return index; 13575} 13576 13577static int set_max_cos_est(int chip_id) 13578{ 13579 switch (chip_id) { 13580 case BCM57710: 13581 case BCM57711: 13582 case BCM57711E: 13583 return BNX2X_MULTI_TX_COS_E1X; 13584 case BCM57712: 13585 case BCM57712_MF: 13586 return BNX2X_MULTI_TX_COS_E2_E3A0; 13587 case BCM57800: 13588 case BCM57800_MF: 13589 case BCM57810: 13590 case BCM57810_MF: 13591 case BCM57840_4_10: 13592 case BCM57840_2_20: 13593 case BCM57840_O: 13594 case BCM57840_MFO: 13595 case BCM57840_MF: 13596 case BCM57811: 13597 case BCM57811_MF: 13598 return BNX2X_MULTI_TX_COS_E3B0; 13599 case BCM57712_VF: 13600 case BCM57800_VF: 13601 case BCM57810_VF: 13602 case BCM57840_VF: 13603 case BCM57811_VF: 13604 return 1; 13605 default: 13606 pr_err("Unknown board_type (%d), aborting\n", chip_id); 13607 return -ENODEV; 13608 } 13609} 13610 13611static int set_is_vf(int chip_id) 13612{ 13613 switch (chip_id) { 13614 case BCM57712_VF: 13615 case BCM57800_VF: 13616 case BCM57810_VF: 13617 case BCM57840_VF: 13618 case BCM57811_VF: 13619 return true; 13620 default: 13621 return false; 13622 } 13623} 13624 13625/* nig_tsgen registers relative address */ 13626#define tsgen_ctrl 0x0 13627#define tsgen_freecount 0x10 13628#define tsgen_synctime_t0 0x20 13629#define tsgen_offset_t0 0x28 13630#define tsgen_drift_t0 0x30 13631#define tsgen_synctime_t1 0x58 13632#define tsgen_offset_t1 0x60 13633#define tsgen_drift_t1 0x68 13634 13635/* FW workaround for setting drift */ 13636static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, 13637 int best_val, int best_period) 13638{ 13639 struct bnx2x_func_state_params func_params = {NULL}; 13640 struct bnx2x_func_set_timesync_params *set_timesync_params = 13641 &func_params.params.set_timesync; 13642 13643 /* Prepare parameters for function state transitions */ 13644 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 13645 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 13646 13647 func_params.f_obj = &bp->func_obj; 13648 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; 13649 13650 /* Function parameters */ 13651 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET; 13652 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; 13653 set_timesync_params->add_sub_drift_adjust_value = 13654 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE; 13655 set_timesync_params->drift_adjust_value = best_val; 13656 set_timesync_params->drift_adjust_period = best_period; 13657 13658 return bnx2x_func_state_change(bp, &func_params); 13659} 13660 13661static int bnx2x_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 13662{ 13663 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13664 int rc; 13665 int drift_dir = 1; 13666 int val, period, period1, period2, dif, dif1, dif2; 13667 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0; 13668 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 13669 13670 DP(BNX2X_MSG_PTP, "PTP adjfine called, ppb = %d\n", ppb); 13671 13672 if (!netif_running(bp->dev)) { 13673 DP(BNX2X_MSG_PTP, 13674 "PTP adjfine called while the interface is down\n"); 13675 return -ENETDOWN; 13676 } 13677 13678 if (ppb < 0) { 13679 ppb = -ppb; 13680 drift_dir = 0; 13681 } 13682 13683 if (ppb == 0) { 13684 best_val = 1; 13685 best_period = 0x1FFFFFF; 13686 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) { 13687 best_val = 31; 13688 best_period = 1; 13689 } else { 13690 /* Changed not to allow val = 8, 16, 24 as these values 13691 * are not supported in workaround. 13692 */ 13693 for (val = 0; val <= 31; val++) { 13694 if ((val & 0x7) == 0) 13695 continue; 13696 period1 = val * 1000000 / ppb; 13697 period2 = period1 + 1; 13698 if (period1 != 0) 13699 dif1 = ppb - (val * 1000000 / period1); 13700 else 13701 dif1 = BNX2X_MAX_PHC_DRIFT; 13702 if (dif1 < 0) 13703 dif1 = -dif1; 13704 dif2 = ppb - (val * 1000000 / period2); 13705 if (dif2 < 0) 13706 dif2 = -dif2; 13707 dif = (dif1 < dif2) ? dif1 : dif2; 13708 period = (dif1 < dif2) ? period1 : period2; 13709 if (dif < best_dif) { 13710 best_dif = dif; 13711 best_val = val; 13712 best_period = period; 13713 } 13714 } 13715 } 13716 13717 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, 13718 best_period); 13719 if (rc) { 13720 BNX2X_ERR("Failed to set drift\n"); 13721 return -EFAULT; 13722 } 13723 13724 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val, 13725 best_period); 13726 13727 return 0; 13728} 13729 13730static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 13731{ 13732 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13733 13734 if (!netif_running(bp->dev)) { 13735 DP(BNX2X_MSG_PTP, 13736 "PTP adjtime called while the interface is down\n"); 13737 return -ENETDOWN; 13738 } 13739 13740 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta); 13741 13742 timecounter_adjtime(&bp->timecounter, delta); 13743 13744 return 0; 13745} 13746 13747static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 13748{ 13749 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13750 u64 ns; 13751 13752 if (!netif_running(bp->dev)) { 13753 DP(BNX2X_MSG_PTP, 13754 "PTP gettime called while the interface is down\n"); 13755 return -ENETDOWN; 13756 } 13757 13758 ns = timecounter_read(&bp->timecounter); 13759 13760 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns); 13761 13762 *ts = ns_to_timespec64(ns); 13763 13764 return 0; 13765} 13766 13767static int bnx2x_ptp_settime(struct ptp_clock_info *ptp, 13768 const struct timespec64 *ts) 13769{ 13770 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13771 u64 ns; 13772 13773 if (!netif_running(bp->dev)) { 13774 DP(BNX2X_MSG_PTP, 13775 "PTP settime called while the interface is down\n"); 13776 return -ENETDOWN; 13777 } 13778 13779 ns = timespec64_to_ns(ts); 13780 13781 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns); 13782 13783 /* Re-init the timecounter */ 13784 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); 13785 13786 return 0; 13787} 13788 13789/* Enable (or disable) ancillary features of the phc subsystem */ 13790static int bnx2x_ptp_enable(struct ptp_clock_info *ptp, 13791 struct ptp_clock_request *rq, int on) 13792{ 13793 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); 13794 13795 BNX2X_ERR("PHC ancillary features are not supported\n"); 13796 return -ENOTSUPP; 13797} 13798 13799void bnx2x_register_phc(struct bnx2x *bp) 13800{ 13801 /* Fill the ptp_clock_info struct and register PTP clock*/ 13802 bp->ptp_clock_info.owner = THIS_MODULE; 13803 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); 13804 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ 13805 bp->ptp_clock_info.n_alarm = 0; 13806 bp->ptp_clock_info.n_ext_ts = 0; 13807 bp->ptp_clock_info.n_per_out = 0; 13808 bp->ptp_clock_info.pps = 0; 13809 bp->ptp_clock_info.adjfine = bnx2x_ptp_adjfine; 13810 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; 13811 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; 13812 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; 13813 bp->ptp_clock_info.enable = bnx2x_ptp_enable; 13814 13815 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); 13816 if (IS_ERR(bp->ptp_clock)) { 13817 bp->ptp_clock = NULL; 13818 BNX2X_ERR("PTP clock registration failed\n"); 13819 } 13820} 13821 13822static int bnx2x_init_one(struct pci_dev *pdev, 13823 const struct pci_device_id *ent) 13824{ 13825 struct net_device *dev = NULL; 13826 struct bnx2x *bp; 13827 int rc, max_non_def_sbs; 13828 int rx_count, tx_count, rss_count, doorbell_size; 13829 int max_cos_est; 13830 bool is_vf; 13831 int cnic_cnt; 13832 13833 /* Management FW 'remembers' living interfaces. Allow it some time 13834 * to forget previously living interfaces, allowing a proper re-load. 13835 */ 13836 if (is_kdump_kernel()) { 13837 ktime_t now = ktime_get_boottime(); 13838 ktime_t fw_ready_time = ktime_set(5, 0); 13839 13840 if (ktime_before(now, fw_ready_time)) 13841 msleep(ktime_ms_delta(fw_ready_time, now)); 13842 } 13843 13844 /* An estimated maximum supported CoS number according to the chip 13845 * version. 13846 * We will try to roughly estimate the maximum number of CoSes this chip 13847 * may support in order to minimize the memory allocated for Tx 13848 * netdev_queue's. This number will be accurately calculated during the 13849 * initialization of bp->max_cos based on the chip versions AND chip 13850 * revision in the bnx2x_init_bp(). 13851 */ 13852 max_cos_est = set_max_cos_est(ent->driver_data); 13853 if (max_cos_est < 0) 13854 return max_cos_est; 13855 is_vf = set_is_vf(ent->driver_data); 13856 cnic_cnt = is_vf ? 0 : 1; 13857 13858 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt); 13859 13860 /* add another SB for VF as it has no default SB */ 13861 max_non_def_sbs += is_vf ? 1 : 0; 13862 13863 /* Maximum number of RSS queues: one IGU SB goes to CNIC */ 13864 rss_count = max_non_def_sbs - cnic_cnt; 13865 13866 if (rss_count < 1) 13867 return -EINVAL; 13868 13869 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */ 13870 rx_count = rss_count + cnic_cnt; 13871 13872 /* Maximum number of netdev Tx queues: 13873 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2 13874 */ 13875 tx_count = rss_count * max_cos_est + cnic_cnt; 13876 13877 /* dev zeroed in init_etherdev */ 13878 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); 13879 if (!dev) 13880 return -ENOMEM; 13881 13882 bp = netdev_priv(dev); 13883 13884 bp->flags = 0; 13885 if (is_vf) 13886 bp->flags |= IS_VF_FLAG; 13887 13888 bp->igu_sb_cnt = max_non_def_sbs; 13889 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; 13890 bp->msg_enable = debug; 13891 bp->cnic_support = cnic_cnt; 13892 bp->cnic_probe = bnx2x_cnic_probe; 13893 13894 pci_set_drvdata(pdev, dev); 13895 13896 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); 13897 if (rc < 0) { 13898 free_netdev(dev); 13899 return rc; 13900 } 13901 13902 BNX2X_DEV_INFO("This is a %s function\n", 13903 IS_PF(bp) ? "physical" : "virtual"); 13904 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); 13905 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs); 13906 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n", 13907 tx_count, rx_count); 13908 13909 rc = bnx2x_init_bp(bp); 13910 if (rc) 13911 goto init_one_exit; 13912 13913 /* Map doorbells here as we need the real value of bp->max_cos which 13914 * is initialized in bnx2x_init_bp() to determine the number of 13915 * l2 connections. 13916 */ 13917 if (IS_VF(bp)) { 13918 bp->doorbells = bnx2x_vf_doorbells(bp); 13919 rc = bnx2x_vf_pci_alloc(bp); 13920 if (rc) 13921 goto init_one_freemem; 13922 } else { 13923 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); 13924 if (doorbell_size > pci_resource_len(pdev, 2)) { 13925 dev_err(&bp->pdev->dev, 13926 "Cannot map doorbells, bar size too small, aborting\n"); 13927 rc = -ENOMEM; 13928 goto init_one_freemem; 13929 } 13930 bp->doorbells = ioremap(pci_resource_start(pdev, 2), 13931 doorbell_size); 13932 } 13933 if (!bp->doorbells) { 13934 dev_err(&bp->pdev->dev, 13935 "Cannot map doorbell space, aborting\n"); 13936 rc = -ENOMEM; 13937 goto init_one_freemem; 13938 } 13939 13940 if (IS_VF(bp)) { 13941 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); 13942 if (rc) 13943 goto init_one_freemem; 13944 13945#ifdef CONFIG_BNX2X_SRIOV 13946 /* VF with OLD Hypervisor or old PF do not support filtering */ 13947 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) { 13948 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13949 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 13950 } 13951#endif 13952 } 13953 13954 /* Enable SRIOV if capability found in configuration space */ 13955 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); 13956 if (rc) 13957 goto init_one_freemem; 13958 13959 /* calc qm_cid_count */ 13960 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); 13961 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); 13962 13963 /* disable FCOE L2 queue for E1x*/ 13964 if (CHIP_IS_E1x(bp)) 13965 bp->flags |= NO_FCOE_FLAG; 13966 13967 /* Set bp->num_queues for MSI-X mode*/ 13968 bnx2x_set_num_queues(bp); 13969 13970 /* Configure interrupt mode: try to enable MSI-X/MSI if 13971 * needed. 13972 */ 13973 rc = bnx2x_set_int_mode(bp); 13974 if (rc) { 13975 dev_err(&pdev->dev, "Cannot set interrupts\n"); 13976 goto init_one_freemem; 13977 } 13978 BNX2X_DEV_INFO("set interrupts successfully\n"); 13979 13980 /* register the net device */ 13981 rc = register_netdev(dev); 13982 if (rc) { 13983 dev_err(&pdev->dev, "Cannot register net device\n"); 13984 goto init_one_freemem; 13985 } 13986 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name); 13987 13988 if (!NO_FCOE(bp)) { 13989 /* Add storage MAC address */ 13990 rtnl_lock(); 13991 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 13992 rtnl_unlock(); 13993 } 13994 BNX2X_DEV_INFO( 13995 "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n", 13996 board_info[ent->driver_data].name, 13997 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 13998 dev->base_addr, bp->pdev->irq, dev->dev_addr); 13999 pcie_print_link_status(bp->pdev); 14000 14001 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) 14002 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED); 14003 14004 return 0; 14005 14006init_one_freemem: 14007 bnx2x_free_mem_bp(bp); 14008 14009init_one_exit: 14010 if (bp->regview) 14011 iounmap(bp->regview); 14012 14013 if (IS_PF(bp) && bp->doorbells) 14014 iounmap(bp->doorbells); 14015 14016 free_netdev(dev); 14017 14018 if (atomic_read(&pdev->enable_cnt) == 1) 14019 pci_release_regions(pdev); 14020 14021 pci_disable_device(pdev); 14022 14023 return rc; 14024} 14025 14026static void __bnx2x_remove(struct pci_dev *pdev, 14027 struct net_device *dev, 14028 struct bnx2x *bp, 14029 bool remove_netdev) 14030{ 14031 /* Delete storage MAC address */ 14032 if (!NO_FCOE(bp)) { 14033 rtnl_lock(); 14034 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); 14035 rtnl_unlock(); 14036 } 14037 14038#ifdef BCM_DCBNL 14039 /* Delete app tlvs from dcbnl */ 14040 bnx2x_dcbnl_update_applist(bp, true); 14041#endif 14042 14043 if (IS_PF(bp) && 14044 !BP_NOMCP(bp) && 14045 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) 14046 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); 14047 14048 /* Close the interface - either directly or implicitly */ 14049 if (remove_netdev) { 14050 unregister_netdev(dev); 14051 } else { 14052 rtnl_lock(); 14053 dev_close(dev); 14054 rtnl_unlock(); 14055 } 14056 14057 bnx2x_iov_remove_one(bp); 14058 14059 /* Power on: we can't let PCI layer write to us while we are in D3 */ 14060 if (IS_PF(bp)) { 14061 bnx2x_set_power_state(bp, PCI_D0); 14062 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED); 14063 14064 /* Set endianity registers to reset values in case next driver 14065 * boots in different endianty environment. 14066 */ 14067 bnx2x_reset_endianity(bp); 14068 } 14069 14070 /* Disable MSI/MSI-X */ 14071 bnx2x_disable_msi(bp); 14072 14073 /* Power off */ 14074 if (IS_PF(bp)) 14075 bnx2x_set_power_state(bp, PCI_D3hot); 14076 14077 /* Make sure RESET task is not scheduled before continuing */ 14078 cancel_delayed_work_sync(&bp->sp_rtnl_task); 14079 14080 /* send message via vfpf channel to release the resources of this vf */ 14081 if (IS_VF(bp)) 14082 bnx2x_vfpf_release(bp); 14083 14084 /* Assumes no further PCIe PM changes will occur */ 14085 if (system_state == SYSTEM_POWER_OFF) { 14086 pci_wake_from_d3(pdev, bp->wol); 14087 pci_set_power_state(pdev, PCI_D3hot); 14088 } 14089 14090 if (remove_netdev) { 14091 if (bp->regview) 14092 iounmap(bp->regview); 14093 14094 /* For vfs, doorbells are part of the regview and were unmapped 14095 * along with it. FW is only loaded by PF. 14096 */ 14097 if (IS_PF(bp)) { 14098 if (bp->doorbells) 14099 iounmap(bp->doorbells); 14100 14101 bnx2x_release_firmware(bp); 14102 } else { 14103 bnx2x_vf_pci_dealloc(bp); 14104 } 14105 bnx2x_free_mem_bp(bp); 14106 14107 free_netdev(dev); 14108 14109 if (atomic_read(&pdev->enable_cnt) == 1) 14110 pci_release_regions(pdev); 14111 14112 pci_disable_device(pdev); 14113 } 14114} 14115 14116static void bnx2x_remove_one(struct pci_dev *pdev) 14117{ 14118 struct net_device *dev = pci_get_drvdata(pdev); 14119 struct bnx2x *bp; 14120 14121 if (!dev) { 14122 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n"); 14123 return; 14124 } 14125 bp = netdev_priv(dev); 14126 14127 __bnx2x_remove(pdev, dev, bp, true); 14128} 14129 14130static int bnx2x_eeh_nic_unload(struct bnx2x *bp) 14131{ 14132 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; 14133 14134 bp->rx_mode = BNX2X_RX_MODE_NONE; 14135 14136 if (CNIC_LOADED(bp)) 14137 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); 14138 14139 /* Stop Tx */ 14140 bnx2x_tx_disable(bp); 14141 netdev_reset_tc(bp->dev); 14142 14143 del_timer_sync(&bp->timer); 14144 cancel_delayed_work_sync(&bp->sp_task); 14145 cancel_delayed_work_sync(&bp->period_task); 14146 14147 if (!down_timeout(&bp->stats_lock, HZ / 10)) { 14148 bp->stats_state = STATS_STATE_DISABLED; 14149 up(&bp->stats_lock); 14150 } 14151 14152 bnx2x_save_statistics(bp); 14153 14154 netif_carrier_off(bp->dev); 14155 14156 return 0; 14157} 14158 14159/** 14160 * bnx2x_io_error_detected - called when PCI error is detected 14161 * @pdev: Pointer to PCI device 14162 * @state: The current pci connection state 14163 * 14164 * This function is called after a PCI bus error affecting 14165 * this device has been detected. 14166 */ 14167static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev, 14168 pci_channel_state_t state) 14169{ 14170 struct net_device *dev = pci_get_drvdata(pdev); 14171 struct bnx2x *bp = netdev_priv(dev); 14172 14173 rtnl_lock(); 14174 14175 BNX2X_ERR("IO error detected\n"); 14176 14177 netif_device_detach(dev); 14178 14179 if (state == pci_channel_io_perm_failure) { 14180 rtnl_unlock(); 14181 return PCI_ERS_RESULT_DISCONNECT; 14182 } 14183 14184 if (netif_running(dev)) 14185 bnx2x_eeh_nic_unload(bp); 14186 14187 bnx2x_prev_path_mark_eeh(bp); 14188 14189 pci_disable_device(pdev); 14190 14191 rtnl_unlock(); 14192 14193 /* Request a slot reset */ 14194 return PCI_ERS_RESULT_NEED_RESET; 14195} 14196 14197/** 14198 * bnx2x_io_slot_reset - called after the PCI bus has been reset 14199 * @pdev: Pointer to PCI device 14200 * 14201 * Restart the card from scratch, as if from a cold-boot. 14202 */ 14203static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev) 14204{ 14205 struct net_device *dev = pci_get_drvdata(pdev); 14206 struct bnx2x *bp = netdev_priv(dev); 14207 int i; 14208 14209 rtnl_lock(); 14210 BNX2X_ERR("IO slot reset initializing...\n"); 14211 if (pci_enable_device(pdev)) { 14212 dev_err(&pdev->dev, 14213 "Cannot re-enable PCI device after reset\n"); 14214 rtnl_unlock(); 14215 return PCI_ERS_RESULT_DISCONNECT; 14216 } 14217 14218 pci_set_master(pdev); 14219 pci_restore_state(pdev); 14220 pci_save_state(pdev); 14221 14222 if (netif_running(dev)) 14223 bnx2x_set_power_state(bp, PCI_D0); 14224 14225 if (netif_running(dev)) { 14226 BNX2X_ERR("IO slot reset --> driver unload\n"); 14227 14228 /* MCP should have been reset; Need to wait for validity */ 14229 if (bnx2x_init_shmem(bp)) { 14230 rtnl_unlock(); 14231 return PCI_ERS_RESULT_DISCONNECT; 14232 } 14233 14234 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { 14235 u32 v; 14236 14237 v = SHMEM2_RD(bp, 14238 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); 14239 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], 14240 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 14241 } 14242 bnx2x_drain_tx_queues(bp); 14243 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); 14244 if (!bp->nic_stopped) { 14245 bnx2x_netif_stop(bp, 1); 14246 bnx2x_del_all_napi(bp); 14247 14248 if (CNIC_LOADED(bp)) 14249 bnx2x_del_all_napi_cnic(bp); 14250 14251 bnx2x_free_irq(bp); 14252 bp->nic_stopped = true; 14253 } 14254 14255 /* Report UNLOAD_DONE to MCP */ 14256 bnx2x_send_unload_done(bp, true); 14257 14258 bp->sp_state = 0; 14259 bp->port.pmf = 0; 14260 14261 bnx2x_prev_unload(bp); 14262 14263 /* We should have reseted the engine, so It's fair to 14264 * assume the FW will no longer write to the bnx2x driver. 14265 */ 14266 bnx2x_squeeze_objects(bp); 14267 bnx2x_free_skbs(bp); 14268 for_each_rx_queue(bp, i) 14269 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); 14270 bnx2x_free_fp_mem(bp); 14271 bnx2x_free_mem(bp); 14272 14273 bp->state = BNX2X_STATE_CLOSED; 14274 } 14275 14276 rtnl_unlock(); 14277 14278 return PCI_ERS_RESULT_RECOVERED; 14279} 14280 14281/** 14282 * bnx2x_io_resume - called when traffic can start flowing again 14283 * @pdev: Pointer to PCI device 14284 * 14285 * This callback is called when the error recovery driver tells us that 14286 * its OK to resume normal operation. 14287 */ 14288static void bnx2x_io_resume(struct pci_dev *pdev) 14289{ 14290 struct net_device *dev = pci_get_drvdata(pdev); 14291 struct bnx2x *bp = netdev_priv(dev); 14292 14293 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 14294 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); 14295 return; 14296 } 14297 14298 rtnl_lock(); 14299 14300 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & 14301 DRV_MSG_SEQ_NUMBER_MASK; 14302 14303 if (netif_running(dev)) { 14304 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 14305 netdev_err(bp->dev, "Error during driver initialization, try unloading/reloading the driver\n"); 14306 goto done; 14307 } 14308 } 14309 14310 netif_device_attach(dev); 14311 14312done: 14313 rtnl_unlock(); 14314} 14315 14316static const struct pci_error_handlers bnx2x_err_handler = { 14317 .error_detected = bnx2x_io_error_detected, 14318 .slot_reset = bnx2x_io_slot_reset, 14319 .resume = bnx2x_io_resume, 14320}; 14321 14322static void bnx2x_shutdown(struct pci_dev *pdev) 14323{ 14324 struct net_device *dev = pci_get_drvdata(pdev); 14325 struct bnx2x *bp; 14326 14327 if (!dev) 14328 return; 14329 14330 bp = netdev_priv(dev); 14331 if (!bp) 14332 return; 14333 14334 rtnl_lock(); 14335 netif_device_detach(dev); 14336 rtnl_unlock(); 14337 14338 /* Don't remove the netdevice, as there are scenarios which will cause 14339 * the kernel to hang, e.g., when trying to remove bnx2i while the 14340 * rootfs is mounted from SAN. 14341 */ 14342 __bnx2x_remove(pdev, dev, bp, false); 14343} 14344 14345static struct pci_driver bnx2x_pci_driver = { 14346 .name = DRV_MODULE_NAME, 14347 .id_table = bnx2x_pci_tbl, 14348 .probe = bnx2x_init_one, 14349 .remove = bnx2x_remove_one, 14350 .driver.pm = &bnx2x_pm_ops, 14351 .err_handler = &bnx2x_err_handler, 14352#ifdef CONFIG_BNX2X_SRIOV 14353 .sriov_configure = bnx2x_sriov_configure, 14354#endif 14355 .shutdown = bnx2x_shutdown, 14356}; 14357 14358static int __init bnx2x_init(void) 14359{ 14360 int ret; 14361 14362 bnx2x_wq = create_singlethread_workqueue("bnx2x"); 14363 if (bnx2x_wq == NULL) { 14364 pr_err("Cannot create workqueue\n"); 14365 return -ENOMEM; 14366 } 14367 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov"); 14368 if (!bnx2x_iov_wq) { 14369 pr_err("Cannot create iov workqueue\n"); 14370 destroy_workqueue(bnx2x_wq); 14371 return -ENOMEM; 14372 } 14373 14374 ret = pci_register_driver(&bnx2x_pci_driver); 14375 if (ret) { 14376 pr_err("Cannot register driver\n"); 14377 destroy_workqueue(bnx2x_wq); 14378 destroy_workqueue(bnx2x_iov_wq); 14379 } 14380 return ret; 14381} 14382 14383static void __exit bnx2x_cleanup(void) 14384{ 14385 struct list_head *pos, *q; 14386 14387 pci_unregister_driver(&bnx2x_pci_driver); 14388 14389 destroy_workqueue(bnx2x_wq); 14390 destroy_workqueue(bnx2x_iov_wq); 14391 14392 /* Free globally allocated resources */ 14393 list_for_each_safe(pos, q, &bnx2x_prev_list) { 14394 struct bnx2x_prev_path_list *tmp = 14395 list_entry(pos, struct bnx2x_prev_path_list, list); 14396 list_del(pos); 14397 kfree(tmp); 14398 } 14399} 14400 14401void bnx2x_notify_link_changed(struct bnx2x *bp) 14402{ 14403 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); 14404} 14405 14406module_init(bnx2x_init); 14407module_exit(bnx2x_cleanup); 14408 14409/** 14410 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s). 14411 * @bp: driver handle 14412 * 14413 * This function will wait until the ramrod completion returns. 14414 * Return 0 if success, -ENODEV if ramrod doesn't return. 14415 */ 14416static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) 14417{ 14418 unsigned long ramrod_flags = 0; 14419 14420 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 14421 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, 14422 &bp->iscsi_l2_mac_obj, true, 14423 BNX2X_ISCSI_ETH_MAC, &ramrod_flags); 14424} 14425 14426/* count denotes the number of new completions we have seen */ 14427static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) 14428{ 14429 struct eth_spe *spe; 14430 int cxt_index, cxt_offset; 14431 14432#ifdef BNX2X_STOP_ON_ERROR 14433 if (unlikely(bp->panic)) 14434 return; 14435#endif 14436 14437 spin_lock_bh(&bp->spq_lock); 14438 BUG_ON(bp->cnic_spq_pending < count); 14439 bp->cnic_spq_pending -= count; 14440 14441 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { 14442 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) 14443 & SPE_HDR_CONN_TYPE) >> 14444 SPE_HDR_CONN_TYPE_SHIFT; 14445 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) 14446 >> SPE_HDR_CMD_ID_SHIFT) & 0xff; 14447 14448 /* Set validation for iSCSI L2 client before sending SETUP 14449 * ramrod 14450 */ 14451 if (type == ETH_CONNECTION_TYPE) { 14452 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) { 14453 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / 14454 ILT_PAGE_CIDS; 14455 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - 14456 (cxt_index * ILT_PAGE_CIDS); 14457 bnx2x_set_ctx_validation(bp, 14458 &bp->context[cxt_index]. 14459 vcxt[cxt_offset].eth, 14460 BNX2X_ISCSI_ETH_CID(bp)); 14461 } 14462 } 14463 14464 /* 14465 * There may be not more than 8 L2, not more than 8 L5 SPEs 14466 * and in the air. We also check that number of outstanding 14467 * COMMON ramrods is not more than the EQ and SPQ can 14468 * accommodate. 14469 */ 14470 if (type == ETH_CONNECTION_TYPE) { 14471 if (!atomic_read(&bp->cq_spq_left)) 14472 break; 14473 else 14474 atomic_dec(&bp->cq_spq_left); 14475 } else if (type == NONE_CONNECTION_TYPE) { 14476 if (!atomic_read(&bp->eq_spq_left)) 14477 break; 14478 else 14479 atomic_dec(&bp->eq_spq_left); 14480 } else if ((type == ISCSI_CONNECTION_TYPE) || 14481 (type == FCOE_CONNECTION_TYPE)) { 14482 if (bp->cnic_spq_pending >= 14483 bp->cnic_eth_dev.max_kwqe_pending) 14484 break; 14485 else 14486 bp->cnic_spq_pending++; 14487 } else { 14488 BNX2X_ERR("Unknown SPE type: %d\n", type); 14489 bnx2x_panic(); 14490 break; 14491 } 14492 14493 spe = bnx2x_sp_get_next(bp); 14494 *spe = *bp->cnic_kwq_cons; 14495 14496 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n", 14497 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 14498 14499 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 14500 bp->cnic_kwq_cons = bp->cnic_kwq; 14501 else 14502 bp->cnic_kwq_cons++; 14503 } 14504 bnx2x_sp_prod_update(bp); 14505 spin_unlock_bh(&bp->spq_lock); 14506} 14507 14508static int bnx2x_cnic_sp_queue(struct net_device *dev, 14509 struct kwqe_16 *kwqes[], u32 count) 14510{ 14511 struct bnx2x *bp = netdev_priv(dev); 14512 int i; 14513 14514#ifdef BNX2X_STOP_ON_ERROR 14515 if (unlikely(bp->panic)) { 14516 BNX2X_ERR("Can't post to SP queue while panic\n"); 14517 return -EIO; 14518 } 14519#endif 14520 14521 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 14522 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 14523 BNX2X_ERR("Handling parity error recovery. Try again later\n"); 14524 return -EAGAIN; 14525 } 14526 14527 spin_lock_bh(&bp->spq_lock); 14528 14529 for (i = 0; i < count; i++) { 14530 struct eth_spe *spe = (struct eth_spe *)kwqes[i]; 14531 14532 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) 14533 break; 14534 14535 *bp->cnic_kwq_prod = *spe; 14536 14537 bp->cnic_kwq_pending++; 14538 14539 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n", 14540 spe->hdr.conn_and_cmd_data, spe->hdr.type, 14541 spe->data.update_data_addr.hi, 14542 spe->data.update_data_addr.lo, 14543 bp->cnic_kwq_pending); 14544 14545 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) 14546 bp->cnic_kwq_prod = bp->cnic_kwq; 14547 else 14548 bp->cnic_kwq_prod++; 14549 } 14550 14551 spin_unlock_bh(&bp->spq_lock); 14552 14553 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) 14554 bnx2x_cnic_sp_post(bp, 0); 14555 14556 return i; 14557} 14558 14559static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) 14560{ 14561 struct cnic_ops *c_ops; 14562 int rc = 0; 14563 14564 mutex_lock(&bp->cnic_mutex); 14565 c_ops = rcu_dereference_protected(bp->cnic_ops, 14566 lockdep_is_held(&bp->cnic_mutex)); 14567 if (c_ops) 14568 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 14569 mutex_unlock(&bp->cnic_mutex); 14570 14571 return rc; 14572} 14573 14574static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) 14575{ 14576 struct cnic_ops *c_ops; 14577 int rc = 0; 14578 14579 rcu_read_lock(); 14580 c_ops = rcu_dereference(bp->cnic_ops); 14581 if (c_ops) 14582 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); 14583 rcu_read_unlock(); 14584 14585 return rc; 14586} 14587 14588/* 14589 * for commands that have no data 14590 */ 14591int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) 14592{ 14593 struct cnic_ctl_info ctl = {0}; 14594 14595 ctl.cmd = cmd; 14596 14597 return bnx2x_cnic_ctl_send(bp, &ctl); 14598} 14599 14600static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) 14601{ 14602 struct cnic_ctl_info ctl = {0}; 14603 14604 /* first we tell CNIC and only then we count this as a completion */ 14605 ctl.cmd = CNIC_CTL_COMPLETION_CMD; 14606 ctl.data.comp.cid = cid; 14607 ctl.data.comp.error = err; 14608 14609 bnx2x_cnic_ctl_send_bh(bp, &ctl); 14610 bnx2x_cnic_sp_post(bp, 0); 14611} 14612 14613/* Called with netif_addr_lock_bh() taken. 14614 * Sets an rx_mode config for an iSCSI ETH client. 14615 * Doesn't block. 14616 * Completion should be checked outside. 14617 */ 14618static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) 14619{ 14620 unsigned long accept_flags = 0, ramrod_flags = 0; 14621 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 14622 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED; 14623 14624 if (start) { 14625 /* Start accepting on iSCSI L2 ring. Accept all multicasts 14626 * because it's the only way for UIO Queue to accept 14627 * multicasts (in non-promiscuous mode only one Queue per 14628 * function will receive multicast packets (leading in our 14629 * case). 14630 */ 14631 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags); 14632 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags); 14633 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags); 14634 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags); 14635 14636 /* Clear STOP_PENDING bit if START is requested */ 14637 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); 14638 14639 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED; 14640 } else 14641 /* Clear START_PENDING bit if STOP is requested */ 14642 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); 14643 14644 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) 14645 set_bit(sched_state, &bp->sp_state); 14646 else { 14647 __set_bit(RAMROD_RX, &ramrod_flags); 14648 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, 14649 ramrod_flags); 14650 } 14651} 14652 14653static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl) 14654{ 14655 struct bnx2x *bp = netdev_priv(dev); 14656 int rc = 0; 14657 14658 switch (ctl->cmd) { 14659 case DRV_CTL_CTXTBL_WR_CMD: { 14660 u32 index = ctl->data.io.offset; 14661 dma_addr_t addr = ctl->data.io.dma_addr; 14662 14663 bnx2x_ilt_wr(bp, index, addr); 14664 break; 14665 } 14666 14667 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: { 14668 int count = ctl->data.credit.credit_count; 14669 14670 bnx2x_cnic_sp_post(bp, count); 14671 break; 14672 } 14673 14674 /* rtnl_lock is held. */ 14675 case DRV_CTL_START_L2_CMD: { 14676 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14677 unsigned long sp_bits = 0; 14678 14679 /* Configure the iSCSI classification object */ 14680 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, 14681 cp->iscsi_l2_client_id, 14682 cp->iscsi_l2_cid, BP_FUNC(bp), 14683 bnx2x_sp(bp, mac_rdata), 14684 bnx2x_sp_mapping(bp, mac_rdata), 14685 BNX2X_FILTER_MAC_PENDING, 14686 &bp->sp_state, BNX2X_OBJ_TYPE_RX, 14687 &bp->macs_pool); 14688 14689 /* Set iSCSI MAC address */ 14690 rc = bnx2x_set_iscsi_eth_mac_addr(bp); 14691 if (rc) 14692 break; 14693 14694 barrier(); 14695 14696 /* Start accepting on iSCSI L2 ring */ 14697 14698 netif_addr_lock_bh(dev); 14699 bnx2x_set_iscsi_eth_rx_mode(bp, true); 14700 netif_addr_unlock_bh(dev); 14701 14702 /* bits to wait on */ 14703 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 14704 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits); 14705 14706 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 14707 BNX2X_ERR("rx_mode completion timed out!\n"); 14708 14709 break; 14710 } 14711 14712 /* rtnl_lock is held. */ 14713 case DRV_CTL_STOP_L2_CMD: { 14714 unsigned long sp_bits = 0; 14715 14716 /* Stop accepting on iSCSI L2 ring */ 14717 netif_addr_lock_bh(dev); 14718 bnx2x_set_iscsi_eth_rx_mode(bp, false); 14719 netif_addr_unlock_bh(dev); 14720 14721 /* bits to wait on */ 14722 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits); 14723 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits); 14724 14725 if (!bnx2x_wait_sp_comp(bp, sp_bits)) 14726 BNX2X_ERR("rx_mode completion timed out!\n"); 14727 14728 barrier(); 14729 14730 /* Unset iSCSI L2 MAC */ 14731 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, 14732 BNX2X_ISCSI_ETH_MAC, true); 14733 break; 14734 } 14735 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: { 14736 int count = ctl->data.credit.credit_count; 14737 14738 smp_mb__before_atomic(); 14739 atomic_add(count, &bp->cq_spq_left); 14740 smp_mb__after_atomic(); 14741 break; 14742 } 14743 case DRV_CTL_ULP_REGISTER_CMD: { 14744 int ulp_type = ctl->data.register_data.ulp_type; 14745 14746 if (CHIP_IS_E3(bp)) { 14747 int idx = BP_FW_MB_IDX(bp); 14748 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 14749 int path = BP_PATH(bp); 14750 int port = BP_PORT(bp); 14751 int i; 14752 u32 scratch_offset; 14753 u32 *host_addr; 14754 14755 /* first write capability to shmem2 */ 14756 if (ulp_type == CNIC_ULP_ISCSI) 14757 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 14758 else if (ulp_type == CNIC_ULP_FCOE) 14759 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 14760 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 14761 14762 if ((ulp_type != CNIC_ULP_FCOE) || 14763 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || 14764 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) 14765 break; 14766 14767 /* if reached here - should write fcoe capabilities */ 14768 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); 14769 if (!scratch_offset) 14770 break; 14771 scratch_offset += offsetof(struct glob_ncsi_oem_data, 14772 fcoe_features[path][port]); 14773 host_addr = (u32 *) &(ctl->data.register_data. 14774 fcoe_features); 14775 for (i = 0; i < sizeof(struct fcoe_capabilities); 14776 i += 4) 14777 REG_WR(bp, scratch_offset + i, 14778 *(host_addr + i/4)); 14779 } 14780 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14781 break; 14782 } 14783 14784 case DRV_CTL_ULP_UNREGISTER_CMD: { 14785 int ulp_type = ctl->data.ulp_type; 14786 14787 if (CHIP_IS_E3(bp)) { 14788 int idx = BP_FW_MB_IDX(bp); 14789 u32 cap; 14790 14791 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); 14792 if (ulp_type == CNIC_ULP_ISCSI) 14793 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI; 14794 else if (ulp_type == CNIC_ULP_FCOE) 14795 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE; 14796 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); 14797 } 14798 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14799 break; 14800 } 14801 14802 default: 14803 BNX2X_ERR("unknown command %x\n", ctl->cmd); 14804 rc = -EINVAL; 14805 } 14806 14807 /* For storage-only interfaces, change driver state */ 14808 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) { 14809 switch (ctl->drv_state) { 14810 case DRV_NOP: 14811 break; 14812 case DRV_ACTIVE: 14813 bnx2x_set_os_driver_state(bp, 14814 OS_DRIVER_STATE_ACTIVE); 14815 break; 14816 case DRV_INACTIVE: 14817 bnx2x_set_os_driver_state(bp, 14818 OS_DRIVER_STATE_DISABLED); 14819 break; 14820 case DRV_UNLOADED: 14821 bnx2x_set_os_driver_state(bp, 14822 OS_DRIVER_STATE_NOT_LOADED); 14823 break; 14824 default: 14825 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state); 14826 } 14827 } 14828 14829 return rc; 14830} 14831 14832static int bnx2x_get_fc_npiv(struct net_device *dev, 14833 struct cnic_fc_npiv_tbl *cnic_tbl) 14834{ 14835 struct bnx2x *bp = netdev_priv(dev); 14836 struct bdn_fc_npiv_tbl *tbl = NULL; 14837 u32 offset, entries; 14838 int rc = -EINVAL; 14839 int i; 14840 14841 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0])) 14842 goto out; 14843 14844 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n"); 14845 14846 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL); 14847 if (!tbl) { 14848 BNX2X_ERR("Failed to allocate fc_npiv table\n"); 14849 goto out; 14850 } 14851 14852 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]); 14853 if (!offset) { 14854 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n"); 14855 goto out; 14856 } 14857 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset); 14858 14859 /* Read the table contents from nvram */ 14860 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) { 14861 BNX2X_ERR("Failed to read FC-NPIV table\n"); 14862 goto out; 14863 } 14864 14865 /* Since bnx2x_nvram_read() returns data in be32, we need to convert 14866 * the number of entries back to cpu endianness. 14867 */ 14868 entries = tbl->fc_npiv_cfg.num_of_npiv; 14869 entries = (__force u32)be32_to_cpu((__force __be32)entries); 14870 tbl->fc_npiv_cfg.num_of_npiv = entries; 14871 14872 if (!tbl->fc_npiv_cfg.num_of_npiv) { 14873 DP(BNX2X_MSG_MCP, 14874 "No FC-NPIV table [valid, simply not present]\n"); 14875 goto out; 14876 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) { 14877 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n", 14878 tbl->fc_npiv_cfg.num_of_npiv); 14879 goto out; 14880 } else { 14881 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n", 14882 tbl->fc_npiv_cfg.num_of_npiv); 14883 } 14884 14885 /* Copy the data into cnic-provided struct */ 14886 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv; 14887 for (i = 0; i < cnic_tbl->count; i++) { 14888 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8); 14889 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8); 14890 } 14891 14892 rc = 0; 14893out: 14894 kfree(tbl); 14895 return rc; 14896} 14897 14898void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) 14899{ 14900 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14901 14902 if (bp->flags & USING_MSIX_FLAG) { 14903 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX; 14904 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX; 14905 cp->irq_arr[0].vector = bp->msix_table[1].vector; 14906 } else { 14907 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX; 14908 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX; 14909 } 14910 if (!CHIP_IS_E1x(bp)) 14911 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; 14912 else 14913 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; 14914 14915 cp->irq_arr[0].status_blk_map = bp->cnic_sb_mapping; 14916 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); 14917 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); 14918 cp->irq_arr[1].status_blk = bp->def_status_blk; 14919 cp->irq_arr[1].status_blk_map = bp->def_status_blk_mapping; 14920 cp->irq_arr[1].status_blk_num = DEF_SB_ID; 14921 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID; 14922 14923 cp->num_irq = 2; 14924} 14925 14926void bnx2x_setup_cnic_info(struct bnx2x *bp) 14927{ 14928 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14929 14930 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 14931 bnx2x_cid_ilt_lines(bp); 14932 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 14933 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 14934 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 14935 14936 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n", 14937 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, 14938 cp->iscsi_l2_cid); 14939 14940 if (NO_ISCSI_OOO(bp)) 14941 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 14942} 14943 14944static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops, 14945 void *data) 14946{ 14947 struct bnx2x *bp = netdev_priv(dev); 14948 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 14949 int rc; 14950 14951 DP(NETIF_MSG_IFUP, "Register_cnic called\n"); 14952 14953 if (ops == NULL) { 14954 BNX2X_ERR("NULL ops received\n"); 14955 return -EINVAL; 14956 } 14957 14958 if (!CNIC_SUPPORT(bp)) { 14959 BNX2X_ERR("Can't register CNIC when not supported\n"); 14960 return -EOPNOTSUPP; 14961 } 14962 14963 if (!CNIC_LOADED(bp)) { 14964 rc = bnx2x_load_cnic(bp); 14965 if (rc) { 14966 BNX2X_ERR("CNIC-related load failed\n"); 14967 return rc; 14968 } 14969 } 14970 14971 bp->cnic_enabled = true; 14972 14973 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 14974 if (!bp->cnic_kwq) 14975 return -ENOMEM; 14976 14977 bp->cnic_kwq_cons = bp->cnic_kwq; 14978 bp->cnic_kwq_prod = bp->cnic_kwq; 14979 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; 14980 14981 bp->cnic_spq_pending = 0; 14982 bp->cnic_kwq_pending = 0; 14983 14984 bp->cnic_data = data; 14985 14986 cp->num_irq = 0; 14987 cp->drv_state |= CNIC_DRV_STATE_REGD; 14988 cp->iro_arr = bp->iro_arr; 14989 14990 bnx2x_setup_cnic_irq_info(bp); 14991 14992 rcu_assign_pointer(bp->cnic_ops, ops); 14993 14994 /* Schedule driver to read CNIC driver versions */ 14995 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); 14996 14997 return 0; 14998} 14999 15000static int bnx2x_unregister_cnic(struct net_device *dev) 15001{ 15002 struct bnx2x *bp = netdev_priv(dev); 15003 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 15004 15005 mutex_lock(&bp->cnic_mutex); 15006 cp->drv_state = 0; 15007 RCU_INIT_POINTER(bp->cnic_ops, NULL); 15008 mutex_unlock(&bp->cnic_mutex); 15009 synchronize_rcu(); 15010 bp->cnic_enabled = false; 15011 kfree(bp->cnic_kwq); 15012 bp->cnic_kwq = NULL; 15013 15014 return 0; 15015} 15016 15017static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev) 15018{ 15019 struct bnx2x *bp = netdev_priv(dev); 15020 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 15021 15022 /* If both iSCSI and FCoE are disabled - return NULL in 15023 * order to indicate CNIC that it should not try to work 15024 * with this device. 15025 */ 15026 if (NO_ISCSI(bp) && NO_FCOE(bp)) 15027 return NULL; 15028 15029 cp->drv_owner = THIS_MODULE; 15030 cp->chip_id = CHIP_ID(bp); 15031 cp->pdev = bp->pdev; 15032 cp->io_base = bp->regview; 15033 cp->io_base2 = bp->doorbells; 15034 cp->max_kwqe_pending = 8; 15035 cp->ctx_blk_size = CDU_ILT_PAGE_SZ; 15036 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + 15037 bnx2x_cid_ilt_lines(bp); 15038 cp->ctx_tbl_len = CNIC_ILT_LINES; 15039 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; 15040 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue; 15041 cp->drv_ctl = bnx2x_drv_ctl; 15042 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv; 15043 cp->drv_register_cnic = bnx2x_register_cnic; 15044 cp->drv_unregister_cnic = bnx2x_unregister_cnic; 15045 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); 15046 cp->iscsi_l2_client_id = 15047 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); 15048 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); 15049 15050 if (NO_ISCSI_OOO(bp)) 15051 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO; 15052 15053 if (NO_ISCSI(bp)) 15054 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI; 15055 15056 if (NO_FCOE(bp)) 15057 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 15058 15059 BNX2X_DEV_INFO( 15060 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n", 15061 cp->ctx_blk_size, 15062 cp->ctx_tbl_offset, 15063 cp->ctx_tbl_len, 15064 cp->starting_cid); 15065 return cp; 15066} 15067 15068static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 15069{ 15070 struct bnx2x *bp = fp->bp; 15071 u32 offset = BAR_USTRORM_INTMEM; 15072 15073 if (IS_VF(bp)) 15074 return bnx2x_vf_ustorm_prods_offset(bp, fp); 15075 else if (!CHIP_IS_E1x(bp)) 15076 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 15077 else 15078 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 15079 15080 return offset; 15081} 15082 15083/* called only on E1H or E2. 15084 * When pretending to be PF, the pretend value is the function number 0...7 15085 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 15086 * combination 15087 */ 15088int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) 15089{ 15090 u32 pretend_reg; 15091 15092 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) 15093 return -1; 15094 15095 /* get my own pretend register */ 15096 pretend_reg = bnx2x_get_pretend_reg(bp); 15097 REG_WR(bp, pretend_reg, pretend_func_val); 15098 REG_RD(bp, pretend_reg); 15099 return 0; 15100} 15101 15102static void bnx2x_ptp_task(struct work_struct *work) 15103{ 15104 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); 15105 int port = BP_PORT(bp); 15106 u32 val_seq; 15107 u64 timestamp, ns; 15108 struct skb_shared_hwtstamps shhwtstamps; 15109 bool bail = true; 15110 int i; 15111 15112 /* FW may take a while to complete timestamping; try a bit and if it's 15113 * still not complete, may indicate an error state - bail out then. 15114 */ 15115 for (i = 0; i < 10; i++) { 15116 /* Read Tx timestamp registers */ 15117 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15118 NIG_REG_P0_TLLH_PTP_BUF_SEQID); 15119 if (val_seq & 0x10000) { 15120 bail = false; 15121 break; 15122 } 15123 msleep(1 << i); 15124 } 15125 15126 if (!bail) { 15127 /* There is a valid timestamp value */ 15128 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : 15129 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB); 15130 timestamp <<= 32; 15131 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : 15132 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB); 15133 /* Reset timestamp register to allow new timestamp */ 15134 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15135 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); 15136 ns = timecounter_cyc2time(&bp->timecounter, timestamp); 15137 15138 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 15139 shhwtstamps.hwtstamp = ns_to_ktime(ns); 15140 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); 15141 15142 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", 15143 timestamp, ns); 15144 } else { 15145 DP(BNX2X_MSG_PTP, 15146 "Tx timestamp is not recorded (register read=%u)\n", 15147 val_seq); 15148 bp->eth_stats.ptp_skip_tx_ts++; 15149 } 15150 15151 dev_kfree_skb_any(bp->ptp_tx_skb); 15152 bp->ptp_tx_skb = NULL; 15153} 15154 15155void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) 15156{ 15157 int port = BP_PORT(bp); 15158 u64 timestamp, ns; 15159 15160 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : 15161 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB); 15162 timestamp <<= 32; 15163 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : 15164 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB); 15165 15166 /* Reset timestamp register to allow new timestamp */ 15167 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : 15168 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); 15169 15170 ns = timecounter_cyc2time(&bp->timecounter, timestamp); 15171 15172 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 15173 15174 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", 15175 timestamp, ns); 15176} 15177 15178/* Read the PHC */ 15179static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc) 15180{ 15181 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); 15182 int port = BP_PORT(bp); 15183 u32 wb_data[2]; 15184 u64 phc_cycles; 15185 15186 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : 15187 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2); 15188 phc_cycles = wb_data[1]; 15189 phc_cycles = (phc_cycles << 32) + wb_data[0]; 15190 15191 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles); 15192 15193 return phc_cycles; 15194} 15195 15196static void bnx2x_init_cyclecounter(struct bnx2x *bp) 15197{ 15198 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); 15199 bp->cyclecounter.read = bnx2x_cyclecounter_read; 15200 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); 15201 bp->cyclecounter.shift = 0; 15202 bp->cyclecounter.mult = 1; 15203} 15204 15205static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) 15206{ 15207 struct bnx2x_func_state_params func_params = {NULL}; 15208 struct bnx2x_func_set_timesync_params *set_timesync_params = 15209 &func_params.params.set_timesync; 15210 15211 /* Prepare parameters for function state transitions */ 15212 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 15213 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags); 15214 15215 func_params.f_obj = &bp->func_obj; 15216 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC; 15217 15218 /* Function parameters */ 15219 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET; 15220 set_timesync_params->offset_cmd = TS_OFFSET_KEEP; 15221 15222 return bnx2x_func_state_change(bp, &func_params); 15223} 15224 15225static int bnx2x_enable_ptp_packets(struct bnx2x *bp) 15226{ 15227 struct bnx2x_queue_state_params q_params; 15228 int rc, i; 15229 15230 /* send queue update ramrod to enable PTP packets */ 15231 memset(&q_params, 0, sizeof(q_params)); 15232 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 15233 q_params.cmd = BNX2X_Q_CMD_UPDATE; 15234 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, 15235 &q_params.params.update.update_flags); 15236 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS, 15237 &q_params.params.update.update_flags); 15238 15239 /* send the ramrod on all the queues of the PF */ 15240 for_each_eth_queue(bp, i) { 15241 struct bnx2x_fastpath *fp = &bp->fp[i]; 15242 15243 /* Set the appropriate Queue object */ 15244 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; 15245 15246 /* Update the Queue state */ 15247 rc = bnx2x_queue_state_change(bp, &q_params); 15248 if (rc) { 15249 BNX2X_ERR("Failed to enable PTP packets\n"); 15250 return rc; 15251 } 15252 } 15253 15254 return 0; 15255} 15256 15257#define BNX2X_P2P_DETECT_PARAM_MASK 0x5F5 15258#define BNX2X_P2P_DETECT_RULE_MASK 0x3DBB 15259#define BNX2X_PTP_TX_ON_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) 15260#define BNX2X_PTP_TX_ON_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) 15261#define BNX2X_PTP_V1_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EE) 15262#define BNX2X_PTP_V1_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FFE) 15263#define BNX2X_PTP_V2_L4_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x7EA) 15264#define BNX2X_PTP_V2_L4_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3FEE) 15265#define BNX2X_PTP_V2_L2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6BF) 15266#define BNX2X_PTP_V2_L2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EFF) 15267#define BNX2X_PTP_V2_PARAM_MASK (BNX2X_P2P_DETECT_PARAM_MASK & 0x6AA) 15268#define BNX2X_PTP_V2_RULE_MASK (BNX2X_P2P_DETECT_RULE_MASK & 0x3EEE) 15269 15270int bnx2x_configure_ptp_filters(struct bnx2x *bp) 15271{ 15272 int port = BP_PORT(bp); 15273 u32 param, rule; 15274 int rc; 15275 15276 if (!bp->hwtstamp_ioctl_called) 15277 return 0; 15278 15279 param = port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 15280 NIG_REG_P0_TLLH_PTP_PARAM_MASK; 15281 rule = port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 15282 NIG_REG_P0_TLLH_PTP_RULE_MASK; 15283 switch (bp->tx_type) { 15284 case HWTSTAMP_TX_ON: 15285 bp->flags |= TX_TIMESTAMPING_EN; 15286 REG_WR(bp, param, BNX2X_PTP_TX_ON_PARAM_MASK); 15287 REG_WR(bp, rule, BNX2X_PTP_TX_ON_RULE_MASK); 15288 break; 15289 case HWTSTAMP_TX_ONESTEP_SYNC: 15290 case HWTSTAMP_TX_ONESTEP_P2P: 15291 BNX2X_ERR("One-step timestamping is not supported\n"); 15292 return -ERANGE; 15293 } 15294 15295 param = port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 15296 NIG_REG_P0_LLH_PTP_PARAM_MASK; 15297 rule = port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 15298 NIG_REG_P0_LLH_PTP_RULE_MASK; 15299 switch (bp->rx_filter) { 15300 case HWTSTAMP_FILTER_NONE: 15301 break; 15302 case HWTSTAMP_FILTER_ALL: 15303 case HWTSTAMP_FILTER_SOME: 15304 case HWTSTAMP_FILTER_NTP_ALL: 15305 bp->rx_filter = HWTSTAMP_FILTER_NONE; 15306 break; 15307 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 15308 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 15309 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 15310 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 15311 /* Initialize PTP detection for UDP/IPv4 events */ 15312 REG_WR(bp, param, BNX2X_PTP_V1_L4_PARAM_MASK); 15313 REG_WR(bp, rule, BNX2X_PTP_V1_L4_RULE_MASK); 15314 break; 15315 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 15316 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 15317 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 15318 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 15319 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ 15320 REG_WR(bp, param, BNX2X_PTP_V2_L4_PARAM_MASK); 15321 REG_WR(bp, rule, BNX2X_PTP_V2_L4_RULE_MASK); 15322 break; 15323 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 15324 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 15325 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 15326 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 15327 /* Initialize PTP detection L2 events */ 15328 REG_WR(bp, param, BNX2X_PTP_V2_L2_PARAM_MASK); 15329 REG_WR(bp, rule, BNX2X_PTP_V2_L2_RULE_MASK); 15330 15331 break; 15332 case HWTSTAMP_FILTER_PTP_V2_EVENT: 15333 case HWTSTAMP_FILTER_PTP_V2_SYNC: 15334 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 15335 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 15336 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ 15337 REG_WR(bp, param, BNX2X_PTP_V2_PARAM_MASK); 15338 REG_WR(bp, rule, BNX2X_PTP_V2_RULE_MASK); 15339 break; 15340 } 15341 15342 /* Indicate to FW that this PF expects recorded PTP packets */ 15343 rc = bnx2x_enable_ptp_packets(bp); 15344 if (rc) 15345 return rc; 15346 15347 /* Enable sending PTP packets to host */ 15348 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 15349 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1); 15350 15351 return 0; 15352} 15353 15354static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) 15355{ 15356 struct hwtstamp_config config; 15357 int rc; 15358 15359 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n"); 15360 15361 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 15362 return -EFAULT; 15363 15364 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n", 15365 config.tx_type, config.rx_filter); 15366 15367 bp->hwtstamp_ioctl_called = true; 15368 bp->tx_type = config.tx_type; 15369 bp->rx_filter = config.rx_filter; 15370 15371 rc = bnx2x_configure_ptp_filters(bp); 15372 if (rc) 15373 return rc; 15374 15375 config.rx_filter = bp->rx_filter; 15376 15377 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 15378 -EFAULT : 0; 15379} 15380 15381/* Configures HW for PTP */ 15382static int bnx2x_configure_ptp(struct bnx2x *bp) 15383{ 15384 int rc, port = BP_PORT(bp); 15385 u32 wb_data[2]; 15386 15387 /* Reset PTP event detection rules - will be configured in the IOCTL */ 15388 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : 15389 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF); 15390 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : 15391 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF); 15392 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : 15393 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF); 15394 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : 15395 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF); 15396 15397 /* Disable PTP packets to host - will be configured in the IOCTL*/ 15398 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : 15399 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0); 15400 15401 /* Enable the PTP feature */ 15402 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : 15403 NIG_REG_P0_PTP_EN, 0x3F); 15404 15405 /* Enable the free-running counter */ 15406 wb_data[0] = 0; 15407 wb_data[1] = 0; 15408 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); 15409 15410 /* Reset drift register (offset register is not reset) */ 15411 rc = bnx2x_send_reset_timesync_ramrod(bp); 15412 if (rc) { 15413 BNX2X_ERR("Failed to reset PHC drift register\n"); 15414 return -EFAULT; 15415 } 15416 15417 /* Reset possibly old timestamps */ 15418 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : 15419 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000); 15420 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : 15421 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000); 15422 15423 return 0; 15424} 15425 15426/* Called during load, to initialize PTP-related stuff */ 15427void bnx2x_init_ptp(struct bnx2x *bp) 15428{ 15429 int rc; 15430 15431 /* Configure PTP in HW */ 15432 rc = bnx2x_configure_ptp(bp); 15433 if (rc) { 15434 BNX2X_ERR("Stopping PTP initialization\n"); 15435 return; 15436 } 15437 15438 /* Init work queue for Tx timestamping */ 15439 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); 15440 15441 /* Init cyclecounter and timecounter. This is done only in the first 15442 * load. If done in every load, PTP application will fail when doing 15443 * unload / load (e.g. MTU change) while it is running. 15444 */ 15445 if (!bp->timecounter_init_done) { 15446 bnx2x_init_cyclecounter(bp); 15447 timecounter_init(&bp->timecounter, &bp->cyclecounter, 15448 ktime_to_ns(ktime_get_real())); 15449 bp->timecounter_init_done = true; 15450 } 15451 15452 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n"); 15453} 15454