| /linux-master/sound/soc/codecs/ |
| H A D | cs35l45.h | 457 .reg_offset = (CS35L45_ ## _reg) - CS35L45_IRQ1_EINT_1, \
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| /linux-master/drivers/mfd/ |
| H A D | mc13xxx-core.c | 443 mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vpe_v6_1.c | 67 base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0];
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| H A D | mmhub_v1_0.c | 716 if (mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
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| H A D | amdgpu_amdkfd_gfx_v9.c | 1103 uint32_t *reg_offset,
1120 *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);
1100 kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, uint32_t *reg_data) argument
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| H A D | gfx_v9_4.c | 837 if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||
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| H A D | amdgpu_amdkfd_gfx_v10.c | 1027 uint32_t *reg_offset,
1044 *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2);
1024 kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, uint32_t *reg_data) argument
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| /linux-master/drivers/crypto/hisilicon/hpre/ |
| H A D | hpre_main.c | 347 .reg_offset = HPRE_DFX_BASE,
350 .reg_offset = HPRE_DFX_COMMON1,
353 .reg_offset = HPRE_DFX_COMMON2,
356 .reg_offset = HPRE_DFX_CORE,
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| /linux-master/drivers/net/ipa/ |
| H A D | ipa_cmd.c | 304 offset = reg_offset(reg);
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| H A D | ipa_table.c | 379 ipa_cmd_register_write_add(trans, reg_offset(reg), val, val, false);
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| /linux-master/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu-qcom.c | 492 .reg_offset = qcom_smmu_impl0_reg_offset,
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| /linux-master/drivers/accel/habanalabs/gaudi2/ |
| H A D | gaudi2.c | 7716 u32 reg_base, reg_offset, reg_val = 0; local
7724 reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION3_GENERAL);
7725 WREG32(reg_base + reg_offset, reg_val);
7727 reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION4_HBM0_FW);
7728 WREG32(reg_base + reg_offset, reg_val);
7730 reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION5_HBM1_GC_DATA);
7731 WREG32(reg_base + reg_offset, reg_val);
7733 reg_offset = ARC_REGION_CFG_OFFSET(ARC_REGION6_HBM2_GC_DATA);
7734 WREG32(reg_base + reg_offset, reg_val);
7736 reg_offset
[all...] |
| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | si.c | 2474 u32 reg_offset, split_equal_to_row_size; local
2489 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2490 tile[reg_offset] = 0;
2703 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2704 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
[all...] |
| /linux-master/drivers/pinctrl/samsung/ |
| H A D | pinctrl-exynos-arm.c | 27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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| H A D | pinctrl-exynos.c | 234 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
267 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
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| /linux-master/drivers/leds/ |
| H A D | leds-bd2802.c | 149 u8 reg_offset)
151 return reg_offset + bd2802_get_base_offset(id, color);
148 bd2802_get_reg_addr(enum led_ids id, enum led_colors color, u8 reg_offset) argument
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| /linux-master/arch/arm64/kvm/vgic/ |
| H A D | vgic-mmio.c | 826 if (offset < region->reg_offset)
829 if (offset >= region->reg_offset + region->len)
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| H A D | vgic-mmio-v3.c | 577 .reg_offset = off, \
584 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \
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| /linux-master/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_82575.c | 2070 u32 reg_val, reg_offset; local
2074 reg_offset = E1000_DTXSWC;
2078 reg_offset = E1000_TXSWC;
2084 reg_val = rd32(reg_offset);
2096 wr32(reg_offset, reg_val);
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| /linux-master/drivers/pinctrl/ |
| H A D | pinctrl-st.c | 1091 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4; local
1098 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1102 reg_offset += 4;
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| /linux-master/drivers/net/wireless/mediatek/mt76/mt7603/ |
| H A D | mac.c | 52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | local
67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
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| /linux-master/drivers/net/ethernet/qlogic/qed/ |
| H A D | qed_dbg_hsi.h | 390 u16 reg_offset; /* offset of this rules registers in the idle check member in struct:dbg_idle_chk_rule
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| /linux-master/drivers/net/wireless/mediatek/mt76/mt7615/ |
| H A D | mac.c | 142 u32 val, reg_offset; local
175 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
177 mt76_wr(dev, MT_TMAC_CDTR, cck + reg_offset);
178 mt76_wr(dev, MT_TMAC_ODTR, ofdm + reg_offset);
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| /linux-master/drivers/net/wireless/ath/ath5k/ |
| H A D | base.c | 231 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) argument
234 return ath5k_hw_reg_read(ah, reg_offset);
237 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) argument
240 ath5k_hw_reg_write(ah, val, reg_offset);
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| /linux-master/drivers/crypto/marvell/octeontx2/ |
| H A D | otx2_cptpf_mbox.c | 492 rsp_rd_wr->reg_offset, rsp_rd_wr->is_write,
|