/linux-master/drivers/gpu/drm/i915/display/ |
H A D | hsw_ips.c | 47 intel_de_write(i915, IPS_CTL, val); 82 intel_de_write(i915, IPS_CTL, 0);
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H A D | intel_ddi.c | 139 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 141 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 171 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 173 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 443 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 465 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 605 intel_de_write(dev_priv, 609 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 629 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 641 intel_de_write(dev_pri [all...] |
H A D | intel_dpll.c | 1837 intel_de_write(dev_priv, FP0(pipe), hw_state->fp0); 1838 intel_de_write(dev_priv, FP1(pipe), hw_state->fp1); 1845 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS); 1846 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1853 intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); 1860 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1865 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 1994 intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); 2015 intel_de_write(dev_priv, DPLL(pipe), 2023 intel_de_write(dev_pri [all...] |
H A D | intel_dvo.c | 311 intel_de_write(i915, DVO_SRCDIM(port), 314 intel_de_write(i915, DVO(port), dvo_val); 465 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
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H A D | intel_display.c | 466 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), 517 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); 761 intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); 1608 intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), 1644 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), 1862 intel_de_write(dev_priv, PFIT_PGM_RATIOS, 1864 intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); 1868 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); 2102 intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); 2105 intel_de_write(dev_pri [all...] |
H A D | intel_audio.c | 307 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); 309 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); 366 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 375 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 526 intel_de_write(i915, AUD_CONFIG_BE, val); 901 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 902 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 977 intel_de_write(i915, AUD_FREQ_CNTRL,
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H A D | intel_overlay.c | 216 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0); 218 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 1334 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1335 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1336 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1337 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1338 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1339 intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
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H A D | intel_dpll_mgr.c | 568 intel_de_write(i915, PCH_FP0(id), hw_state->fp0); 569 intel_de_write(i915, PCH_FP1(id), hw_state->fp1); 571 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); 582 intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); 592 intel_de_write(i915, PCH_DPLL(id), 0); 695 intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll); 706 intel_de_write(i915, SPLL_CTL, hw_state->spll); 1384 intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1); 1385 intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2); 2089 intel_de_write(i91 [all...] |
H A D | intel_snps_phy.c | 83 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); 1835 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); 1836 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); 1837 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); 1838 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); 1839 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); 1840 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); 1841 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); 1861 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
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H A D | intel_cdclk.c | 606 intel_de_write(dev_priv, GCI_CONTROL, 609 intel_de_write(dev_priv, GCI_CONTROL, 875 intel_de_write(dev_priv, CDCLK_FREQ, 1151 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1156 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1164 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1167 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1171 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1698 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1715 intel_de_write(dev_pri [all...] |
H A D | intel_lvds.c | 217 intel_de_write(dev_priv, PP_CONTROL(0), val); 219 intel_de_write(dev_priv, PP_ON_DELAYS(0), 224 intel_de_write(dev_priv, PP_OFF_DELAYS(0), 228 intel_de_write(dev_priv, PP_DIVISOR(0), 308 intel_de_write(i915, lvds_encoder->reg, temp);
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H A D | intel_dp_aux.c | 333 intel_de_write(i915, ch_data[i >> 2], 338 intel_de_write(i915, ch_ctl, send_ctl); 343 intel_de_write(i915, ch_ctl,
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H A D | intel_display_power.c | 1254 intel_de_write(dev_priv, D_COMP_BDW, val); 1278 intel_de_write(dev_priv, LCPLL_CTL, val); 1288 intel_de_write(dev_priv, LCPLL_CTL, val); 1331 intel_de_write(dev_priv, LCPLL_CTL, val); 1342 intel_de_write(dev_priv, LCPLL_CTL, val); 1619 intel_de_write(dev_priv, BW_BUDDY_CTL(i), 1623 intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), 1702 intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
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H A D | intel_psr.c | 606 intel_de_write(dev_priv, 622 intel_de_write(dev_priv, psr_aux_ctl_reg(dev_priv, cpu_transcoder), 923 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0); 933 intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val); 935 intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); 1786 intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder), 1793 intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder), 1808 intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl); 1871 intel_de_write(dev_priv, psr_debug_reg(dev_priv, cpu_transcoder), mask); 2246 intel_de_write(dev_pri [all...] |
H A D | intel_de.h | 87 #define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__) macro
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H A D | intel_pmdemand.c | 536 intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0), 542 intel_de_write(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
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H A D | intel_dmc.c | 405 intel_de_write(i915, ctl_reg, 410 intel_de_write(i915, htp_reg, 0); 597 intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
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H A D | intel_tc.c | 422 intel_de_write(i915, PORT_TX_DFLEXDPMLE1(tc->phy_fia), val); 566 intel_de_write(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia), val); 1027 intel_de_write(i915, reg, val); 1071 intel_de_write(i915, reg, val);
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H A D | intel_dp.c | 4371 intel_de_write(dev_priv, reg, val); 4784 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 4792 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4797 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4803 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4815 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); 4817 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); 4819 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); 4820 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 4832 intel_de_write(dev_pri [all...] |
H A D | i9xx_plane.c | 1087 intel_de_write(dev_priv, DSPSURF(i9xx_plane), base); 1089 intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);
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H A D | intel_gmbus.c | 211 intel_de_write(i915, GMBUS0(i915), 0); 212 intel_de_write(i915, GMBUS4(i915), 0);
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H A D | intel_dpio_phy.c | 287 intel_de_write(i915, reg_group, val); 466 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
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H A D | intel_cx0_phy.c | 134 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), 208 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), 278 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), 2769 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 2869 intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val); 2888 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 2929 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); 2990 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
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H A D | intel_display_irq.c | 994 intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir); 997 intel_de_write(i915, SDEIIR, *pch_iir); 1000 intel_de_write(i915, PICAINTERRUPT_IER, pica_ier);
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H A D | intel_dp_mst.c | 932 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state), 1221 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), 1223 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
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