/linux-master/drivers/gpu/drm/gma500/ |
H A D | psb_device.c | 204 .dpll = DPLL_A, 228 .dpll = DPLL_B,
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H A D | oaktrail_device.c | 144 p->dpll = PSB_RVDC32(MRST_DPLL_A); 261 PSB_WVDC32(p->dpll, MRST_DPLL_A); 402 .dpll = MRST_DPLL_A, 426 .dpll = DPLL_B,
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H A D | cdv_device.c | 503 .dpll = DPLL_A, 528 .dpll = DPLL_B,
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H A D | psb_drv.h | 225 u32 dpll; member in struct:psb_offset 259 u32 dpll; member in struct:psb_pipe
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_display_core.h | 123 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 125 * dpll, because on some platforms plls share registers. 298 const struct intel_dpll_funcs *dpll; member in struct:intel_display::__anon558 545 struct intel_dpll dpll; member in struct:intel_display
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H A D | intel_pch_refclk.c | 464 dev_priv->display.dpll.pch_ssc_use = 0; 468 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); 473 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); 478 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); 481 if (dev_priv->display.dpll.pch_ssc_use)
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H A D | intel_dvo.c | 420 u32 dpll[I915_MAX_PIPES]; local 459 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE); 465 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]);
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H A D | g4x_dp.c | 30 static const struct dpll g4x_dpll[] = { 35 static const struct dpll pch_dpll[] = { 40 static const struct dpll vlv_dpll[] = { 45 static const struct dpll chv_dpll[] = { 51 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 60 const struct dpll *divisor = NULL; 80 pipe_config->dpll = divisor[i];
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H A D | icl_dsi.c | 606 mutex_lock(&dev_priv->display.dpll.lock); 612 mutex_unlock(&dev_priv->display.dpll.lock); 622 mutex_lock(&dev_priv->display.dpll.lock); 628 mutex_unlock(&dev_priv->display.dpll.lock); 658 mutex_lock(&dev_priv->display.dpll.lock); 674 mutex_unlock(&dev_priv->display.dpll.lock);
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H A D | intel_display_types.h | 667 struct dpll { struct 1158 /* Settings for the intel dpll used on pretty much everything but 1160 struct dpll dpll; member in struct:intel_crtc_state 1162 /* Selected dpll when shared or NULL. */ 1165 /* Actual register state of the dpll, for shared dpll cross-checking. */ 1202 * Frequence the dpll for the port should run at. Differs from the
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H A D | intel_ddi.c | 1482 mutex_lock(&i915->display.dpll.lock); 1492 mutex_unlock(&i915->display.dpll.lock); 1498 mutex_lock(&i915->display.dpll.lock); 1502 mutex_unlock(&i915->display.dpll.lock); 1777 mutex_lock(&i915->display.dpll.lock); 1782 mutex_unlock(&i915->display.dpll.lock); 1791 mutex_lock(&i915->display.dpll.lock); 1796 mutex_unlock(&i915->display.dpll.lock); 1881 mutex_lock(&i915->display.dpll.lock); 1889 mutex_unlock(&i915->display.dpll [all...] |
/linux-master/drivers/ata/ |
H A D | pata_hpt37x.c | 948 int dpll, adjust; local 951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; 953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; 981 if (dpll == 3) 987 MHz[clock_slot], MHz[dpll]);
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/linux-master/drivers/dpll/ |
H A D | dpll_nl.c | 3 /* Documentation/netlink/specs/dpll.yaml */ 11 #include <uapi/linux/dpll.h> 76 /* Ops table for dpll */
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/linux-master/arch/arm/mach-omap2/ |
H A D | sram242x.S | 252 /* set new dpll dividers _after_ in bypass */ 254 str r0, [r4] @ set dpll ctrl val 267 beq pend @ jump over dpll relock 272 orr r8, r7, #0x3 @ val for lock dpll
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H A D | sram243x.S | 252 /* set new dpll dividers _after_ in bypass */ 254 str r0, [r4] @ set dpll ctrl val 267 beq pend @ jump over dpll relock 272 orr r8, r7, #0x3 @ val for lock dpll
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/linux-master/drivers/clk/rockchip/ |
H A D | clk-rk3036.c | 21 apll, dpll, gpll, enumerator in enum:rk3036_plls 120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; 123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" }; 124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" }; 126 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; 139 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 183 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 198 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
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H A D | clk-rk3228.c | 19 apll, dpll, cpll, gpll, enumerator in enum:rk3228_plls 171 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), 222 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 235 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
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H A D | clk-rk3128.c | 18 apll, dpll, cpll, gpll, enumerator in enum:rk3128_plls 161 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 209 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
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H A D | clk-rk3188.c | 19 apll, cpll, dpll, gpll, enumerator in enum:rk3188_plls 200 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" }; 212 PNAME(mux_mac_p) = { "gpll", "dpll" }; 218 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 229 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
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H A D | clk-px30.c | 18 apll, dpll, cpll, npll, apll_b_h, apll_b_l, enumerator in enum:px30_plls 188 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 332 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
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/linux-master/drivers/ptp/ |
H A D | ptp_ocp.c | 26 #include <linux/dpll.h> 378 struct dpll_device *dpll; member in struct:ptp_ocp 4497 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv, argument 4510 const struct dpll_device *dpll, void *priv, 4527 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv, argument 4536 const struct dpll_device *dpll, 4551 const struct dpll_device *dpll, 4570 const struct dpll_device *dpll, 4592 const struct dpll_device *dpll, 4637 dpll_device_change_ntf(bp->dpll); 4509 ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv, const struct dpll_device *dpll, void *priv, enum dpll_pin_state *state, struct netlink_ext_ack *extack) argument 4534 ptp_ocp_dpll_direction_get(const struct dpll_pin *pin, void *pin_priv, const struct dpll_device *dpll, void *priv, enum dpll_pin_direction *direction, struct netlink_ext_ack *extack) argument 4549 ptp_ocp_dpll_direction_set(const struct dpll_pin *pin, void *pin_priv, const struct dpll_device *dpll, void *dpll_priv, enum dpll_pin_direction direction, struct netlink_ext_ack *extack) argument 4568 ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin, void *pin_priv, const struct dpll_device *dpll, void *dpll_priv, u64 frequency, struct netlink_ext_ack *extack) argument 4590 ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin, void *pin_priv, const struct dpll_device *dpll, void *dpll_priv, u64 *frequency, struct netlink_ext_ack *extack) argument [all...] |
H A D | ptp_clockmatrix.c | 352 u8 dpll = 0; local 360 err = read_sys_dpll_status(idtcm, &dpll); 365 dpll &= DPLL_SYS_STATE_MASK; 368 dpll == DPLL_STATE_LOCKED) { 370 } else if (dpll == DPLL_STATE_FREERUN || 371 dpll == DPLL_STATE_HOLDOVER || 372 dpll == DPLL_STATE_OPEN_LOOP) { 374 "No wait state: DPLL_SYS_STATE %d", dpll); 383 LOCK_TIMEOUT_MS, apll, dpll);
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/linux-master/drivers/ |
H A D | Makefile | 193 obj-$(CONFIG_DPLL) += dpll/
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/linux-master/drivers/net/ethernet/intel/ice/ |
H A D | ice_ptp_hw.h | 6 #include <linux/dpll.h>
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/linux-master/drivers/net/ethernet/mellanox/mlx5/core/ |
H A D | Makefile | 133 mlx5_dpll-y := dpll.o
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