1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2022 Intel Corporation 4 */ 5 6#ifndef __INTEL_DISPLAY_CORE_H__ 7#define __INTEL_DISPLAY_CORE_H__ 8 9#include <linux/list.h> 10#include <linux/llist.h> 11#include <linux/mutex.h> 12#include <linux/types.h> 13#include <linux/wait.h> 14#include <linux/workqueue.h> 15 16#include <drm/drm_connector.h> 17#include <drm/drm_modeset_lock.h> 18 19#include "intel_cdclk.h" 20#include "intel_display_device.h" 21#include "intel_display_limits.h" 22#include "intel_display_params.h" 23#include "intel_display_power.h" 24#include "intel_dpll_mgr.h" 25#include "intel_fbc.h" 26#include "intel_global_state.h" 27#include "intel_gmbus.h" 28#include "intel_opregion.h" 29#include "intel_wm_types.h" 30 31struct task_struct; 32 33struct drm_i915_private; 34struct drm_property; 35struct drm_property_blob; 36struct i915_audio_component; 37struct i915_hdcp_arbiter; 38struct intel_atomic_state; 39struct intel_audio_funcs; 40struct intel_cdclk_funcs; 41struct intel_cdclk_vals; 42struct intel_color_funcs; 43struct intel_crtc; 44struct intel_crtc_state; 45struct intel_dmc; 46struct intel_dpll_funcs; 47struct intel_dpll_mgr; 48struct intel_fbdev; 49struct intel_fdi_funcs; 50struct intel_hotplug_funcs; 51struct intel_initial_plane_config; 52struct intel_opregion; 53struct intel_overlay; 54 55/* Amount of SAGV/QGV points, BSpec precisely defines this */ 56#define I915_NUM_QGV_POINTS 8 57 58/* Amount of PSF GV points, BSpec precisely defines this */ 59#define I915_NUM_PSF_GV_POINTS 3 60 61struct intel_display_funcs { 62 /* 63 * Returns the active state of the crtc, and if the crtc is active, 64 * fills out the pipe-config with the hw state. 65 */ 66 bool (*get_pipe_config)(struct intel_crtc *, 67 struct intel_crtc_state *); 68 void (*get_initial_plane_config)(struct intel_crtc *, 69 struct intel_initial_plane_config *); 70 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc, 71 const struct intel_initial_plane_config *plane_config); 72 void (*crtc_enable)(struct intel_atomic_state *state, 73 struct intel_crtc *crtc); 74 void (*crtc_disable)(struct intel_atomic_state *state, 75 struct intel_crtc *crtc); 76 void (*commit_modeset_enables)(struct intel_atomic_state *state); 77}; 78 79/* functions used for watermark calcs for display. */ 80struct intel_wm_funcs { 81 /* update_wm is for legacy wm management */ 82 void (*update_wm)(struct drm_i915_private *dev_priv); 83 int (*compute_pipe_wm)(struct intel_atomic_state *state, 84 struct intel_crtc *crtc); 85 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 86 struct intel_crtc *crtc); 87 void (*initial_watermarks)(struct intel_atomic_state *state, 88 struct intel_crtc *crtc); 89 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 90 struct intel_crtc *crtc); 91 void (*optimize_watermarks)(struct intel_atomic_state *state, 92 struct intel_crtc *crtc); 93 int (*compute_global_watermarks)(struct intel_atomic_state *state); 94 void (*get_hw_state)(struct drm_i915_private *i915); 95}; 96 97struct intel_audio_state { 98 struct intel_encoder *encoder; 99 u8 eld[MAX_ELD_BYTES]; 100}; 101 102struct intel_audio { 103 /* hda/i915 audio component */ 104 struct i915_audio_component *component; 105 bool component_registered; 106 /* mutex for audio/video sync */ 107 struct mutex mutex; 108 int power_refcount; 109 u32 freq_cntrl; 110 111 /* current audio state for the audio component hooks */ 112 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 113 114 /* necessary resource sharing with HDMI LPE audio driver. */ 115 struct { 116 struct platform_device *platdev; 117 int irq; 118 } lpe; 119}; 120 121/* 122 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 123 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 124 * dpll, because on some platforms plls share registers. 125 */ 126struct intel_dpll { 127 struct mutex lock; 128 129 int num_shared_dpll; 130 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 131 const struct intel_dpll_mgr *mgr; 132 133 struct { 134 int nssc; 135 int ssc; 136 } ref_clks; 137 138 /* 139 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 140 */ 141 u8 pch_ssc_use; 142}; 143 144struct intel_frontbuffer_tracking { 145 spinlock_t lock; 146 147 /* 148 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 149 * scheduled flips. 150 */ 151 unsigned busy_bits; 152 unsigned flip_bits; 153}; 154 155struct intel_hotplug { 156 struct delayed_work hotplug_work; 157 158 const u32 *hpd, *pch_hpd; 159 160 struct { 161 unsigned long last_jiffies; 162 int count; 163 enum { 164 HPD_ENABLED = 0, 165 HPD_DISABLED = 1, 166 HPD_MARK_DISABLED = 2 167 } state; 168 } stats[HPD_NUM_PINS]; 169 u32 event_bits; 170 u32 retry_bits; 171 struct delayed_work reenable_work; 172 173 u32 long_port_mask; 174 u32 short_port_mask; 175 struct work_struct dig_port_work; 176 177 struct work_struct poll_init_work; 178 bool poll_enabled; 179 180 /* 181 * Queuing of hotplug_work, reenable_work and poll_init_work is 182 * enabled. Protected by drm_i915_private::irq_lock. 183 */ 184 bool detection_work_enabled; 185 186 unsigned int hpd_storm_threshold; 187 /* Whether or not to count short HPD IRQs in HPD storms */ 188 u8 hpd_short_storm_enabled; 189 190 /* Last state reported by oob_hotplug_event for each encoder */ 191 unsigned long oob_hotplug_last_state; 192 193 /* 194 * if we get a HPD irq from DP and a HPD irq from non-DP 195 * the non-DP HPD could block the workqueue on a mode config 196 * mutex getting, that userspace may have taken. However 197 * userspace is waiting on the DP workqueue to run which is 198 * blocked behind the non-DP one. 199 */ 200 struct workqueue_struct *dp_wq; 201 202 /* 203 * Flag to track if long HPDs need not to be processed 204 * 205 * Some panels generate long HPDs while keep connected to the port. 206 * This can cause issues with CI tests results. In CI systems we 207 * don't expect to disconnect the panels and could ignore the long 208 * HPDs generated from the faulty panels. This flag can be used as 209 * cue to ignore the long HPDs and can be set / unset using debugfs. 210 */ 211 bool ignore_long_hpd; 212}; 213 214struct intel_vbt_data { 215 /* bdb version */ 216 u16 version; 217 218 /* Feature bits */ 219 unsigned int int_tv_support:1; 220 unsigned int int_crt_support:1; 221 unsigned int lvds_use_ssc:1; 222 unsigned int int_lvds_support:1; 223 unsigned int display_clock_mode:1; 224 unsigned int fdi_rx_polarity_inverted:1; 225 int lvds_ssc_freq; 226 enum drm_panel_orientation orientation; 227 228 bool override_afc_startup; 229 u8 override_afc_startup_val; 230 231 int crt_ddc_pin; 232 233 struct list_head display_devices; 234 struct list_head bdb_blocks; 235 236 struct sdvo_device_mapping { 237 u8 initialized; 238 u8 dvo_port; 239 u8 slave_addr; 240 u8 dvo_wiring; 241 u8 i2c_pin; 242 u8 ddc_pin; 243 } sdvo_mappings[2]; 244}; 245 246struct intel_wm { 247 /* 248 * Raw watermark latency values: 249 * in 0.1us units for WM0, 250 * in 0.5us units for WM1+. 251 */ 252 /* primary */ 253 u16 pri_latency[5]; 254 /* sprite */ 255 u16 spr_latency[5]; 256 /* cursor */ 257 u16 cur_latency[5]; 258 /* 259 * Raw watermark memory latency values 260 * for SKL for all 8 levels 261 * in 1us units. 262 */ 263 u16 skl_latency[8]; 264 265 /* current hardware state */ 266 union { 267 struct ilk_wm_values hw; 268 struct vlv_wm_values vlv; 269 struct g4x_wm_values g4x; 270 }; 271 272 u8 num_levels; 273 274 /* 275 * Should be held around atomic WM register writing; also 276 * protects * intel_crtc->wm.active and 277 * crtc_state->wm.need_postvbl_update. 278 */ 279 struct mutex wm_mutex; 280 281 bool ipc_enabled; 282}; 283 284struct intel_display { 285 /* Display functions */ 286 struct { 287 /* Top level crtc-ish functions */ 288 const struct intel_display_funcs *display; 289 290 /* Display CDCLK functions */ 291 const struct intel_cdclk_funcs *cdclk; 292 293 /* Display pll funcs */ 294 const struct intel_dpll_funcs *dpll; 295 296 /* irq display functions */ 297 const struct intel_hotplug_funcs *hotplug; 298 299 /* pm display functions */ 300 const struct intel_wm_funcs *wm; 301 302 /* fdi display functions */ 303 const struct intel_fdi_funcs *fdi; 304 305 /* Display internal color functions */ 306 const struct intel_color_funcs *color; 307 308 /* Display internal audio functions */ 309 const struct intel_audio_funcs *audio; 310 } funcs; 311 312 struct { 313 bool any_task_allowed; 314 struct task_struct *allowed_task; 315 } access; 316 317 struct { 318 /* backlight registers and fields in struct intel_panel */ 319 struct mutex lock; 320 } backlight; 321 322 struct { 323 struct intel_global_obj obj; 324 325 struct intel_bw_info { 326 /* for each QGV point */ 327 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 328 /* for each PSF GV point */ 329 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 330 /* Peak BW for each QGV point */ 331 unsigned int peakbw[I915_NUM_QGV_POINTS]; 332 u8 num_qgv_points; 333 u8 num_psf_gv_points; 334 u8 num_planes; 335 } max[6]; 336 } bw; 337 338 struct { 339 /* The current hardware cdclk configuration */ 340 struct intel_cdclk_config hw; 341 342 /* cdclk, divider, and ratio table from bspec */ 343 const struct intel_cdclk_vals *table; 344 345 struct intel_global_obj obj; 346 347 unsigned int max_cdclk_freq; 348 } cdclk; 349 350 struct { 351 struct drm_property_blob *glk_linear_degamma_lut; 352 } color; 353 354 struct { 355 /* The current hardware dbuf configuration */ 356 u8 enabled_slices; 357 358 struct intel_global_obj obj; 359 } dbuf; 360 361 struct { 362 /* 363 * dkl.phy_lock protects against concurrent access of the 364 * Dekel TypeC PHYs. 365 */ 366 spinlock_t phy_lock; 367 } dkl; 368 369 struct { 370 struct intel_dmc *dmc; 371 intel_wakeref_t wakeref; 372 } dmc; 373 374 struct { 375 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 376 u32 mmio_base; 377 } dsi; 378 379 struct { 380 /* list of fbdev register on this device */ 381 struct intel_fbdev *fbdev; 382 struct work_struct suspend_work; 383 } fbdev; 384 385 struct { 386 unsigned int pll_freq; 387 u32 rx_config; 388 } fdi; 389 390 struct { 391 struct list_head obj_list; 392 } global; 393 394 struct { 395 /* 396 * Base address of where the gmbus and gpio blocks are located 397 * (either on PCH or on SoC for platforms without PCH). 398 */ 399 u32 mmio_base; 400 401 /* 402 * gmbus.mutex protects against concurrent usage of the single 403 * hw gmbus controller on different i2c buses. 404 */ 405 struct mutex mutex; 406 407 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 408 409 wait_queue_head_t wait_queue; 410 } gmbus; 411 412 struct { 413 struct i915_hdcp_arbiter *arbiter; 414 bool comp_added; 415 416 /* 417 * HDCP message struct for allocation of memory which can be 418 * reused when sending message to gsc cs. 419 * this is only populated post Meteorlake 420 */ 421 struct intel_hdcp_gsc_message *hdcp_message; 422 /* Mutex to protect the above hdcp related values. */ 423 struct mutex hdcp_mutex; 424 } hdcp; 425 426 struct { 427 /* 428 * HTI (aka HDPORT) state read during initial hw readout. Most 429 * platforms don't have HTI, so this will just stay 0. Those 430 * that do will use this later to figure out which PLLs and PHYs 431 * are unavailable for driver usage. 432 */ 433 u32 state; 434 } hti; 435 436 struct { 437 /* Access with DISPLAY_INFO() */ 438 const struct intel_display_device_info *__device_info; 439 440 /* Access with DISPLAY_RUNTIME_INFO() */ 441 struct intel_display_runtime_info __runtime_info; 442 } info; 443 444 struct { 445 bool false_color; 446 } ips; 447 448 struct { 449 wait_queue_head_t waitqueue; 450 451 /* mutex to protect pmdemand programming sequence */ 452 struct mutex lock; 453 454 struct intel_global_obj obj; 455 } pmdemand; 456 457 struct { 458 struct i915_power_domains domains; 459 460 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 461 u32 chv_phy_control; 462 463 /* perform PHY state sanity checks? */ 464 bool chv_phy_assert[2]; 465 } power; 466 467 struct { 468 u32 mmio_base; 469 470 /* protects panel power sequencer state */ 471 struct mutex mutex; 472 } pps; 473 474 struct { 475 struct drm_property *broadcast_rgb; 476 struct drm_property *force_audio; 477 } properties; 478 479 struct { 480 unsigned long mask; 481 } quirks; 482 483 struct { 484 /* restore state for suspend/resume and display reset */ 485 struct drm_atomic_state *modeset_state; 486 struct drm_modeset_acquire_ctx reset_ctx; 487 } restore; 488 489 struct { 490 enum { 491 I915_SAGV_UNKNOWN = 0, 492 I915_SAGV_DISABLED, 493 I915_SAGV_ENABLED, 494 I915_SAGV_NOT_CONTROLLED 495 } status; 496 497 u32 block_time_us; 498 } sagv; 499 500 struct { 501 /* 502 * DG2: Mask of PHYs that were not calibrated by the firmware 503 * and should not be used. 504 */ 505 u8 phy_failed_calibration; 506 } snps; 507 508 struct { 509 /* 510 * Shadows for CHV DPLL_MD regs to keep the state 511 * checker somewhat working in the presence hardware 512 * crappiness (can't read out DPLL_MD for pipes B & C). 513 */ 514 u32 chv_dpll_md[I915_MAX_PIPES]; 515 u32 bxt_phy_grc; 516 } state; 517 518 struct { 519 /* ordered wq for modesets */ 520 struct workqueue_struct *modeset; 521 522 /* unbound hipri wq for page flips/plane updates */ 523 struct workqueue_struct *flip; 524 } wq; 525 526 /* Grouping using named structs. Keep sorted. */ 527 struct drm_dp_tunnel_mgr *dp_tunnel_mgr; 528 struct intel_audio audio; 529 struct intel_dpll dpll; 530 struct intel_fbc *fbc[I915_MAX_FBCS]; 531 struct intel_frontbuffer_tracking fb_tracking; 532 struct intel_hotplug hotplug; 533 struct intel_opregion *opregion; 534 struct intel_overlay *overlay; 535 struct intel_display_params params; 536 struct intel_vbt_data vbt; 537 struct intel_wm wm; 538}; 539 540#endif /* __INTEL_DISPLAY_CORE_H__ */ 541