Searched refs:clocks (Results 51 - 75 of 123) sorted by relevance

12345

/linux-master/drivers/bus/
H A Dti-sysc.c114 * @clocks: clocks used by the interconnect target module
115 * @clock_roles: clock role names for the found clocks
116 * @nr_clocks: number of clocks used by the interconnect target module
146 struct clk **clocks; member in struct:sysc
407 if (!ddata->clocks[i]) {
419 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
420 if (IS_ERR(ddata->clocks[index])) {
422 name, PTR_ERR(ddata->clocks[index]));
424 return PTR_ERR(ddata->clocks[inde
[all...]
/linux-master/sound/soc/tegra/
H A Dtegra30_ahub.c48 clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks);
56 * the driver supports right now, so we'll just treat the two clocks as one
72 ret = clk_bulk_prepare_enable(ahub->nclocks, ahub->clocks);
98 clk_bulk_disable_unprepare(ahub->nclocks, ahub->clocks);
537 ahub->clocks[ahub->nclocks++].id = "apbif";
538 ahub->clocks[ahub->nclocks++].id = "d_audio";
540 ret = devm_clk_bulk_get(&pdev->dev, ahub->nclocks, ahub->clocks);
/linux-master/drivers/memory/tegra/
H A Dtegra20.c451 u32 clocks, count0, count1, control_0, control_1; local
459 * and set clocks counter saturation limit to maximum.
472 clocks = mc_readl(mc, MC_STAT_EMC_CLOCKS);
473 clocks = max(clocks / 100 / MC_FX_FRAC_SCALE, 1u);
475 stat->gather0.result = DIV_ROUND_UP(count0, clocks);
476 stat->gather1.result = DIV_ROUND_UP(count1, clocks);
/linux-master/drivers/staging/media/rkvdec/
H A Drkvdec.h94 struct clk_bulk_data *clocks; member in struct:rkvdec_dev
H A Drkvdec.c1015 rkvdec->clocks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(rkvdec_clk_names),
1016 sizeof(*rkvdec->clocks), GFP_KERNEL);
1017 if (!rkvdec->clocks)
1021 rkvdec->clocks[i].id = rkvdec_clk_names[i];
1024 rkvdec->clocks);
1085 rkvdec->clocks);
1093 rkvdec->clocks);
/linux-master/drivers/staging/vc04_services/vchiq-mmal/
H A Dmmal-vchiq.h90 u32 clocks; /* Number of clock ports */ member in struct:vchiq_mmal_component
/linux-master/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-core.h105 * @clocks: JPEG IP clock(s)
123 struct clk *clocks[JPEG_MAX_CLOCKS]; member in struct:s5p_jpeg
/linux-master/drivers/clk/ti/
H A Dclk.c162 * ti_dt_clocks_register - register DT alias clocks during boot
163 * @oclks: list of clocks to register
166 * default, DT clocks are found based on their clock-output-names
278 * once all the other clocks have been initialized.
356 /* Other clocks that may or may not have ti,bit-shift property */
370 * dropped once all the composite clocks use a clksel node with a
408 * mapping from clocks node to the memory map index. All the clocks
410 * clocks will access their memory maps based on the node layout.
416 struct device_node *clocks; local
[all...]
H A Dclkctrl.c45 struct list_head clocks; member in struct:omap_clkctrl_provider
236 list_for_each_entry(iter, &provider->clocks, node) {
322 list_add(&clkctrl_clk->node, &provider->clocks);
641 INIT_LIST_HEAD(&provider->clocks);
643 /* Generate clocks */
700 list_add(&clkctrl_clk->node, &provider->clocks);
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_kms.h100 struct clk_bulk_data *clocks; member in struct:dpu_kms
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Daldebaran_ppt.c551 struct pp_clock_levels_with_latency *clocks,
556 clocks->num_levels = min_t(uint32_t,
560 for (i = 0; i < clocks->num_levels; i++) {
561 clocks->data[i].clocks_in_khz =
563 clocks->data[i].latency_in_us = 0;
740 struct pp_clock_levels_with_latency clocks; local
775 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
777 display_levels = (clocks.num_levels == 1) ? 1 : 2;
807 aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
818 aldebaran_get_clk_table(smu, &clocks, single_dpm_tabl
550 aldebaran_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct smu_13_0_dpm_table *dpm_table) argument
[all...]
/linux-master/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c90 * @clocks: fimc clocks.
107 struct clk *clocks[FIMC_CLKS_MAX]; member in struct:fimc_context
1174 if (IS_ERR(ctx->clocks[i]))
1176 clk_put(ctx->clocks[i]);
1177 ctx->clocks[i] = ERR_PTR(-EINVAL);
1188 ctx->clocks[i] = ERR_PTR(-EINVAL);
1196 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1197 if (IS_ERR(ctx->clocks[i])) {
1198 ret = PTR_ERR(ctx->clocks[
[all...]
H A Dexynos_drm_gsc.c108 struct clk *clocks[GSC_MAX_CLOCKS]; member in struct:gsc_context
121 * @clk_names: names of clocks needed by this variant
122 * @num_clocks: the number of clocks needed by this variant
1265 ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
1266 if (IS_ERR(ctx->clocks[i])) {
1269 return PTR_ERR(ctx->clocks[i]);
1329 clk_disable_unprepare(ctx->clocks[i]);
1342 ret = clk_prepare_enable(ctx->clocks[i]);
1345 clk_disable_unprepare(ctx->clocks[i]);
/linux-master/sound/soc/ti/
H A Dj721e-evm.c460 struct j721e_audio_clocks *clocks, char *prefix)
466 clocks->target = devm_clk_get(dev, prefix);
467 if (IS_ERR(clocks->target))
468 return dev_err_probe(dev, PTR_ERR(clocks->target),
483 clocks->parent[J721E_CLK_PARENT_48000] = parent;
500 clocks->parent[J721E_CLK_PARENT_44100] = parent;
505 if (!clocks->parent[J721E_CLK_PARENT_44100] &&
506 !clocks->parent[J721E_CLK_PARENT_48000]) {
459 j721e_get_clocks(struct device *dev, struct j721e_audio_clocks *clocks, char *prefix) argument
/linux-master/drivers/media/platform/verisilicon/
H A Drockchip_vpu_hw.c432 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
439 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
440 clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
447 clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);
454 clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
674 * Despite this variant has separate clocks for decoder and encoder,
H A Dimx8m_vpu_hw.c58 ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);
60 dev_err(vpu->dev, "Failed to enable clocks\n");
72 clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);
/linux-master/sound/soc/hisilicon/
H A Dhi6210-i2s.c37 int clocks; member in struct:hi6210_i2s
102 for (n = 0; n < i2s->clocks; n++) {
177 for (n = 0; n < i2s->clocks; n++)
576 i2s->clocks++;
581 i2s->clocks++;
/linux-master/drivers/gpu/drm/amd/pm/inc/
H A Damdgpu_dpm.h63 /* UVD clocks */
66 /* VCE clocks */
568 struct amd_pp_clocks *clocks);
570 struct amd_pp_simple_clock_info *clocks);
573 struct pp_clock_levels_with_latency *clocks);
576 struct pp_clock_levels_with_voltage *clocks);
582 struct amd_pp_clock_info *clocks);
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c319 // notify DMCUB of latest clocks
323 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
324 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
326 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
327 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
604 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) argument
610 if (clocks[i] > max)
611 max = clocks[i];
662 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
671 /* Now update clocks w
[all...]
/linux-master/drivers/i2c/busses/
H A Di2c-tegra.c235 * @clocks: array of I2C controller clocks
236 * @nclocks: number of clocks in the array
272 struct clk_bulk_data clocks[2]; member in struct:tegra_i2c_dev
1684 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1687 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1690 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1693 i2c_dev->clocks);
1697 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1701 i2c_dev->div_clk = i2c_dev->clocks[
[all...]
H A Di2c-qcom-cci.c132 struct clk_bulk_data *clocks; member in struct:cci
472 return clk_bulk_prepare_enable(cci->nclocks, cci->clocks);
477 clk_bulk_disable_unprepare(cci->nclocks, cci->clocks);
590 ret = devm_clk_bulk_get_all(dev, &cci->clocks);
592 return dev_err_probe(dev, ret, "failed to get clocks\n");
594 return dev_err_probe(dev, -EINVAL, "not enough clocks in DT\n");
599 if (!strcmp(cci->clocks[i].id, "cci")) {
600 cci_clk_rate = clk_get_rate(cci->clocks[i].clk);
/linux-master/include/soc/tegra/
H A Dbpmp.h95 struct tegra_bpmp_clk **clocks; member in struct:tegra_bpmp
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.h74 struct clk_bulk_data *clocks; member in struct:a6xx_gmu
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c717 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; local
719 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ;
720 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000;
721 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000;
722 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000;
723 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
724 clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
725 clocks->fclk_p_state_change_support = true;
726 clocks->p_state_change_support = true;
728 clocks
[all...]
/linux-master/drivers/clk/renesas/
H A DMakefile34 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o

Completed in 646 milliseconds

12345