/linux-master/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_scaler.c | 46 struct clk *clock[SCALER_MAX_CLK]; member in struct:scaler_context 517 scaler->clock[i] = devm_clk_get(dev, 519 if (IS_ERR(scaler->clock[i])) { 520 dev_err(dev, "failed to get clock\n"); 521 return PTR_ERR(scaler->clock[i]); 565 clk_fun(scaler->clock[i]);
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_panel.c | 113 mode->clock != preferred_mode->clock; 155 /* pick the fixed_mode that has the highest clock */ 157 if (fixed_mode->clock > best_mode->clock) 245 DIV_ROUND_CLOSEST(adjusted_mode->clock * 1000,
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/linux-master/drivers/media/platform/st/sti/bdisp/ |
H A D | bdisp-v4l2.c | 1207 int ret = clk_enable(bdisp->clock); 1221 clk_disable(bdisp->clock); 1274 if (!IS_ERR(bdisp->clock)) 1275 clk_unprepare(bdisp->clock); 1323 bdisp->clock = devm_clk_get(dev, BDISP_NAME); 1324 if (IS_ERR(bdisp->clock)) { 1325 dev_err(dev, "failed to get clock\n"); 1326 ret = PTR_ERR(bdisp->clock); 1330 ret = clk_prepare(bdisp->clock); 1332 dev_err(dev, "clock prepar [all...] |
/linux-master/drivers/gpu/drm/renesas/rcar-du/ |
H A D | rcar_du_crtc.c | 187 * Compute the input clock rate and internal divisor values to obtain 188 * the clock rate closest to the target frequency. 210 unsigned long mode_clock = mode->clock * 1000; 224 * system clock, and have no internal clock divider. 247 * Use the external LVDS or DSI PLL output as the dot clock when 249 * this clock routing option. We use the clock directly in that 256 rcar_du_escr_divider(rcrtc->clock, mode_clock, 262 dev_dbg(rcrtc->dev->dev, "mode clock [all...] |
/linux-master/drivers/media/platform/samsung/exynos-gsc/ |
H A D | gsc-core.c | 1147 gsc->clock[i] = devm_clk_get(dev, drv_data->clk_names[i]); 1148 if (IS_ERR(gsc->clock[i])) { 1149 dev_err(dev, "failed to get clock: %s\n", 1151 return PTR_ERR(gsc->clock[i]); 1156 ret = clk_prepare_enable(gsc->clock[i]); 1158 dev_err(dev, "clock prepare failed for clock: %s\n", 1161 clk_disable_unprepare(gsc->clock[i]); 1199 clk_disable_unprepare(gsc->clock[i]); 1217 clk_disable_unprepare(gsc->clock[ [all...] |
/linux-master/drivers/mmc/host/ |
H A D | sdhci-of-dwcmshc.c | 130 /* PHY clock pad settings */ 185 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 249 return pltfm_host->clock; 556 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) argument 567 if (clock == 0) { 568 /* Disable interface clock at initial state. */ 569 sdhci_set_clock(host, clock); 574 if (clock <= 400000) 575 clock = 375000; 577 err = clk_set_rate(pltfm_host->clk, clock); [all...] |
H A D | sdhci-esdhc-imx.c | 175 * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 186 /* The IP lost clock rate in PM_RUNTIME */ 233 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ 439 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 911 return pltfm_host->clock; 918 return pltfm_host->clock / 256 / 16; 922 unsigned int clock) 926 unsigned int host_clock = pltfm_host->clock; 940 if (clock 921 esdhc_pltfm_set_clock(struct sdhci_host *host, unsigned int clock) argument [all...] |
H A D | sdhci.c | 209 host->clock = 0; 379 /* force clock reconfiguration */ 380 host->clock = 0; 914 if (host->clock && data->timeout_clks) { 918 * data->timeout_clks is in units of clock cycles. 919 * host->clock is in Hz. target_timeout is in us. 923 if (do_div(val, host->clock)) 949 freq = mmc->actual_clock ? : host->clock; 1886 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, argument 1919 <= clock) 2032 sdhci_set_clock(struct sdhci_host *host, unsigned int clock) argument [all...] |
H A D | sdhci-of-at91.c | 36 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ 62 static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) argument 69 * There is no requirement to disable the internal clock before 70 * changing the SD clock configuration. Moreover, disabling the 71 * internal clock, changing the configuration and re-enabling the 72 * internal clock causes some bugs. It can prevent to get the internal 73 * clock stable flag ready and an unexpected switch to the base clock 80 if (clock == 0) 83 clk = sdhci_calc_clk(host, clock, [all...] |
H A D | sdhci-brcmstb.c | 127 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) argument 133 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 136 if (clock == 0) 329 "Failed to get and enable clock from Device Tree\n"); 358 * Automatic clock gating does not work for SD cards that may 387 /* Change the base clock frequency if the DT property exists */ 388 if (device_property_read_u32(&pdev->dev, "clock-frequency", 402 /* set improved clock rate */
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | fiji_smumgr.c | 183 /* Enable clock */ 354 uint32_t clock, uint32_t *voltage, uint32_t *mvdd) 362 /* clock - voltage dependency table is empty table */ 368 if (dep_table->entries[i].clk >= clock) { 856 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) 870 /* get the engine clock dividers for this clock value */ 871 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); 902 uint32_t vco_freq = clock * dividers.uc_pll_post_div; 926 sclk->SclkFrequency = clock; 352 fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, uint32_t clock, uint32_t *voltage, uint32_t *mvdd) argument 855 fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) argument 936 fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level) argument 1142 fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk) argument 1161 fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level) argument [all...] |
/linux-master/drivers/media/platform/ti/omap3isp/ |
H A D | isp.c | 1270 /* AEWB and AF share the same clock. */ 1322 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]); 1324 dev_err(isp->dev, "failed to enable cam_ick clock\n"); 1327 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ); 1332 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]); 1334 dev_err(isp->dev, "failed to enable cam_mclk clock\n"); 1337 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]); 1342 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]); 1344 dev_err(isp->dev, "failed to enable csi2_fck clock\n"); 1350 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCL [all...] |
/linux-master/drivers/mmc/core/ |
H A D | core.c | 688 if (card->host->ios.clock) 690 (card->host->ios.clock / 1000); 892 pr_debug("%s: clock %uHz busmode %u powermode %u cs %u Vdd %u " 894 mmc_hostname(host), ios->clock, ios->bus_mode, 911 * Sets the host clock to the highest possible frequency that 921 host->ios.clock = hz; 1184 u32 clock; local 1187 * During a signal voltage level switch, the clock must be gated 1190 clock = host->ios.clock; [all...] |
/linux-master/drivers/scsi/ |
H A D | 53c700.c | 66 * support for odd clock speeds which constrain SDTR negotiations. 719 if(hostdata->clock > 75) { 720 printk(KERN_ERR "53c700: Clock speed %dMHz is too high: 75Mhz is the maximum this chip can be driven at\n", hostdata->clock); 721 /* do the best we can, but the async clock will be out 726 hostdata->sync_clock = hostdata->clock/2; 727 } else if(hostdata->clock > 50 && hostdata->clock <= 75) { 732 hostdata->sync_clock = hostdata->clock*2; 735 } else if(hostdata->clock > 37 && hostdata->clock < [all...] |
/linux-master/drivers/net/ethernet/intel/ice/ |
H A D | ice_ptp.c | 364 * ice_ptp_read_src_clk_reg - Read the source clock register 367 * the system clock. Will be ignored if NULL is given. 672 * In cases where the PTP hardware clock was directly adjusted, some 675 * timestamps when the clock is adjusted. Then this function will discard 954 * This should be called when the PTP clock is modified such as after a set 968 * ice_ptp_flush_all_tx_tracker - Flush all timestamp trackers on this clock 971 * Called by the clock owner to flush all the Tx timestamp trackers associated 972 * with the clock. 1185 * ice_ptp_write_adj - Adjust PHC clock time atomically 1204 * value is used to define the nominal clock tic 2957 struct ptp_clock *clock; local [all...] |
/linux-master/drivers/gpu/drm/nouveau/dispnv04/ |
H A D | tvnv17.c | 213 mode->clock = tv_norm->tv_enc_mode.vrefresh * 218 mode->clock *= 2; 313 if (mode->clock > 400000) 330 if (mode->clock > 70000) 355 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock; 357 adjusted_mode->clock = 90000;
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/linux-master/drivers/pinctrl/ |
H A D | pinctrl-microchip-sgpio.c | 122 u32 clock; member in struct:sgpio_priv 934 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 937 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 938 priv->clock = 12500000; 939 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 940 dev_err(dev, "Invalid frequency %d\n", priv->clock); 978 val = max(2U, div_clock / priv->clock);
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/linux-master/drivers/net/ethernet/wangxun/txgbe/ |
H A D | txgbe_phy.c | 57 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 570 struct clk_lookup *clock; local 581 clock = clkdev_create(clk, NULL, clk_name); 582 if (!clock) { 588 txgbe->clock = clock; 756 wx_err(wx, "failed to register clock: %d\n", ret); 777 clkdev_drop(txgbe->clock); 799 clkdev_drop(txgbe->clock);
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/linux-master/drivers/gpu/drm/tiny/ |
H A D | simpledrm.c | 279 * up simplefb, and the clock definitions in the device tree. Chances are 303 struct clk *clock; local 320 clock = of_clk_get(of_node, i); 321 if (IS_ERR(clock)) { 322 ret = PTR_ERR(clock); 325 drm_err(dev, "clock %u not found: %d\n", i, ret); 328 ret = clk_prepare_enable(clock); 330 drm_err(dev, "failed to enable clock %u: %d\n", 332 clk_put(clock); 335 sdev->clks[i] = clock; [all...] |
/linux-master/drivers/memstick/host/ |
H A D | rtsx_usb_ms.c | 35 unsigned int clock; member in struct:rtsx_usb_ms 556 unsigned int clock = 0; local 592 clock = 19000000; 599 clock = 39000000; 612 err = rtsx_usb_switch_clock(ucr, clock, 615 dev_dbg(ms_dev(host), "switch clock failed\n"); 620 host->clock = clock;
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/linux-master/drivers/ata/ |
H A D | sata_sx4.c | 1216 u32 clock = 0; local 1239 clock cycle. 1253 clock = (ticks / 300000); 1255 clock, clock); 1257 clock = (clock * 33); 1259 clock, clock); 1262 fparam = (1400000 / clock) [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/ |
H A D | amd_powerplay.c | 716 pr_debug("force clock level is for dpm manual mode only.\n"); 1159 struct pp_display_clock_request *clock) 1163 if (!hwmgr || !hwmgr->pm_en || !clock) 1166 return phm_display_clock_voltage_request(hwmgr, clock); 1315 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock) argument 1327 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); 1332 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock) argument 1344 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); 1349 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) argument 1361 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); 1158 pp_display_clock_voltage_request(void *handle, struct pp_display_clock_request *clock) argument [all...] |
/linux-master/sound/soc/codecs/ |
H A D | wm8753.c | 797 /* codec hifi mclk (after PLL) clock divider coefficients */ 978 /* clock inversion */ 1104 /* clock inversion */ 1192 u16 clock; local 1195 clock = snd_soc_component_read(component, WM8753_CLOCK) & 0xfffb; 1196 snd_soc_component_write(component, WM8753_CLOCK, clock); 1210 u16 clock; local 1213 clock = snd_soc_component_read(component, WM8753_CLOCK) & 0xfffb; 1214 snd_soc_component_write(component, WM8753_CLOCK, clock); 1222 u16 clock; local [all...] |
/linux-master/drivers/gpu/drm/radeon/ |
H A D | r600_hdmi.c | 316 struct radeon_crtc *crtc, unsigned int clock) 332 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 336 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); 315 r600_hdmi_audio_set_dto(struct radeon_device *rdev, struct radeon_crtc *crtc, unsigned int clock) argument
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/linux-master/drivers/gpu/drm/stm/ |
H A D | dw_mipi_dsi-stm.c | 254 pll_out_khz = mode->clock * bpp / lanes; 341 pll_out_khz = mode->clock * bpp / lanes; 374 target_px_clock_hz = mode->clock * 1000; 376 * Filter modes according to the clock value, particularly useful for 411 * resync with LTDC pixel clock. 476 dev_err_probe(dev, ret, "Unable to get pll reference clock\n"); 489 DRM_ERROR("Unable to get peripheral clock: %d\n", ret);
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