Searched refs:Shl (Results 51 - 75 of 102) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp1323 case Instruction::Shl: {
2814 case Instruction::Shl: {
3057 case Instruction::Shl:
3062 if (I->getOpcode() == Instruction::Shl) {
4683 case Instruction::Shl:
6181 case Instruction::Shl:
H A DTargetTransformInfo.cpp1252 case Instruction::Shl:
H A DBasicAliasAnalysis.cpp342 case Instruction::Shl:
H A DInstructionSimplify.cpp1235 /// Given operands for an Shl, LShr or AShr, see if we can fold the result.
1285 /// Given operands for an Shl, LShr or AShr, see if we can
1312 /// Given operands for an Shl, see if we can fold the result.
1316 if (Value *V = SimplifyShift(Instruction::Shl, Op0, Op1, Q, MaxRecurse))
3063 case Instruction::Shl: {
5018 case Instruction::Shl:
5562 case Instruction::Shl:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3772 case Instruction::Shl:
3988 if (Inst->getOpcode() == Instruction::Shl && Inst->hasOneUse()) {
4332 case Instruction::Shl: {
4339 if (Opcode == Instruction::Shl)
6231 case Instruction::Shl: {
7586 case Instruction::Shl:
H A DTargetLoweringBase.cpp1660 case Shl: return ISD::SHL;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1362 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); local
1363 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
4653 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); local
4660 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);
5004 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); local
5005 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonLoopIdiomRecognition.cpp1241 case Instruction::Shl:
1289 if (Opc == Instruction::Shl || Opc == Instruction::LShr)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopRerollPass.cpp750 case Instruction::Shl:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp122 case Instruction::Shl:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/IR/
H A DConstants.cpp2124 case Instruction::Shl:
2556 return get(Instruction::Shl, C1, C2, Flags);
2600 case Instruction::Shl: // X << 0 = X
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp1755 if (Opc == Instruction::LShr || Opc == Instruction::Shl)
2139 bool IsFshl = (!SubIsOnLHS && ShiftOpcode0 == BinaryOperator::Shl) ||
2140 (SubIsOnLHS && ShiftOpcode1 == BinaryOperator::Shl);
H A DInstCombineCalls.cpp3750 Value *Shl = Builder.CreateShl(Src, IntSize - Offset - Width); local
3751 Value *RightShift = Signed ? Builder.CreateAShr(Shl, IntSize - Width)
3752 : Builder.CreateLShr(Shl, IntSize - Width);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1989 const SDValue &Shl = N->getOperand(0); local
1990 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
2001 ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
H A DAMDGPUISelLowering.cpp2819 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width); local
2820 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
3083 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); local
3084 return DAG.getZExtOrTrunc(Shl, SL, VT);
/freebsd-13-stable/contrib/llvm-project/clang/lib/AST/Interp/
H A DInterp.h842 // Shr, Shl
911 inline bool Shl(InterpState &S, CodePtr OpPC) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1450 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg}); local
1452 Shl.addImm(*ImmVal);
1454 Shl.addUse(Src2Reg);
1455 constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLocal.cpp1756 case Instruction::Shl:
2787 if (I->getOpcode() == Instruction::Shl) {
H A DSimplifyLibCalls.cpp945 Value *Shl = B.CreateShl(B.getIntN(Width, 1ULL), C);
946 Value *Bits = B.CreateIsNotNull(B.CreateAnd(Shl, BitfieldC), "memchr.bits");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp2391 case Instruction::Shl:
2404 case Instruction::Shl: return MCBinaryExpr::createShl(LHS, RHS, Ctx);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp4280 case Instruction::Shl:
6325 case Instruction::Shl:
7036 case Instruction::Shl:
H A DSLPVectorizer.cpp2860 case Instruction::Shl:
3475 case Instruction::Shl:
4358 case Instruction::Shl:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp900 SDValue Shl = And1.getOperand(0);
902 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
914 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp1101 return IsFP ? -1 : Instruction::Shl;
2591 Opc == Instruction::Shl) {
3975 Opc == Instruction::Shl) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1877 case Instruction::Shl:

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