Searched refs:ISD (Results 76 - 100 of 155) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.h27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
96 ISD::MemIndexedMode &AM,
100 SDValue &Offset, ISD::MemIndexedMode &AM,
137 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
151 const SmallVectorImpl<ISD::OutputArg> &Outs,
155 const SmallVectorImpl<ISD::OutputArg> &Outs,
160 const SmallVectorImpl<ISD::InputArg> &Ins,
167 const SmallVectorImpl<ISD::InputArg> &Ins,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp91 if (Addr.getOpcode() != ISD::ADD && Addr.getOpcode() != ISD::SUB &&
93 if (Addr.getOpcode() == ISD::FrameIndex) {
107 if (Addr.getOpcode() == ISD::SUB)
114 if (Base.getOpcode() == ISD::FrameIndex) {
136 if (Addr.getOpcode() == ISD::SUB)
154 if (Addr.getOpcode() == ISD::ADD) {
171 case ISD::Constant: {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp54 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
61 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
H A DPPCISelLowering.h41 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
44 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
48 FIRST_NUMBER = ISD::BUILTIN_OP_END,
459 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
705 /// getSetCCResultType - Return the ISD::SETCC ValueType
719 ISD::MemIndexedMode &AM,
902 if (Opc != ISD::LOAD && Opc != ISD::STORE)
1052 ISD::LoadExtType ET = ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h178 ISD::ArgFlagsTy ArgFlags, CCState &State);
185 ISD::ArgFlagsTy &ArgFlags, CCState &State);
204 SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
282 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
286 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
293 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
299 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
304 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
310 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
314 void AnalyzeArguments(const SmallVectorImpl<ISD
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H A DSelectionDAG.h720 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
731 return getNode(ISD::CopyToReg, dl, VTs,
740 return getNode(ISD::CopyToReg, dl, VTs,
747 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
757 return getNode(ISD::CopyFromReg, dl, VTs,
761 SDValue getCondCode(ISD::CondCode Cond);
763 /// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,
769 /// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
775 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
778 /// Return an ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
79 const SmallVectorImpl<ISD::InputArg> &Ins,
93 const SmallVectorImpl<ISD::InputArg> &Ins,
98 const SmallVectorImpl<ISD::OutputArg> &Outs,
120 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
129 ISD::NodeType getExtendForAtomicOps() const override {
130 return ISD::SIGN_EXTEND;
133 ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
134 return ISD::SIGN_EXTEND;
167 const SmallVectorImpl<ISD::InputArg> &Ins,
172 const SmallVectorImpl<ISD::OutputArg> &Outs,
175 const SmallVectorImpl<ISD::OutputArg> &Outs,
207 const SmallVectorImpl<ISD::InputArg> &Ins,
210 const SmallVectorImpl<ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp458 if (Opcode == ISD::TRUNCATE) {
462 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
474 if (Op0Code == ISD::Constant)
477 if (Op1Code == ISD::Constant)
525 if (Base->getOpcode() == ISD::FrameIndex)
555 if (IndexOpcode == ISD::SIGN_EXTEND ||
556 IndexOpcode == ISD::SIGN_EXTEND_INREG)
576 if (Addr.getOpcode() == ISD::Constant &&
633 else if (Base.getOpcode() == ISD::FrameIndex) {
642 SDValue Trunc = CurDAG->getNode(ISD
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H A DSystemZSelectionDAGInfo.cpp103 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
118 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
123 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
137 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
174 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM,
176 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL,
204 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,
206 SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);
259 SDValue Len = DAG.getNode(ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp77 ISD::LoadExtType ExtType = LD->getExtensionType();
78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
134 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
139 if (ExtType == ISD::SEXTLOAD)
150 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
187 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
275 if (C->getOpcode() != ISD::INTRINSIC_W_CHAIN)
282 ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h688 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); }
692 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
693 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
694 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
696 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
697 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
698 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
699 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
700 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
701 void visitUDiv(const User &I) { visitBinary(I, ISD
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H A DResourcePriorityQueue.cpp87 case ISD::TokenFactor: break;
88 case ISD::CopyFromReg: NumberDeps++; break;
89 case ISD::CopyToReg: break;
90 case ISD::INLINEASM: break;
91 case ISD::INLINEASM_BR: break;
124 case ISD::TokenFactor: break;
125 case ISD::CopyFromReg: break;
126 case ISD::CopyToReg: NumberDeps++; break;
127 case ISD::INLINEASM: break;
128 case ISD
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H A DFastISel.cpp421 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
434 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
448 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
533 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
538 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
611 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
612 ISDOpcode == ISD::XOR))
648 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
651 ISDOpcode = ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp224 assert(Node->getOpcode() == ISD::ADD && "Should only get 'add' here.");
256 ISD::SUB, DL, VT, {CurDAG->getConstant(0, DL, VT), C});
258 SDValue NewNode = CurDAG->getNode(ISD::SUB, DL, VT, X, NegC);
284 case ISD::ADD:
291 case ISD::GLOBAL_OFFSET_TABLE:
296 case ISD::LOAD:
297 case ISD::STORE:
H A DMipsISelLowering.h60 // Start the numbering from where ISD NodeType finishes.
61 FIRST_NUMBER = ISD::BUILTIN_OP_END,
247 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
283 ISD::NodeType) const override;
315 ISD::NodeType getExtendForAtomicOps() const override {
316 return ISD::SIGN_EXTEND;
336 /// getSetCCResultType - get the ISD::SETCC result ValueType
403 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
430 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
447 return DAG.getNode(ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
122 /// getSetCCResultType - Return the ISD::SETCC ValueType
128 const SmallVectorImpl<ISD::InputArg> &Ins,
133 const SmallVectorImpl<ISD::InputArg> &Ins,
138 const SmallVectorImpl<ISD::InputArg> &Ins,
151 const SmallVectorImpl<ISD::OutputArg> &Outs,
156 const SmallVectorImpl<ISD::OutputArg> &Outs,
161 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
148 const SmallVectorImpl<ISD::InputArg> &Ins,
154 const SmallVectorImpl<ISD::OutputArg> &Outs,
156 const SmallVectorImpl<ISD::InputArg> &Ins,
212 const SmallVectorImpl<ISD::InputArg> &Ins,
221 const SmallVectorImpl<ISD::OutputArg> &Outs,
228 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
H A DXCoreISelDAGToDAG.cpp95 if (Addr.getOpcode() == ISD::ADD) {
136 case ISD::Constant: {
203 case ISD::BRIND:
221 if (Chain->getOpcode() != ISD::TokenFactor)
235 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops);
243 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
274 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp106 assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2);
334 return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
340 if (In.getOpcode() != ISD::TRUNCATE)
344 if (Srl.getOpcode() == ISD::SRL) {
359 if (In.getOpcode() == ISD::TRUNCATE) {
429 SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
436 LoadOp = LdHi->getExtensionType() == ISD::SEXTLOAD ?
464 LoadOp = LdLo->getExtensionType() == ISD::SEXTLOAD ?
470 TiedIn = CurDAG->getNode(ISD::BITCAST, SDLoc(N), VT, TiedIn);
502 case ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp349 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
401 if (N->getOpcode() != ISD::ADD)
416 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
417 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
443 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
462 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
466 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
469 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
489 if (Use->getOpcode() == ISD::CopyToReg)
536 assert(N.getOpcode() == ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.cpp29 ISD::ArgFlagsTy &ArgFlags,
93 ISD::ArgFlagsTy &ArgFlags,
130 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
190 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
229 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
239 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
299 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
H A DX86IntrinsicsInfo.h388 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
389 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
418 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
419 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
449 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
450 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
507 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
641 ISD::TRUNCATE, X86ISD::VMTRUNC),
645 ISD::TRUNCATE, X86ISD::VMTRUNC),
647 ISD
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCallLowering.h53 SmallVector<ISD::ArgFlagsTy, 4> Flags;
57 ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
62 this->Flags.push_back(ISD::ArgFlagsTy());
171 ISD::ArgFlagsTy Flags, CCState &State) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE,
84 const SmallVectorImpl<ISD::OutputArg> &Outs,
87 const SmallVectorImpl<ISD::OutputArg> &Outs,
92 const SmallVectorImpl<ISD::InputArg> &Ins,

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