1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that PPC uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15#define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16
17#include "PPCInstrInfo.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGNodes.h"
23#include "llvm/CodeGen/TargetLowering.h"
24#include "llvm/CodeGen/ValueTypes.h"
25#include "llvm/IR/Attributes.h"
26#include "llvm/IR/CallingConv.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/Metadata.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/MachineValueType.h"
32#include <utility>
33
34namespace llvm {
35
36  namespace PPCISD {
37
38    // When adding a NEW PPCISD node please add it to the correct position in
39    // the enum. The order of elements in this enum matters!
40    // Values that are added after this entry:
41    //     STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
42    // are considered memory opcodes and are treated differently than entries
43    // that come before it. For example, ADD or MUL should be placed before
44    // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
45    // after it.
46  enum NodeType : unsigned {
47    // Start the numbering where the builtin ops and target ops leave off.
48    FIRST_NUMBER = ISD::BUILTIN_OP_END,
49
50    /// FSEL - Traditional three-operand fsel node.
51    ///
52    FSEL,
53
54    /// XSMAXCDP, XSMINCDP - C-type min/max instructions.
55    XSMAXCDP,
56    XSMINCDP,
57
58    /// FCFID - The FCFID instruction, taking an f64 operand and producing
59    /// and f64 value containing the FP representation of the integer that
60    /// was temporarily in the f64 operand.
61    FCFID,
62
63    /// Newer FCFID[US] integer-to-floating-point conversion instructions for
64    /// unsigned integers and single-precision outputs.
65    FCFIDU,
66    FCFIDS,
67    FCFIDUS,
68
69    /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
70    /// operand, producing an f64 value containing the integer representation
71    /// of that FP value.
72    FCTIDZ,
73    FCTIWZ,
74
75    /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
76    /// unsigned integers with round toward zero.
77    FCTIDUZ,
78    FCTIWUZ,
79
80    /// Floating-point-to-interger conversion instructions
81    FP_TO_UINT_IN_VSR,
82    FP_TO_SINT_IN_VSR,
83
84    /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
85    /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
86    VEXTS,
87
88    /// Reciprocal estimate instructions (unary FP ops).
89    FRE,
90    FRSQRTE,
91
92    /// VPERM - The PPC VPERM Instruction.
93    ///
94    VPERM,
95
96    /// XXSPLT - The PPC VSX splat instructions
97    ///
98    XXSPLT,
99
100    /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
101    /// converting immediate single precision numbers to double precision
102    /// vector or scalar.
103    XXSPLTI_SP_TO_DP,
104
105    /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
106    ///
107    XXSPLTI32DX,
108
109    /// VECINSERT - The PPC vector insert instruction
110    ///
111    VECINSERT,
112
113    /// VECSHL - The PPC vector shift left instruction
114    ///
115    VECSHL,
116
117    /// XXPERMDI - The PPC XXPERMDI instruction
118    ///
119    XXPERMDI,
120
121    /// The CMPB instruction (takes two operands of i32 or i64).
122    CMPB,
123
124    /// Hi/Lo - These represent the high and low 16-bit parts of a global
125    /// address respectively.  These nodes have two operands, the first of
126    /// which must be a TargetGlobalAddress, and the second of which must be a
127    /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
128    /// though these are usually folded into other nodes.
129    Hi,
130    Lo,
131
132    /// The following two target-specific nodes are used for calls through
133    /// function pointers in the 64-bit SVR4 ABI.
134
135    /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
136    /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
137    /// compute an allocation on the stack.
138    DYNALLOC,
139
140    /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
141    /// compute an offset from native SP to the address  of the most recent
142    /// dynamic alloca.
143    DYNAREAOFFSET,
144
145    /// To avoid stack clash, allocation is performed by block and each block is
146    /// probed.
147    PROBED_ALLOCA,
148
149    /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
150    /// at function entry, used for PIC code.
151    GlobalBaseReg,
152
153    /// These nodes represent PPC shifts.
154    ///
155    /// For scalar types, only the last `n + 1` bits of the shift amounts
156    /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
157    /// for exact behaviors.
158    ///
159    /// For vector types, only the last n bits are used. See vsld.
160    SRL,
161    SRA,
162    SHL,
163
164    /// FNMSUB - Negated multiply-subtract instruction.
165    FNMSUB,
166
167    /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
168    /// word and shift left immediate.
169    EXTSWSLI,
170
171    /// The combination of sra[wd]i and addze used to implemented signed
172    /// integer division by a power of 2. The first operand is the dividend,
173    /// and the second is the constant shift amount (representing the
174    /// divisor).
175    SRA_ADDZE,
176
177    /// CALL - A direct function call.
178    /// CALL_NOP is a call with the special NOP which follows 64-bit
179    /// CALL_NOTOC the caller does not use the TOC.
180    /// SVR4 calls and 32-bit/64-bit AIX calls.
181    CALL,
182    CALL_NOP,
183    CALL_NOTOC,
184
185    /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
186    /// MTCTR instruction.
187    MTCTR,
188
189    /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
190    /// BCTRL instruction.
191    BCTRL,
192
193    /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
194    /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX
195    /// and 64-bit AIX.
196    BCTRL_LOAD_TOC,
197
198    /// Return with a flag operand, matched by 'blr'
199    RET_FLAG,
200
201    /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
202    /// This copies the bits corresponding to the specified CRREG into the
203    /// resultant GPR.  Bits corresponding to other CR regs are undefined.
204    MFOCRF,
205
206    /// Direct move from a VSX register to a GPR
207    MFVSR,
208
209    /// Direct move from a GPR to a VSX register (algebraic)
210    MTVSRA,
211
212    /// Direct move from a GPR to a VSX register (zero)
213    MTVSRZ,
214
215    /// Direct move of 2 consecutive GPR to a VSX register.
216    BUILD_FP128,
217
218    /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
219    /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
220    /// unsupported for this target.
221    /// Merge 2 GPRs to a single SPE register.
222    BUILD_SPE64,
223
224    /// Extract SPE register component, second argument is high or low.
225    EXTRACT_SPE,
226
227    /// Extract a subvector from signed integer vector and convert to FP.
228    /// It is primarily used to convert a (widened) illegal integer vector
229    /// type to a legal floating point vector type.
230    /// For example v2i32 -> widened to v4i32 -> v2f64
231    SINT_VEC_TO_FP,
232
233    /// Extract a subvector from unsigned integer vector and convert to FP.
234    /// As with SINT_VEC_TO_FP, used for converting illegal types.
235    UINT_VEC_TO_FP,
236
237    /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to
238    /// place the value into the least significant element of the most
239    /// significant doubleword in the vector. This is not element zero for
240    /// anything smaller than a doubleword on either endianness. This node has
241    /// the same semantics as SCALAR_TO_VECTOR except that the value remains in
242    /// the aforementioned location in the vector register.
243    SCALAR_TO_VECTOR_PERMUTED,
244
245    // FIXME: Remove these once the ANDI glue bug is fixed:
246    /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
247    /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
248    /// implement truncation of i32 or i64 to i1.
249    ANDI_rec_1_EQ_BIT,
250    ANDI_rec_1_GT_BIT,
251
252    // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
253    // target (returns (Lo, Hi)). It takes a chain operand.
254    READ_TIME_BASE,
255
256    // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
257    EH_SJLJ_SETJMP,
258
259    // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
260    EH_SJLJ_LONGJMP,
261
262    /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
263    /// instructions.  For lack of better number, we use the opcode number
264    /// encoding for the OPC field to identify the compare.  For example, 838
265    /// is VCMPGTSH.
266    VCMP,
267
268    /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
269    /// altivec VCMP*o instructions.  For lack of better number, we use the
270    /// opcode number encoding for the OPC field to identify the compare.  For
271    /// example, 838 is VCMPGTSH.
272    VCMPo,
273
274    /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
275    /// corresponds to the COND_BRANCH pseudo instruction.  CRRC is the
276    /// condition register to branch on, OPC is the branch opcode to use (e.g.
277    /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
278    /// an optional input flag argument.
279    COND_BRANCH,
280
281    /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
282    /// loops.
283    BDNZ,
284    BDZ,
285
286    /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
287    /// towards zero.  Used only as part of the long double-to-int
288    /// conversion sequence.
289    FADDRTZ,
290
291    /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
292    MFFS,
293
294    /// TC_RETURN - A tail call return.
295    ///   operand #0 chain
296    ///   operand #1 callee (register or absolute)
297    ///   operand #2 stack adjustment
298    ///   operand #3 optional in flag
299    TC_RETURN,
300
301    /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
302    CR6SET,
303    CR6UNSET,
304
305    /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
306    /// for non-position independent code on PPC32.
307    PPC32_GOT,
308
309    /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
310    /// local dynamic TLS and position indendepent code on PPC32.
311    PPC32_PICGOT,
312
313    /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
314    /// TLS model, produces an ADDIS8 instruction that adds the GOT
315    /// base to sym\@got\@tprel\@ha.
316    ADDIS_GOT_TPREL_HA,
317
318    /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
319    /// TLS model, produces a LD instruction with base register G8RReg
320    /// and offset sym\@got\@tprel\@l.  This completes the addition that
321    /// finds the offset of "sym" relative to the thread pointer.
322    LD_GOT_TPREL_L,
323
324    /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
325    /// model, produces an ADD instruction that adds the contents of
326    /// G8RReg to the thread pointer.  Symbol contains a relocation
327    /// sym\@tls which is to be replaced by the thread pointer and
328    /// identifies to the linker that the instruction is part of a
329    /// TLS sequence.
330    ADD_TLS,
331
332    /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
333    /// model, produces an ADDIS8 instruction that adds the GOT base
334    /// register to sym\@got\@tlsgd\@ha.
335    ADDIS_TLSGD_HA,
336
337    /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
338    /// model, produces an ADDI8 instruction that adds G8RReg to
339    /// sym\@got\@tlsgd\@l and stores the result in X3.  Hidden by
340    /// ADDIS_TLSGD_L_ADDR until after register assignment.
341    ADDI_TLSGD_L,
342
343    /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
344    /// model, produces a call to __tls_get_addr(sym\@tlsgd).  Hidden by
345    /// ADDIS_TLSGD_L_ADDR until after register assignment.
346    GET_TLS_ADDR,
347
348    /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
349    /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
350    /// register assignment.
351    ADDI_TLSGD_L_ADDR,
352
353    /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
354    /// model, produces an ADDIS8 instruction that adds the GOT base
355    /// register to sym\@got\@tlsld\@ha.
356    ADDIS_TLSLD_HA,
357
358    /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
359    /// model, produces an ADDI8 instruction that adds G8RReg to
360    /// sym\@got\@tlsld\@l and stores the result in X3.  Hidden by
361    /// ADDIS_TLSLD_L_ADDR until after register assignment.
362    ADDI_TLSLD_L,
363
364    /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
365    /// model, produces a call to __tls_get_addr(sym\@tlsld).  Hidden by
366    /// ADDIS_TLSLD_L_ADDR until after register assignment.
367    GET_TLSLD_ADDR,
368
369    /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
370    /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
371    /// following register assignment.
372    ADDI_TLSLD_L_ADDR,
373
374    /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
375    /// model, produces an ADDIS8 instruction that adds X3 to
376    /// sym\@dtprel\@ha.
377    ADDIS_DTPREL_HA,
378
379    /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
380    /// model, produces an ADDI8 instruction that adds G8RReg to
381    /// sym\@got\@dtprel\@l.
382    ADDI_DTPREL_L,
383
384    /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
385    /// during instruction selection to optimize a BUILD_VECTOR into
386    /// operations on splats.  This is necessary to avoid losing these
387    /// optimizations due to constant folding.
388    VADD_SPLAT,
389
390    /// CHAIN = SC CHAIN, Imm128 - System call.  The 7-bit unsigned
391    /// operand identifies the operating system entry point.
392    SC,
393
394    /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
395    CLRBHRB,
396
397    /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
398    /// history rolling buffer entry.
399    MFBHRBE,
400
401    /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
402    RFEBB,
403
404    /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
405    /// endian.  Maps to an xxswapd instruction that corrects an lxvd2x
406    /// or stxvd2x instruction.  The chain is necessary because the
407    /// sequence replaces a load and needs to provide the same number
408    /// of outputs.
409    XXSWAPD,
410
411    /// An SDNode for swaps that are not associated with any loads/stores
412    /// and thereby have no chain.
413    SWAP_NO_CHAIN,
414
415    /// An SDNode for Power9 vector absolute value difference.
416    /// operand #0 vector
417    /// operand #1 vector
418    /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
419    /// the most significant bit for signed i32
420    ///
421    /// Power9 VABSD* instructions are designed to support unsigned integer
422    /// vectors (byte/halfword/word), if we want to make use of them for signed
423    /// integer vectors, we have to flip their sign bits first. To flip sign bit
424    /// for byte/halfword integer vector would become inefficient, but for word
425    /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
426    /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
427    ///               => VABSDUW((XVNEGSP a), (XVNEGSP b))
428    VABSD,
429
430    /// QVFPERM = This corresponds to the QPX qvfperm instruction.
431    QVFPERM,
432
433    /// QVGPCI = This corresponds to the QPX qvgpci instruction.
434    QVGPCI,
435
436    /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
437    QVALIGNI,
438
439    /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
440    QVESPLATI,
441
442    /// QBFLT = Access the underlying QPX floating-point boolean
443    /// representation.
444    QBFLT,
445
446    /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or
447    /// lower (IDX=1) half of v4f32 to v2f64.
448    FP_EXTEND_HALF,
449
450    /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
451    /// either through an add like PADDI or through a PC Relative load like
452    /// PLD.
453    MAT_PCREL_ADDR,
454
455    /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
456    /// byte-swapping store instruction.  It byte-swaps the low "Type" bits of
457    /// the GPRC input, then stores it through Ptr.  Type can be either i16 or
458    /// i32.
459    STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
460
461    /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
462    /// byte-swapping load instruction.  It loads "Type" bits, byte swaps it,
463    /// then puts it in the bottom bits of the GPRC.  TYPE can be either i16
464    /// or i32.
465    LBRX,
466
467    /// STFIWX - The STFIWX instruction.  The first operand is an input token
468    /// chain, then an f64 value to store, then an address to store it to.
469    STFIWX,
470
471    /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
472    /// load which sign-extends from a 32-bit integer value into the
473    /// destination 64-bit register.
474    LFIWAX,
475
476    /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
477    /// load which zero-extends from a 32-bit integer value into the
478    /// destination 64-bit register.
479    LFIWZX,
480
481    /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
482    /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
483    /// This can be used for converting loaded integers to floating point.
484    LXSIZX,
485
486    /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
487    /// chain, then an f64 value to store, then an address to store it to,
488    /// followed by a byte-width for the store.
489    STXSIX,
490
491    /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
492    /// Maps directly to an lxvd2x instruction that will be followed by
493    /// an xxswapd.
494    LXVD2X,
495
496    /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
497    /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on
498    /// the vector type to load vector in big-endian element order.
499    LOAD_VEC_BE,
500
501    /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a
502    /// v2f32 value into the lower half of a VSR register.
503    LD_VSX_LH,
504
505    /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory
506    /// instructions such as LXVDSX, LXVWSX.
507    LD_SPLAT,
508
509    /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
510    /// Maps directly to an stxvd2x instruction that will be preceded by
511    /// an xxswapd.
512    STXVD2X,
513
514    /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
515    /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on
516    /// the vector type to store vector in big-endian element order.
517    STORE_VEC_BE,
518
519    /// Store scalar integers from VSR.
520    ST_VSR_SCAL_INT,
521
522    /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
523    /// The 4xf32 load used for v4i1 constants.
524    QVLFSb,
525
526    /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
527    /// except they ensure that the compare input is zero-extended for
528    /// sub-word versions because the atomic loads zero-extend.
529    ATOMIC_CMP_SWAP_8,
530    ATOMIC_CMP_SWAP_16,
531
532    /// GPRC = TOC_ENTRY GA, TOC
533    /// Loads the entry for GA from the TOC, where the TOC base is given by
534    /// the last operand.
535    TOC_ENTRY
536  };
537
538  } // end namespace PPCISD
539
540  /// Define some predicates that are used for node matching.
541  namespace PPC {
542
543    /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
544    /// VPKUHUM instruction.
545    bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
546                              SelectionDAG &DAG);
547
548    /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
549    /// VPKUWUM instruction.
550    bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
551                              SelectionDAG &DAG);
552
553    /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
554    /// VPKUDUM instruction.
555    bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
556                              SelectionDAG &DAG);
557
558    /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
559    /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
560    bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
561                            unsigned ShuffleKind, SelectionDAG &DAG);
562
563    /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
564    /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
565    bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
566                            unsigned ShuffleKind, SelectionDAG &DAG);
567
568    /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
569    /// a VMRGEW or VMRGOW instruction
570    bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
571                             unsigned ShuffleKind, SelectionDAG &DAG);
572    /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
573    /// for a XXSLDWI instruction.
574    bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
575                              bool &Swap, bool IsLE);
576
577    /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
578    /// for a XXBRH instruction.
579    bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
580
581    /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
582    /// for a XXBRW instruction.
583    bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
584
585    /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
586    /// for a XXBRD instruction.
587    bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
588
589    /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
590    /// for a XXBRQ instruction.
591    bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
592
593    /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
594    /// for a XXPERMDI instruction.
595    bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
596                              bool &Swap, bool IsLE);
597
598    /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
599    /// shift amount, otherwise return -1.
600    int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
601                            SelectionDAG &DAG);
602
603    /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
604    /// specifies a splat of a single element that is suitable for input to
605    /// VSPLTB/VSPLTH/VSPLTW.
606    bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
607
608    /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
609    /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
610    /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
611    /// vector into the other. This function will also set a couple of
612    /// output parameters for how much the source vector needs to be shifted and
613    /// what byte number needs to be specified for the instruction to put the
614    /// element in the desired location of the target vector.
615    bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
616                         unsigned &InsertAtByte, bool &Swap, bool IsLE);
617
618    /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
619    /// appropriate for PPC mnemonics (which have a big endian bias - namely
620    /// elements are counted from the left of the vector register).
621    unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
622                                        SelectionDAG &DAG);
623
624    /// get_VSPLTI_elt - If this is a build_vector of constants which can be
625    /// formed by using a vspltis[bhw] instruction of the specified element
626    /// size, return the constant being splatted.  The ByteSize field indicates
627    /// the number of bytes of each element [124] -> [bhw].
628    SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
629
630    /// If this is a qvaligni shuffle mask, return the shift
631    /// amount, otherwise return -1.
632    int isQVALIGNIShuffleMask(SDNode *N);
633
634  } // end namespace PPC
635
636  class PPCTargetLowering : public TargetLowering {
637    const PPCSubtarget &Subtarget;
638
639  public:
640    explicit PPCTargetLowering(const PPCTargetMachine &TM,
641                               const PPCSubtarget &STI);
642
643    /// getTargetNodeName() - This method returns the name of a target specific
644    /// DAG node.
645    const char *getTargetNodeName(unsigned Opcode) const override;
646
647    bool isSelectSupported(SelectSupportKind Kind) const override {
648      // PowerPC does not support scalar condition selects on vectors.
649      return (Kind != SelectSupportKind::ScalarCondVectorVal);
650    }
651
652    /// getPreferredVectorAction - The code we generate when vector types are
653    /// legalized by promoting the integer element type is often much worse
654    /// than code we generate if we widen the type for applicable vector types.
655    /// The issue with promoting is that the vector is scalaraized, individual
656    /// elements promoted and then the vector is rebuilt. So say we load a pair
657    /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
658    /// loads, moves back into VSR's (or memory ops if we don't have moves) and
659    /// then the VPERM for the shuffle. All in all a very slow sequence.
660    TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
661      const override {
662      if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0)
663        return TypeWidenVector;
664      return TargetLoweringBase::getPreferredVectorAction(VT);
665    }
666
667    bool useSoftFloat() const override;
668
669    bool hasSPE() const;
670
671    MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
672      return MVT::i32;
673    }
674
675    bool isCheapToSpeculateCttz() const override {
676      return true;
677    }
678
679    bool isCheapToSpeculateCtlz() const override {
680      return true;
681    }
682
683    bool isCtlzFast() const override {
684      return true;
685    }
686
687    bool isEqualityCmpFoldedWithSignedCmp() const override {
688      return false;
689    }
690
691    bool hasAndNotCompare(SDValue) const override {
692      return true;
693    }
694
695    bool preferIncOfAddToSubOfNot(EVT VT) const override;
696
697    bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
698      return VT.isScalarInteger();
699    }
700
701    SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
702                                 bool OptForSize, NegatibleCost &Cost,
703                                 unsigned Depth = 0) const override;
704
705    /// getSetCCResultType - Return the ISD::SETCC ValueType
706    EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
707                           EVT VT) const override;
708
709    /// Return true if target always beneficiates from combining into FMA for a
710    /// given value type. This must typically return false on targets where FMA
711    /// takes more cycles to execute than FADD.
712    bool enableAggressiveFMAFusion(EVT VT) const override;
713
714    /// getPreIndexedAddressParts - returns true by value, base pointer and
715    /// offset pointer and addressing mode by reference if the node's address
716    /// can be legally represented as pre-indexed load / store address.
717    bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
718                                   SDValue &Offset,
719                                   ISD::MemIndexedMode &AM,
720                                   SelectionDAG &DAG) const override;
721
722    /// SelectAddressEVXRegReg - Given the specified addressed, check to see if
723    /// it can be more efficiently represented as [r+imm].
724    bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index,
725                                SelectionDAG &DAG) const;
726
727    /// SelectAddressRegReg - Given the specified addressed, check to see if it
728    /// can be more efficiently represented as [r+imm]. If \p EncodingAlignment
729    /// is non-zero, only accept displacement which is not suitable for [r+imm].
730    /// Returns false if it can be represented by [r+imm], which are preferred.
731    bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
732                             SelectionDAG &DAG,
733                             MaybeAlign EncodingAlignment = None) const;
734
735    /// SelectAddressRegImm - Returns true if the address N can be represented
736    /// by a base register plus a signed 16-bit displacement [r+imm], and if it
737    /// is not better represented as reg+reg. If \p EncodingAlignment is
738    /// non-zero, only accept displacements suitable for instruction encoding
739    /// requirement, i.e. multiples of 4 for DS form.
740    bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
741                             SelectionDAG &DAG,
742                             MaybeAlign EncodingAlignment) const;
743
744    /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
745    /// represented as an indexed [r+r] operation.
746    bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
747                                 SelectionDAG &DAG) const;
748
749    /// SelectAddressPCRel - Represent the specified address as pc relative to
750    /// be represented as [pc+imm]
751    bool SelectAddressPCRel(SDValue N, SDValue &Base) const;
752
753    Sched::Preference getSchedulingPreference(SDNode *N) const override;
754
755    /// LowerOperation - Provide custom lowering hooks for some operations.
756    ///
757    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
758
759    /// ReplaceNodeResults - Replace the results of node with an illegal result
760    /// type with new values built out of custom code.
761    ///
762    void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
763                            SelectionDAG &DAG) const override;
764
765    SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
766    SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
767
768    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
769
770    SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
771                          SmallVectorImpl<SDNode *> &Created) const override;
772
773    Register getRegisterByName(const char* RegName, LLT VT,
774                               const MachineFunction &MF) const override;
775
776    void computeKnownBitsForTargetNode(const SDValue Op,
777                                       KnownBits &Known,
778                                       const APInt &DemandedElts,
779                                       const SelectionDAG &DAG,
780                                       unsigned Depth = 0) const override;
781
782    Align getPrefLoopAlignment(MachineLoop *ML) const override;
783
784    bool shouldInsertFencesForAtomic(const Instruction *I) const override {
785      return true;
786    }
787
788    Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
789                                  AtomicOrdering Ord) const override;
790    Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
791                                   AtomicOrdering Ord) const override;
792
793    MachineBasicBlock *
794    EmitInstrWithCustomInserter(MachineInstr &MI,
795                                MachineBasicBlock *MBB) const override;
796    MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
797                                        MachineBasicBlock *MBB,
798                                        unsigned AtomicSize,
799                                        unsigned BinOpcode,
800                                        unsigned CmpOpcode = 0,
801                                        unsigned CmpPred = 0) const;
802    MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
803                                                MachineBasicBlock *MBB,
804                                                bool is8bit,
805                                                unsigned Opcode,
806                                                unsigned CmpOpcode = 0,
807                                                unsigned CmpPred = 0) const;
808
809    MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
810                                        MachineBasicBlock *MBB) const;
811
812    MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
813                                         MachineBasicBlock *MBB) const;
814
815    MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
816                                        MachineBasicBlock *MBB) const;
817
818    bool hasInlineStackProbe(MachineFunction &MF) const override;
819
820    unsigned getStackProbeSize(MachineFunction &MF) const;
821
822    ConstraintType getConstraintType(StringRef Constraint) const override;
823
824    /// Examine constraint string and operand type and determine a weight value.
825    /// The operand object must already have been set up with the operand type.
826    ConstraintWeight getSingleConstraintMatchWeight(
827      AsmOperandInfo &info, const char *constraint) const override;
828
829    std::pair<unsigned, const TargetRegisterClass *>
830    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
831                                 StringRef Constraint, MVT VT) const override;
832
833    /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
834    /// function arguments in the caller parameter area.  This is the actual
835    /// alignment, not its logarithm.
836    unsigned getByValTypeAlignment(Type *Ty,
837                                   const DataLayout &DL) const override;
838
839    /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
840    /// vector.  If it is invalid, don't add anything to Ops.
841    void LowerAsmOperandForConstraint(SDValue Op,
842                                      std::string &Constraint,
843                                      std::vector<SDValue> &Ops,
844                                      SelectionDAG &DAG) const override;
845
846    unsigned
847    getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
848      if (ConstraintCode == "es")
849        return InlineAsm::Constraint_es;
850      else if (ConstraintCode == "o")
851        return InlineAsm::Constraint_o;
852      else if (ConstraintCode == "Q")
853        return InlineAsm::Constraint_Q;
854      else if (ConstraintCode == "Z")
855        return InlineAsm::Constraint_Z;
856      else if (ConstraintCode == "Zy")
857        return InlineAsm::Constraint_Zy;
858      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
859    }
860
861    /// isLegalAddressingMode - Return true if the addressing mode represented
862    /// by AM is legal for this target, for a load/store of the specified type.
863    bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
864                               Type *Ty, unsigned AS,
865                               Instruction *I = nullptr) const override;
866
867    /// isLegalICmpImmediate - Return true if the specified immediate is legal
868    /// icmp immediate, that is the target has icmp instructions which can
869    /// compare a register against the immediate without having to materialize
870    /// the immediate into a register.
871    bool isLegalICmpImmediate(int64_t Imm) const override;
872
873    /// isLegalAddImmediate - Return true if the specified immediate is legal
874    /// add immediate, that is the target has add instructions which can
875    /// add a register and the immediate without having to materialize
876    /// the immediate into a register.
877    bool isLegalAddImmediate(int64_t Imm) const override;
878
879    /// isTruncateFree - Return true if it's free to truncate a value of
880    /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
881    /// register X1 to i32 by referencing its sub-register R1.
882    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
883    bool isTruncateFree(EVT VT1, EVT VT2) const override;
884
885    bool isZExtFree(SDValue Val, EVT VT2) const override;
886
887    bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
888
889    /// Returns true if it is beneficial to convert a load of a constant
890    /// to just the constant itself.
891    bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
892                                           Type *Ty) const override;
893
894    bool convertSelectOfConstantsToMath(EVT VT) const override {
895      return true;
896    }
897
898    bool isDesirableToTransformToIntegerOp(unsigned Opc,
899                                           EVT VT) const override {
900      // Only handle float load/store pair because float(fpr) load/store
901      // instruction has more cycles than integer(gpr) load/store in PPC.
902      if (Opc != ISD::LOAD && Opc != ISD::STORE)
903        return false;
904      if (VT != MVT::f32 && VT != MVT::f64)
905        return false;
906
907      return true;
908    }
909
910    // Returns true if the address of the global is stored in TOC entry.
911    bool isAccessedAsGotIndirect(SDValue N) const;
912
913    bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
914
915    bool getTgtMemIntrinsic(IntrinsicInfo &Info,
916                            const CallInst &I,
917                            MachineFunction &MF,
918                            unsigned Intrinsic) const override;
919
920    /// It returns EVT::Other if the type should be determined using generic
921    /// target-independent logic.
922    EVT getOptimalMemOpType(const MemOp &Op,
923                            const AttributeList &FuncAttributes) const override;
924
925    /// Is unaligned memory access allowed for the given type, and is it fast
926    /// relative to software emulation.
927    bool allowsMisalignedMemoryAccesses(
928        EVT VT, unsigned AddrSpace, unsigned Align = 1,
929        MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
930        bool *Fast = nullptr) const override;
931
932    /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
933    /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
934    /// expanded to FMAs when this method returns true, otherwise fmuladd is
935    /// expanded to fmul + fadd.
936    bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
937                                    EVT VT) const override;
938
939    bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
940
941    /// isProfitableToHoist - Check if it is profitable to hoist instruction
942    /// \p I to its dominator block.
943    /// For example, it is not profitable if \p I and it's only user can form a
944    /// FMA instruction, because Powerpc prefers FMADD.
945    bool isProfitableToHoist(Instruction *I) const override;
946
947    const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
948
949    // Should we expand the build vector with shuffles?
950    bool
951    shouldExpandBuildVectorWithShuffles(EVT VT,
952                                        unsigned DefinedValues) const override;
953
954    /// createFastISel - This method returns a target-specific FastISel object,
955    /// or null if the target does not support "fast" instruction selection.
956    FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
957                             const TargetLibraryInfo *LibInfo) const override;
958
959    /// Returns true if an argument of type Ty needs to be passed in a
960    /// contiguous block of registers in calling convention CallConv.
961    bool functionArgumentNeedsConsecutiveRegisters(
962      Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
963      // We support any array type as "consecutive" block in the parameter
964      // save area.  The element type defines the alignment requirement and
965      // whether the argument should go in GPRs, FPRs, or VRs if available.
966      //
967      // Note that clang uses this capability both to implement the ELFv2
968      // homogeneous float/vector aggregate ABI, and to avoid having to use
969      // "byval" when passing aggregates that might fully fit in registers.
970      return Ty->isArrayTy();
971    }
972
973    /// If a physical register, this returns the register that receives the
974    /// exception address on entry to an EH pad.
975    Register
976    getExceptionPointerRegister(const Constant *PersonalityFn) const override;
977
978    /// If a physical register, this returns the register that receives the
979    /// exception typeid on entry to a landing pad.
980    Register
981    getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
982
983    /// isMulhCheaperThanMulShift - Return true if a mulh[s|u] node for a
984    /// specific type is cheaper than a multiply followed by a shift.
985    /// This is true for words and doublewords on 64-bit PowerPC.
986    bool isMulhCheaperThanMulShift(EVT Type) const override;
987
988    /// Override to support customized stack guard loading.
989    bool useLoadStackGuardNode() const override;
990    void insertSSPDeclarations(Module &M) const override;
991
992    bool isFPImmLegal(const APFloat &Imm, EVT VT,
993                      bool ForCodeSize) const override;
994
995    unsigned getJumpTableEncoding() const override;
996    bool isJumpTableRelative() const override;
997    SDValue getPICJumpTableRelocBase(SDValue Table,
998                                     SelectionDAG &DAG) const override;
999    const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1000                                               unsigned JTI,
1001                                               MCContext &Ctx) const override;
1002
1003    /// Structure that collects some common arguments that get passed around
1004    /// between the functions for call lowering.
1005    struct CallFlags {
1006      const CallingConv::ID CallConv;
1007      const bool IsTailCall : 1;
1008      const bool IsVarArg : 1;
1009      const bool IsPatchPoint : 1;
1010      const bool IsIndirect : 1;
1011      const bool HasNest : 1;
1012      const bool NoMerge : 1;
1013
1014      CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg,
1015                bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)
1016          : CallConv(CC), IsTailCall(IsTailCall), IsVarArg(IsVarArg),
1017            IsPatchPoint(IsPatchPoint), IsIndirect(IsIndirect),
1018            HasNest(HasNest), NoMerge(NoMerge) {}
1019    };
1020
1021  private:
1022    struct ReuseLoadInfo {
1023      SDValue Ptr;
1024      SDValue Chain;
1025      SDValue ResChain;
1026      MachinePointerInfo MPI;
1027      bool IsDereferenceable = false;
1028      bool IsInvariant = false;
1029      Align Alignment;
1030      AAMDNodes AAInfo;
1031      const MDNode *Ranges = nullptr;
1032
1033      ReuseLoadInfo() = default;
1034
1035      MachineMemOperand::Flags MMOFlags() const {
1036        MachineMemOperand::Flags F = MachineMemOperand::MONone;
1037        if (IsDereferenceable)
1038          F |= MachineMemOperand::MODereferenceable;
1039        if (IsInvariant)
1040          F |= MachineMemOperand::MOInvariant;
1041        return F;
1042      }
1043    };
1044
1045    bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
1046      // Addrspacecasts are always noops.
1047      return true;
1048    }
1049
1050    bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
1051                             SelectionDAG &DAG,
1052                             ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
1053    void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
1054                         SelectionDAG &DAG) const;
1055
1056    void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
1057                                SelectionDAG &DAG, const SDLoc &dl) const;
1058    SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
1059                                     const SDLoc &dl) const;
1060
1061    bool directMoveIsProfitable(const SDValue &Op) const;
1062    SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
1063                                     const SDLoc &dl) const;
1064
1065    SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
1066                                 const SDLoc &dl) const;
1067
1068    SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
1069
1070    SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
1071    SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
1072
1073    bool
1074    IsEligibleForTailCallOptimization(SDValue Callee,
1075                                      CallingConv::ID CalleeCC,
1076                                      bool isVarArg,
1077                                      const SmallVectorImpl<ISD::InputArg> &Ins,
1078                                      SelectionDAG& DAG) const;
1079
1080    bool IsEligibleForTailCallOptimization_64SVR4(
1081        SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB,
1082        bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
1083        const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
1084
1085    SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
1086                                         SDValue Chain, SDValue &LROpOut,
1087                                         SDValue &FPOpOut,
1088                                         const SDLoc &dl) const;
1089
1090    SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;
1091
1092    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1093    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1094    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1095    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1096    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1097    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1098    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1099    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1100    SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1101    SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1102    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1103    SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1104    SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
1105    SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
1106    SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1107    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1108    SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1109    SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1110    SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1111    SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1112    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1113    SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1114                           const SDLoc &dl) const;
1115    SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1116    SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1117    SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1118    SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1119    SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1120    SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1121    SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1122    SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1123    SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1124    SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1125    SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1126    SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1127    SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1128    SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1129    SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
1130    SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1131    SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1132    SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
1133    SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
1134
1135    SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1136    SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1137
1138    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1139                            CallingConv::ID CallConv, bool isVarArg,
1140                            const SmallVectorImpl<ISD::InputArg> &Ins,
1141                            const SDLoc &dl, SelectionDAG &DAG,
1142                            SmallVectorImpl<SDValue> &InVals) const;
1143
1144    SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
1145                       SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1146                       SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1147                       SDValue &Callee, int SPDiff, unsigned NumBytes,
1148                       const SmallVectorImpl<ISD::InputArg> &Ins,
1149                       SmallVectorImpl<SDValue> &InVals,
1150                       const CallBase *CB) const;
1151
1152    SDValue
1153    LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1154                         const SmallVectorImpl<ISD::InputArg> &Ins,
1155                         const SDLoc &dl, SelectionDAG &DAG,
1156                         SmallVectorImpl<SDValue> &InVals) const override;
1157
1158    SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1159                      SmallVectorImpl<SDValue> &InVals) const override;
1160
1161    bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1162                        bool isVarArg,
1163                        const SmallVectorImpl<ISD::OutputArg> &Outs,
1164                        LLVMContext &Context) const override;
1165
1166    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1167                        const SmallVectorImpl<ISD::OutputArg> &Outs,
1168                        const SmallVectorImpl<SDValue> &OutVals,
1169                        const SDLoc &dl, SelectionDAG &DAG) const override;
1170
1171    SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1172                              SelectionDAG &DAG, SDValue ArgVal,
1173                              const SDLoc &dl) const;
1174
1175    SDValue LowerFormalArguments_AIX(
1176        SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1177        const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1178        SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1179    SDValue LowerFormalArguments_Darwin(
1180        SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1181        const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1182        SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1183    SDValue LowerFormalArguments_64SVR4(
1184        SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1185        const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1186        SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1187    SDValue LowerFormalArguments_32SVR4(
1188        SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1189        const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1190        SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1191
1192    SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1193                                       SDValue CallSeqStart,
1194                                       ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1195                                       const SDLoc &dl) const;
1196
1197    SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee, CallFlags CFlags,
1198                             const SmallVectorImpl<ISD::OutputArg> &Outs,
1199                             const SmallVectorImpl<SDValue> &OutVals,
1200                             const SmallVectorImpl<ISD::InputArg> &Ins,
1201                             const SDLoc &dl, SelectionDAG &DAG,
1202                             SmallVectorImpl<SDValue> &InVals,
1203                             const CallBase *CB) const;
1204    SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1205                             const SmallVectorImpl<ISD::OutputArg> &Outs,
1206                             const SmallVectorImpl<SDValue> &OutVals,
1207                             const SmallVectorImpl<ISD::InputArg> &Ins,
1208                             const SDLoc &dl, SelectionDAG &DAG,
1209                             SmallVectorImpl<SDValue> &InVals,
1210                             const CallBase *CB) const;
1211    SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallFlags CFlags,
1212                             const SmallVectorImpl<ISD::OutputArg> &Outs,
1213                             const SmallVectorImpl<SDValue> &OutVals,
1214                             const SmallVectorImpl<ISD::InputArg> &Ins,
1215                             const SDLoc &dl, SelectionDAG &DAG,
1216                             SmallVectorImpl<SDValue> &InVals,
1217                             const CallBase *CB) const;
1218    SDValue LowerCall_AIX(SDValue Chain, SDValue Callee, CallFlags CFlags,
1219                          const SmallVectorImpl<ISD::OutputArg> &Outs,
1220                          const SmallVectorImpl<SDValue> &OutVals,
1221                          const SmallVectorImpl<ISD::InputArg> &Ins,
1222                          const SDLoc &dl, SelectionDAG &DAG,
1223                          SmallVectorImpl<SDValue> &InVals,
1224                          const CallBase *CB) const;
1225
1226    SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1227    SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1228    SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1229
1230    SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1231    SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1232    SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1233    SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1234    SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1235    SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1236    SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1237    SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1238    SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1239    SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1240    SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
1241    SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1242    SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1243    SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1244    SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1245    SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
1246                                 SelectionDAG &DAG) const;
1247    SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
1248                                 DAGCombinerInfo &DCI) const;
1249
1250    /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1251    /// SETCC with integer subtraction when (1) there is a legal way of doing it
1252    /// (2) keeping the result of comparison in GPR has performance benefit.
1253    SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1254
1255    SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1256                            int &RefinementSteps, bool &UseOneConstNR,
1257                            bool Reciprocal) const override;
1258    SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1259                             int &RefinementSteps) const override;
1260    unsigned combineRepeatedFPDivisors() const override;
1261
1262    SDValue
1263    combineElementTruncationToVectorTruncation(SDNode *N,
1264                                               DAGCombinerInfo &DCI) const;
1265
1266    /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1267    /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1268    /// essentially any shuffle of v8i16 vectors that just inserts one element
1269    /// from one vector into the other.
1270    SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1271
1272    /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1273    /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1274    /// essentially v16i8 vector version of VINSERTH.
1275    SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1276
1277    /// lowerToXXSPLTI32DX - Return the SDValue if this VECTOR_SHUFFLE can be
1278    /// handled by the XXSPLTI32DX instruction introduced in ISA 3.1.
1279    SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1280
1281    // Return whether the call instruction can potentially be optimized to a
1282    // tail call. This will cause the optimizers to attempt to move, or
1283    // duplicate return instructions to help enable tail call optimizations.
1284    bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1285    bool hasBitPreservingFPLogic(EVT VT) const override;
1286    bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1287  }; // end class PPCTargetLowering
1288
1289  namespace PPC {
1290
1291    FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1292                             const TargetLibraryInfo *LibInfo);
1293
1294  } // end namespace PPC
1295
1296  bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1297  bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1298
1299  bool convertToNonDenormSingle(APInt &ArgAPInt);
1300  bool convertToNonDenormSingle(APFloat &ArgAPFloat);
1301
1302} // end namespace llvm
1303
1304#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
1305