Lines Matching refs:ISD
349 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
401 if (N->getOpcode() != ISD::ADD)
416 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
417 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
443 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
462 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
466 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
469 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
489 if (Use->getOpcode() == ISD::CopyToReg)
536 assert(N.getOpcode() == ISD::MUL);
580 if (N.getOpcode() == ISD::MUL) {
637 // Determine whether an ISD::OR's operands are suitable to turn the operation
640 assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
652 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
654 if (N.getOpcode() == ISD::FrameIndex) {
664 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
665 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
666 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
676 if (N.getOpcode() == ISD::SUB)
681 if (Base.getOpcode() == ISD::FrameIndex) {
701 if (N.getOpcode() == ISD::MUL &&
725 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
726 // ISD::OR that is equivalent to an ISD::ADD.
731 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
739 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
765 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
790 if (Offset.getOpcode() == ISD::MUL && N.hasOneUse()) {
810 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
813 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
846 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
849 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
866 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
869 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
891 if (N.getOpcode() == ISD::SUB) {
902 if (N.getOpcode() == ISD::FrameIndex) {
918 if (Base.getOpcode() == ISD::FrameIndex) {
945 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
948 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
968 if (N.getOpcode() == ISD::FrameIndex) {
973 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
974 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
975 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
989 if (Base.getOpcode() == ISD::FrameIndex) {
1065 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1066 if (AM != ISD::POST_INC)
1098 if (N.getOpcode() != ISD::ADD)
1110 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1141 if (N.getOpcode() == ISD::ADD) {
1144 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
1145 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
1146 N.getOperand(0).getOpcode() != ISD::TargetConstantPool &&
1147 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
1189 if (N.getOpcode() == ISD::FrameIndex) {
1205 if (N.getOperand(0).getOpcode() == ISD::FrameIndex) {
1236 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1241 if (N.getOpcode() == ISD::SUB)
1266 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1268 if (N.getOpcode() == ISD::FrameIndex) {
1278 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress &&
1279 N.getOperand(0).getOpcode() != ISD::TargetExternalSymbol &&
1280 N.getOperand(0).getOpcode() != ISD::TargetGlobalTLSAddress) {
1282 if (Base.getOpcode() == ISD::TargetConstantPool)
1296 if (N.getOpcode() == ISD::SUB)
1301 if (Base.getOpcode() == ISD::FrameIndex) {
1320 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1324 if (Base.getOpcode() == ISD::FrameIndex) {
1330 if (N.getOpcode() == ISD::SUB)
1347 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1353 if (N.getOpcode() == ISD::SUB)
1358 if (Base.getOpcode() == ISD::FrameIndex) {
1374 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1379 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1391 if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
1396 if (Base.getOpcode() == ISD::FrameIndex) {
1402 if (N.getOpcode() == ISD::SUB)
1426 ISD::MemIndexedMode AM;
1428 case ISD::LOAD:
1431 case ISD::STORE:
1434 case ISD::MLOAD:
1437 case ISD::MSTORE:
1448 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1471 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1511 if (OffReg.getOpcode() == ISD::MUL && N.hasOneUse()) {
1534 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1546 if (Base.getOpcode() == ISD::FrameIndex) {
1570 ISD::MemIndexedMode AM = LD->getAddressingMode();
1571 if (AM == ISD::UNINDEXED)
1576 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1595 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1599 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1650 ISD::MemIndexedMode AM = LD->getAddressingMode();
1651 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD ||
1676 ISD::MemIndexedMode AM = LD->getAddressingMode();
1677 if (AM == ISD::UNINDEXED)
1681 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1683 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1735 ISD::MemIndexedMode AM = LD->getAddressingMode();
1736 if (AM == ISD::UNINDEXED)
1746 isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1747 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1751 ISD::MemIndexedMode AM = LD->getAddressingMode();
1752 if (AM == ISD::UNINDEXED)
1762 isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1763 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
3036 if (N->getOpcode() == ISD::AND) {
3037 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
3044 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
3071 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
3095 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
3117 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_imm) &&
3138 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3141 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
3142 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
3161 /// Target-specific DAG combining for ISD::XOR.
3179 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
3253 And->getOpcode() != ISD::AND)
3319 case ISD::STORE: {
3334 if (Ptr.getOpcode() == ISD::ADD &&
3338 if (Ptr.getOpcode() == ISD::CopyFromReg &&
3357 case ISD::WRITE_REGISTER:
3361 case ISD::READ_REGISTER:
3365 case ISD::INLINEASM:
3366 case ISD::INLINEASM_BR:
3370 case ISD::XOR:
3376 case ISD::Constant: {
3422 case ISD::FrameIndex: {
3446 case ISD::SRL:
3450 case ISD::SIGN_EXTEND_INREG:
3451 case ISD::SRA:
3455 case ISD::MUL:
3501 case ISD::AND: {
3565 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
3638 if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||
3664 case ISD::LOAD: {
3678 case ISD::MLOAD:
3779 assert(N1.getOpcode() == ISD::BasicBlock);
3780 assert(N2.getOpcode() == ISD::Constant);
3781 assert(N3.getOpcode() == ISD::Register);
3786 if (InFlag.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4273 case ISD::INTRINSIC_VOID:
4274 case ISD::INTRINSIC_W_CHAIN: {
4740 case ISD::INTRINSIC_WO_CHAIN: {
4917 case ISD::ATOMIC_CMP_SWAP: