Lines Matching refs:ISD
77 ISD::LoadExtType ExtType = LD->getExtensionType();
78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
134 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
139 if (ExtType == ISD::SEXTLOAD)
150 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
187 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
275 if (C->getOpcode() != ISD::INTRINSIC_W_CHAIN)
282 ISD::LoadExtType IntExt;
286 IntExt = ISD::ZEXTLOAD;
290 IntExt = ISD::NON_EXTLOAD;
293 IntExt = ISD::SEXTLOAD;
320 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
361 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
451 ISD::MemIndexedMode AM = LD->getAddressingMode();
452 if (AM != ISD::UNINDEXED) {
560 ISD::MemIndexedMode AM = ST->getAddressingMode();
561 if (AM != ISD::UNINDEXED) {
576 if (N->getValueType(0) != MVT::i32 || Shl_1.getOpcode() != ISD::Constant)
582 if (Shl_0.getOpcode() == ISD::MUL) {
599 if (Shl_0.getOpcode() == ISD::SUB) {
603 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
889 case ISD::Constant: return SelectConstant(N);
890 case ISD::ConstantFP: return SelectConstantFP(N);
891 case ISD::FrameIndex: return SelectFrameIndex(N);
892 case ISD::SHL: return SelectSHL(N);
893 case ISD::LOAD: return SelectLoad(N);
894 case ISD::STORE: return SelectStore(N);
895 case ISD::INTRINSIC_W_CHAIN: return SelectIntrinsicWChain(N);
896 case ISD::INTRINSIC_WO_CHAIN: return SelectIntrinsicWOChain(N);
911 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N);
951 case ISD::ADD:
952 case ISD::SUB:
953 case ISD::AND:
954 case ISD::OR:
973 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
989 if (I->getOpcode() != ISD::OR)
998 if (Op.getOpcode() != ISD::SELECT)
1009 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1015 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
1016 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1019 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
1020 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1037 if (I->getOpcode() != ISD::STORE)
1043 if (Off.getOpcode() != ISD::ADD)
1048 if (T0.getOpcode() != ISD::ADD)
1054 if (T1.getOpcode() != ISD::SHL)
1077 SDValue NewAdd = DAG.getNode(ISD::ADD, DL, VT, T1.getOperand(0), D);
1079 SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C);
1102 if (Opc != ISD::LOAD && Opc != ISD::STORE)
1104 SDValue Addr = Opc == ISD::LOAD ? N->getOperand(1) : N->getOperand(2);
1106 if (Addr.getOpcode() != ISD::ADD)
1110 if (T0.getOpcode() != ISD::AND)
1117 if (S.getOpcode() != ISD::SRL)
1154 SDValue NewSrl = DAG.getNode(ISD::SRL, dl, VT, Y, D);
1155 SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC);
1167 if (Opc != ISD::ZERO_EXTEND)
1212 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1,
1306 if (N.getOpcode() != ISD::FrameIndex)
1353 case ISD::Constant: {
1369 case ISD::ExternalSymbol:
1375 case ISD::BlockAddress:
1394 case ISD::ADD: {
1407 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1459 case ISD::SIGN_EXTEND:
1460 case ISD::SIGN_EXTEND_INREG: {
1462 EVT T = Opc == ISD::SIGN_EXTEND
1474 case ISD::LOAD: {
1476 if (L->getExtensionType() != ISD::SEXTLOAD)
1485 case ISD::SRA: {
1517 case ISD::SIGN_EXTEND:
1518 case ISD::ZERO_EXTEND:
1519 case ISD::ANY_EXTEND: {
1528 case ISD::SIGN_EXTEND_INREG:
1529 case ISD::AssertSext:
1530 case ISD::AssertZext:
1539 case ISD::AND: {
1556 case ISD::OR:
1557 case ISD::XOR: {
1604 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1620 case ISD::ADD:
1621 case ISD::MUL:
1623 case ISD::SHL:
1710 if (Opcode == ISD::MUL &&
1713 if (Opcode == ISD::ADD &&
1750 if (Val.getOpcode() != ISD::SHL ||
1777 if (Val.getOpcode() != ISD::MUL ||
1805 if (Val.getOpcode() == ISD::MUL) {
1817 if (Val.getOpcode() == ISD::SHL) {
1828 if (V.getOpcode() == ISD::MUL) {
1836 } else if (V.getOpcode() == ISD::SHL) {
1845 if (V.getOpcode() == ISD::MUL) {
1857 } else if (V.getOpcode() == ISD::SHL) {
1898 assert(!TopLevel || N->getOpcode() == ISD::ADD);
1948 if (NOpcode == ISD::SHL)
1949 NOpcode = ISD::MUL;
1960 ((isOpcodeHandled(Op0.getNode()) && Op0.getOpcode() == ISD::SHL &&
1962 (isOpcodeHandled(Op1.getNode()) && Op1.getOpcode() == ISD::SHL &&
1996 (Child.getOpcode() == ISD::MUL || Child.getOpcode() == ISD::SHL) &&
2032 (NOpcode == ISD::MUL && ChildOpcode == ISD::SHL));
2036 if (ChildOpcode == ISD::SHL)
2071 SDValue Sum = CurDAG->getNode(ISD::ADD, SDLoc(N), Mul1.Value.getValueType(),
2075 SDValue New = CurDAG->getNode(ISD::SHL, SDLoc(N), Mul1.Value.getValueType(),
2092 if (NOpcode == ISD::ADD && GA.Value.getNode() && Leaves.hasConst() &&
2128 if (NOpcode == ISD::ADD && GA.Value.getNode()) {
2132 GA.Value = CurDAG->getNode(ISD::ADD, SDLoc(GA.Value),
2193 if (V1C && NOpcode == ISD::MUL && V1C->getAPIntValue().isPowerOf2())
2195 ISD::SHL, SDLoc(V0), VT, V0,
2219 if (NewRoot.getOpcode() == ISD::MUL) {
2225 ISD::SHL, SDLoc(NewRoot), VT, V0,
2253 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
2257 if (BasePtr.getOpcode() != ISD::ADD)
2298 if (N->getOpcode() == ISD::LOAD)