Lines Matching refs:ISD
458 if (Opcode == ISD::TRUNCATE) {
462 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
474 if (Op0Code == ISD::Constant)
477 if (Op1Code == ISD::Constant)
525 if (Base->getOpcode() == ISD::FrameIndex)
555 if (IndexOpcode == ISD::SIGN_EXTEND ||
556 IndexOpcode == ISD::SIGN_EXTEND_INREG)
576 if (Addr.getOpcode() == ISD::Constant &&
633 else if (Base.getOpcode() == ISD::FrameIndex) {
642 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
709 if (Index.getOpcode() == ISD::ZERO_EXTEND)
711 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
725 if (Op.getOpcode() != ISD::AND)
776 case ISD::TRUNCATE: {
786 case ISD::AND: {
809 case ISD::OR: {
832 case ISD::ROTL: {
845 case ISD::ANY_EXTEND:
850 case ISD::ZERO_EXTEND:
862 case ISD::SIGN_EXTEND: {
880 case ISD::SHL: {
906 case ISD::SRL:
907 case ISD::SRA: {
917 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
965 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND &&
966 RISBG.Input.getOpcode() != ISD::TRUNCATE)
973 if (Count == 1 && N->getOpcode() != ISD::AND)
996 (Load->getExtensionType() == ISD::EXTLOAD ||
997 Load->getExtensionType() == ISD::ZEXTLOAD) &&
1008 SDValue New = CurDAG->getNode(ISD::AND, DL, VT, In, Mask);
1071 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND &&
1072 RxSBG[I].Input.getOpcode() != ISD::TRUNCATE)
1163 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, DL, VT, Op);
1211 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1256 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1261 if (!ISD::isNormalLoad(Load.getNode()))
1284 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1314 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1473 case ISD::OR:
1474 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1479 case ISD::XOR:
1480 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1489 Node->getOperand(0).getOpcode() != ISD::Constant)
1497 if (Val == (uint64_t)-1 && Opcode == ISD::XOR)
1498 if (ChildOpcode == ISD::AND || ChildOpcode == ISD::OR ||
1499 ChildOpcode == ISD::XOR)
1503 if (ChildOpcode == ISD::XOR) {
1518 case ISD::AND:
1519 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1523 case ISD::ROTL:
1524 case ISD::SHL:
1525 case ISD::SRL:
1526 case ISD::ZERO_EXTEND:
1531 case ISD::Constant:
1537 splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val),
1549 if ((Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) ||
1552 Op1.getOpcode() == ISD::Constant &&
1554 !(Op0.getOpcode() == ISD::Constant &&
1577 case ISD::INSERT_VECTOR_ELT: {
1590 case ISD::BUILD_VECTOR: {
1600 case ISD::ConstantFP: {
1611 case ISD::STORE: {
1677 if (Base.getOpcode() != ISD::TargetFrameIndex &&
1678 Base.getOpcode() != ISD::Register) {
1686 if (Index.getOpcode() != ISD::Register) {
1709 if (N.getOpcode() == ISD::LOAD && U->getOpcode() == SystemZISD::ICMP) {
1719 if (CCUser->getOpcode() == ISD::CopyToReg ||
1851 Result = CurDAG->getNode(ISD::XOR, DL, MVT::i32, Result,
1855 Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
1860 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA;
1865 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result);
1869 Result = CurDAG->getNode(ISD::SRL, DL, VT, Result,
1871 Result = CurDAG->getNode(ISD::AND, DL, VT, Result,
1877 Result = CurDAG->getNode(ISD::SHL, DL, VT, Result,
1879 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result,