Searched refs:CSR_READ_4 (Results 26 - 50 of 84) sorted by relevance

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/freebsd-11.0-release/sys/dev/stge/
H A Dif_stge.c517 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
998 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
1056 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1389 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1395 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1400 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1416 txstat = CSR_READ_4(sc, STGE_TxStatus);
1438 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1874 CSR_READ_4(sc,STGE_OctetRcvOk);
1876 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(s
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/freebsd-11.0-release/sys/dev/wb/
H A Dif_wb.c237 CSR_READ_4(sc, reg) | (x))
241 CSR_READ_4(sc, reg) & ~(x))
245 CSR_READ_4(sc, WB_SIO) | (x))
249 CSR_READ_4(sc, WB_SIO) & ~(x))
308 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
355 val = CSR_READ_4(sc, WB_SIO);
425 rxfilt = CSR_READ_4(sc, WB_NETCFG);
476 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
482 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
483 (CSR_READ_4(s
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/freebsd-11.0-release/sys/dev/age/
H A Dif_age.c222 v = CSR_READ_4(sc, AGE_MDIO);
252 v = CSR_READ_4(sc, AGE_MDIO);
343 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
359 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
372 ea[0] = CSR_READ_4(sc, AGE_PAR0);
373 ea[1] = CSR_READ_4(sc, AGE_PAR1);
499 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
523 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
524 CSR_READ_4(s
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/freebsd-11.0-release/sys/dev/ale/
H A Dif_ale.c214 v = CSR_READ_4(sc, ALE_MDIO);
241 v = CSR_READ_4(sc, ALE_MDIO);
291 reg = CSR_READ_4(sc, ALE_MAC_CFG);
364 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
392 ea[0] = CSR_READ_4(sc, ALE_PAR0);
393 ea[1] = CSR_READ_4(sc, ALE_PAR1);
493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
519 sc->ale_chip_rev = CSR_READ_4(s
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/freebsd-11.0-release/sys/dev/bm/
H A Dif_bmreg.h162 #define CSR_READ_4(sc, reg) \ macro
/freebsd-11.0-release/sys/dev/bwi/
H A Dif_bwi.c755 val = CSR_READ_4(sc, BWI_ID_HI);
789 info = CSR_READ_4(sc, BWI_INFO);
794 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
921 val = CSR_READ_4(sc, BWI_FLAGS);
978 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
980 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1067 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1080 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1128 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1251 if ((CSR_READ_4(s
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H A Dif_bwivar.h75 #define CSR_READ_4(sc, reg) \ macro
86 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
91 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
96 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
/freebsd-11.0-release/sys/dev/tx/
H A Dif_txvar.h136 #define CSR_READ_4(sc, reg) \ macro
H A Dif_tx.c871 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
883 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
1230 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1309 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1443 status = CSR_READ_4(sc, INTSTAT) &
1454 status = CSR_READ_4(sc, INTSTAT);
1530 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1535 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1811 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0)
1816 return (CSR_READ_4(s
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/freebsd-11.0-release/sys/arm/xscale/ixp425/
H A Dixp425_pci_space.c64 #define CSR_READ_4(x) *(volatile uint32_t *) \ macro
261 data = CSR_READ_4(PCI_NP_RDATA);
262 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
343 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
/freebsd-11.0-release/sys/dev/dc/
H A Dif_dc.c363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
366 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
377 CSR_READ_4(sc, DC_BUSCTL);
413 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
525 r = CSR_READ_4(sc, DC_SIO);
546 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
549 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
587 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
650 val = CSR_READ_4(sc, DC_SIO);
694 rval = CSR_READ_4(s
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/freebsd-11.0-release/sys/dev/altera/atse/
H A Dif_atse.c323 #define CSR_READ_4(sc, reg) \ macro
506 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
511 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
552 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
838 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
844 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
879 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG);
917 val4 = CSR_READ_4(sc, TX_CMD_STAT);
920 val4 = CSR_READ_4(sc, RX_CMD_STAT);
925 val4 = CSR_READ_4(s
[all...]
/freebsd-11.0-release/sys/arm/amlogic/aml8726/
H A Daml8726_mmc.c103 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) macro
429 while ((CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG) &
450 isr = CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG);
451 cmdr = CSR_READ_4(sc, AML_MMC_CMD_SEND_REG);
502 resp = CSR_READ_4(sc, AML_MMC_CMD_ARGUMENT_REG);
508 sc->cmd->resp[0] = CSR_READ_4(sc,
530 while ((CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG) &
/freebsd-11.0-release/sys/dev/my/
H A Dif_my.c142 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
143 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
177 miir = CSR_READ_4(sc, MY_MANAGEMENT);
242 miir = CSR_READ_4(sc, MY_MANAGEMENT);
321 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
723 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
728 if (!(CSR_READ_4(sc, MY_TCRRCR) &
760 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
1212 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1233 if (CSR_READ_4(s
[all...]
/freebsd-11.0-release/sys/dev/tl/
H A Dif_tlreg.h468 #define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg) macro
477 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
479 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))
H A Dif_tl.c407 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
980 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1581 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1602 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1723 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1724 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1725 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1726 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1727 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1946 cmd = CSR_READ_4(s
[all...]
/freebsd-11.0-release/sys/dev/jme/
H A Dif_jmevar.h232 #define CSR_READ_4(_sc, reg) \ macro
/freebsd-11.0-release/sys/dev/fxp/
H A Dif_fxpvar.h246 #define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg) macro
/freebsd-11.0-release/sys/dev/ipw/
H A Dif_ipw.c1250 r = CSR_READ_4(sc, IPW_CSR_RX_READ);
1346 r = CSR_READ_4(sc, IPW_CSR_TX_READ);
1383 r = CSR_READ_4(sc, IPW_CSR_INTR);
1806 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)
1813 tmp = CSR_READ_4(sc, IPW_CSR_RST);
1829 tmp = CSR_READ_4(sc, IPW_CSR_CTL);
1834 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY)
1841 tmp = CSR_READ_4(sc, IPW_CSR_RST);
1846 tmp = CSR_READ_4(sc, IPW_CSR_CTL);
1988 tmp = CSR_READ_4(s
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H A Dif_ipwreg.h331 #define CSR_READ_4(sc, reg) \ macro
356 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA))
/freebsd-11.0-release/sys/dev/ti/
H A Dif_ti.c317 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
351 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
359 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
371 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
382 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
553 origwin = CSR_READ_4(sc, TI_WINBASE);
727 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
1966 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
2009 if (!(CSR_READ_4(s
[all...]
/freebsd-11.0-release/sys/mips/idt/
H A Dif_kr.c415 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
424 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
433 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
440 if (CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_NV)
444 result = CSR_READ_4(sc , KR_MIIMRDD);
457 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
466 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
475 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
530 if (!(CSR_READ_4(sc, KR_ETHINTFC) & ETH_INTFC_RIP))
/freebsd-11.0-release/sys/dev/sge/
H A Dif_sge.c186 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg) macro
221 val = CSR_READ_4(sc, ROMInterface);
342 val = CSR_READ_4(sc, GMIIControl);
367 val = CSR_READ_4(sc, GMIIControl);
417 ctl = CSR_READ_4(sc, StationControl);
512 CSR_READ_4(sc, IntrControl);
1338 status = CSR_READ_4(sc, IntrStatus);
1369 status = CSR_READ_4(sc, IntrStatus);
1890 CSR_READ_4(sc, IntrMask);
/freebsd-11.0-release/sys/dev/iwi/
H A Dif_iwi.c250 return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA);
926 iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE));
1562 hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);
1604 hw = CSR_READ_4(sc, txq->csr_ridx);
1656 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) {
2079 if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)
2086 tmp = CSR_READ_4(sc, IWI_CSR_RST);
2100 tmp = CSR_READ_4(sc, IWI_CSR_CTL);
2107 if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY)
2117 tmp = CSR_READ_4(s
[all...]
/freebsd-11.0-release/sys/dev/bfe/
H A Dif_bfereg.h444 #define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg) macro
449 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
452 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)

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