dev/bwi/if_bwi.c

755 	val = CSR_READ_4(sc, BWI_ID_HI);
789 		info = CSR_READ_4(sc, BWI_INFO);
794 		sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
921 		val = CSR_READ_4(sc, BWI_FLAGS);
978 			CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
980 			CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1067 		val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1080 		val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1128 	clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1251 			if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1254 			CSR_READ_4(sc, BWI_TXSTATUS1);
1475 		CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1523 	intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1531 	intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1552 		CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1616 			if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
2706 	val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2737 		status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2793 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2810 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
3299 	val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3411 		tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3414 		tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3464 	val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3515 	busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3533 	val = CSR_READ_4(sc, BWI_STATE_LO);
3554 	state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3578 		state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3591 		state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3611 	CSR_READ_4(sc, BWI_STATE_LO);
3620 	CSR_READ_4(sc, BWI_STATE_LO);
3639 	CSR_READ_4(sc, BWI_STATE_LO);
3642 	state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3646 	imstate = CSR_READ_4(sc, BWI_IMSTATE);
3659 	CSR_READ_4(sc, BWI_STATE_LO);
3668 	CSR_READ_4(sc, BWI_STATE_LO);