dev/dc/if_dc.c

363 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
366 	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
377 		CSR_READ_4(sc, DC_BUSCTL);
413 		if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
525 		r = CSR_READ_4(sc, DC_SIO);
546 	*dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
549 	*dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
587 		if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
650 	val = CSR_READ_4(sc, DC_SIO);
694 			rval = CSR_READ_4(sc, DC_PN_MII);
710 			rval = CSR_READ_4(sc, DC_ROM);
749 		rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
756 		phy_reg = CSR_READ_4(sc, DC_NETCFG);
778 			if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
829 		phy_reg = CSR_READ_4(sc, DC_NETCFG);
1204 	filter = CSR_READ_4(sc, DC_NETCFG);
1359 		isr = CSR_READ_4(sc, DC_ISR);
1391 	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1403 				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1436 				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1511 		if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
2291 		reg = CSR_READ_4(sc, DC_AL_PAR0);
2297 		reg = CSR_READ_4(sc, DC_AL_PAR1);
2334 				mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);
3106 			r = CSR_READ_4(sc, DC_10BTSTAT);
3124 			if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
3171 	netcfg = CSR_READ_4(sc, DC_NETCFG);
3193 				isr = CSR_READ_4(sc, DC_ISR);
3246 		status = CSR_READ_4(sc, DC_ISR);
3258 			uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3296 	status = CSR_READ_4(sc, DC_ISR);
3340 			r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3357 		status = CSR_READ_4(sc, DC_ISR);
3766 	CSR_READ_4(sc, DC_FRAMESDISCARDED);
3975 	netcfg = CSR_READ_4(sc, DC_NETCFG);