Lines Matching refs:CSR_READ_4
317 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
342 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
351 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
359 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
371 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
382 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
553 origwin = CSR_READ_4(sc, TI_WINBASE);
727 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu));
1966 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
2009 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
2013 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
2051 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
2060 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
2102 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
2110 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
2125 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
2985 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
3479 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
3489 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
3759 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START);
3760 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR);
3761 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN);