dev/age/if_age.c

222 		v = CSR_READ_4(sc, AGE_MDIO);
252 		v = CSR_READ_4(sc, AGE_MDIO);
343 	reg = CSR_READ_4(sc, AGE_SPI_CTRL);
355 		CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
359 			reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
372 	ea[0] = CSR_READ_4(sc, AGE_PAR0);
373 	ea[1] = CSR_READ_4(sc, AGE_PAR1);
499 	sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
523 	    CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
524 	    CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
1426 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
1884 			reg = CSR_READ_4(sc, AGE_MAC_CFG);
1938 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2004 		reg = CSR_READ_4(sc, AGE_MAC_CFG);
2006 		CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2122 	status = CSR_READ_4(sc, AGE_INTR_STATUS);
2542 	CSR_READ_4(sc, AGE_MASTER_CFG);
2545 		if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2554 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2673 	reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2714 		CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2734 		reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2741 		reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2829 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2881 	    CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2884 	    CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2886 	    CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2888 		if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2935 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2941 	reg = CSR_READ_4(sc, AGE_DMA_CFG);
2947 		if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2964 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2970 	reg = CSR_READ_4(sc, AGE_DMA_CFG);
2976 		if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
3137 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
3157 	rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);