Searched refs:RC (Results 201 - 225 of 324) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h186 const TargetRegisterClass *RC,
195 const TargetRegisterClass *RC,
H A DHexagonStoreWidening.cpp444 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF); local
445 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
H A DHexagonFrameLowering.h161 const TargetRegisterClass *RC) const;
H A DHexagonExpandCondsets.cpp594 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); local
595 switch (TRI->getRegSizeInBits(*RC)) {
1097 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); local
1098 if (RC == &Hexagon::IntRegsRegClass) {
1102 if (RC == &Hexagon::DoubleRegsRegClass) {
H A DHexagonInstrInfo.cpp886 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
897 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
901 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
905 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
909 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
913 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
917 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
921 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
932 int FI, const TargetRegisterClass *RC,
943 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
884 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
930 loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1628 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg()); local
[all...]
H A DHexagonHardwareLoops.cpp895 const TargetRegisterClass *RC = MRI->getRegClass(R); local
898 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
1589 const TargetRegisterClass *RC = MRI->getRegClass(R); local
1590 Register NewR = MRI->createVirtualRegister(RC);
1908 const TargetRegisterClass *RC = MRI->getRegClass(PR); local
1909 Register NewPR = MRI->createVirtualRegister(RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp136 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); local
137 unsigned RegSize = TRI.getRegSizeInBits(*RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp88 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); local
89 for (const MCPhysReg Reg : RC) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp1361 const TargetRegisterClass *RC = local
1364 Register Reg = MRI->createVirtualRegister(RC);
1486 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1488 MRI->constrainRegClass(DstReg, RC);
1557 const TargetRegisterClass *RC = MRI->getRegClass(RegB); local
1560 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1564 RC = nullptr;
1601 MRI->constrainRegClass(RegA, RC);
H A DTailDuplicator.cpp355 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); local
360 Register NewDef = MRI->createVirtualRegister(RC);
398 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
399 Register NewReg = MRI->createVirtualRegister(RC);
H A DMachineFunction.cpp612 const TargetRegisterClass *RC) {
622 // physical register and is a sub class of the specified RC.
623 assert((VRegRC == RC || (VRegRC->contains(PReg) &&
624 RC->hasSubClassEq(VRegRC))) &&
628 VReg = MRI.createVirtualRegister(RC);
611 addLiveIn(unsigned PReg, const TargetRegisterClass *RC) argument
H A DMachineLICM.cpp896 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
898 RegClassWeight W = TRI->getRegClassWeight(RC);
912 const int *PS = TRI->getRegClassPressureSets(RC);
1340 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); local
1342 Register Reg = MRI->createVirtualRegister(RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp362 const TargetRegisterClass *RC,
384 const TargetRegisterClass *RC,
358 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
381 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp397 static bool getSubRegForClass(const TargetRegisterClass *RC, argument
399 switch (TRI.getRegSizeInBits(*RC)) {
407 if (RC != &AArch64::FPR32RegClass)
1152 const TargetRegisterClass *RC = nullptr; local
1156 RC = &AArch64::FPR128RegClass;
1160 RC = &AArch64::FPR128RegClass;
1164 RC = &AArch64::FPR64RegClass;
1171 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
3133 const TargetRegisterClass *RC = local
3135 if (!RC) {
3944 const TargetRegisterClass *RC = local
4009 const TargetRegisterClass *RC = local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp318 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument
319 addRegisterClass(Ty, RC);
372 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument
373 addRegisterClass(Ty, RC);
3039 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
3068 Register VR2 = RegInfo.createVirtualRegister(RC);
3074 Register VR1 = RegInfo.createVirtualRegister(RC);
3108 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
3137 Register RD1 = RegInfo.createVirtualRegister(RC);
3143 Register RD2 = RegInfo.createVirtualRegister(RC);
3523 const TargetRegisterClass *RC = local
3575 const TargetRegisterClass *RC = local
3822 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; local
3851 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; local
[all...]
/freebsd-11-stable/usr.bin/tip/tip/
H A Dtip.h89 EXTERN char *RC; /* raise character */ variable
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h63 const TargetRegisterClass *RC; member in union:llvm::DstOp::__anon1456
72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
83 MIB.addDef(MRI.createVirtualRegister(RC));
108 return RC;
110 llvm_unreachable("Not a RC Operand");
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h340 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
978 const TargetRegisterClass *RC,
990 const TargetRegisterClass *RC,
1348 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
975 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
987 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp567 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); local
573 Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
574 Register PromotedReg1 = RegInfo.createVirtualRegister(RC);
575 Register PromotedReg2 = RegInfo.createVirtualRegister(RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp573 const TargetRegisterClass *RC = local
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
577 // If cross copy register class is the same as RC, then it must be
579 // If cross copy register class is not the same as RC, then it's
585 if (DestRC != RC) {
594 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp29 for (const auto &RC : T.getRegBank().getRegClasses()) {
30 if (!RC.contains(Reg))
35 const ValueTypeByHwMode &VVT = RC.getValueTypeNum(0);
43 const ValueTypeByHwMode &T = RC.getValueTypeNum(0);
H A DAsmMatcherEmitter.cpp1224 for (const CodeGenRegisterClass &RC : RegClassList)
1226 RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1297 for (const CodeGenRegisterClass &RC : RegClassList) {
1299 Record *Def = RC.getDef();
1302 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1303 RC.getOrder().end())];
1305 CI->ClassName = RC.getName();
1306 CI->Name = "MCK_" + RC.getName();
1307 CI->ValueName = RC
[all...]
H A DRISCVCompressInstEmitter.cpp144 CodeGenRegisterClass RC = Target.getRegisterClass(RegClass); local
148 return RC.contains(R);
163 CodeGenRegisterClass RC = Target.getRegisterClass(InstOpType); local
165 return RC.hasSubClass(&SubRC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1418 const TargetRegisterClass *RC; local
1420 std::tie(InputPtrReg, RC)
1567 const TargetRegisterClass *RC; local
1569 std::tie(Reg, RC) = MFI.getPreloadedValue(PVID);
1570 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1685 const TargetRegisterClass *RC,
1687 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1697 MF.addLiveIn(Reg, RC);
2005 const TargetRegisterClass *RC = nullptr; local
2007 RC
1684 allocateSGPR32InputImpl(CCState &CCInfo, const TargetRegisterClass *RC, unsigned NumArgRegs) argument
2177 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); local
10375 const TargetRegisterClass *RC = local
10466 auto *RC = TRI->getRegClassForReg(MRI, Op.getReg()); local
10593 const TargetRegisterClass *RC = nullptr; local
10994 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false); local
11083 const TargetRegisterClass *RC; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp1435 const TargetRegisterClass * RC; local
1440 RC = &MSP430::GR8RegClass;
1444 RC = &MSP430::GR16RegClass;
1448 RC = &MSP430::GR8RegClass;
1452 RC = &MSP430::GR16RegClass;
1457 RC = &MSP430::GR8RegClass;
1462 RC = &MSP430::GR16RegClass;
1503 Register ShiftReg = RI.createVirtualRegister(RC);
1504 Register ShiftReg2 = RI.createVirtualRegister(RC);

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