1327952Sdim//===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===// 2277323Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6277323Sdim// 7277323Sdim//===----------------------------------------------------------------------===// 8277323Sdim// 9277323Sdim// This file contains support for writing dwarf debug info into asm files. 10277323Sdim// 11277323Sdim//===----------------------------------------------------------------------===// 12277323Sdim 13277323Sdim#include "DwarfExpression.h" 14353358Sdim#include "DwarfCompileUnit.h" 15327952Sdim#include "llvm/ADT/APInt.h" 16277323Sdim#include "llvm/ADT/SmallBitVector.h" 17321369Sdim#include "llvm/BinaryFormat/Dwarf.h" 18360784Sdim#include "llvm/CodeGen/Register.h" 19327952Sdim#include "llvm/CodeGen/TargetRegisterInfo.h" 20327952Sdim#include "llvm/IR/DebugInfoMetadata.h" 21327952Sdim#include "llvm/Support/ErrorHandling.h" 22327952Sdim#include <algorithm> 23327952Sdim#include <cassert> 24327952Sdim#include <cstdint> 25277323Sdim 26277323Sdimusing namespace llvm; 27277323Sdim 28344779Sdimvoid DwarfExpression::emitConstu(uint64_t Value) { 29344779Sdim if (Value < 32) 30344779Sdim emitOp(dwarf::DW_OP_lit0 + Value); 31344779Sdim else if (Value == std::numeric_limits<uint64_t>::max()) { 32344779Sdim // Only do this for 64-bit values as the DWARF expression stack uses 33344779Sdim // target-address-size values. 34344779Sdim emitOp(dwarf::DW_OP_lit0); 35344779Sdim emitOp(dwarf::DW_OP_not); 36344779Sdim } else { 37344779Sdim emitOp(dwarf::DW_OP_constu); 38344779Sdim emitUnsigned(Value); 39344779Sdim } 40344779Sdim} 41344779Sdim 42321369Sdimvoid DwarfExpression::addReg(int DwarfReg, const char *Comment) { 43321369Sdim assert(DwarfReg >= 0 && "invalid negative dwarf register number"); 44353358Sdim assert((isUnknownLocation() || isRegisterLocation()) && 45321369Sdim "location description already locked down"); 46321369Sdim LocationKind = Register; 47321369Sdim if (DwarfReg < 32) { 48321369Sdim emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment); 49277323Sdim } else { 50321369Sdim emitOp(dwarf::DW_OP_regx, Comment); 51321369Sdim emitUnsigned(DwarfReg); 52277323Sdim } 53277323Sdim} 54277323Sdim 55321369Sdimvoid DwarfExpression::addBReg(int DwarfReg, int Offset) { 56277323Sdim assert(DwarfReg >= 0 && "invalid negative dwarf register number"); 57353358Sdim assert(!isRegisterLocation() && "location description already locked down"); 58277323Sdim if (DwarfReg < 32) { 59321369Sdim emitOp(dwarf::DW_OP_breg0 + DwarfReg); 60277323Sdim } else { 61321369Sdim emitOp(dwarf::DW_OP_bregx); 62321369Sdim emitUnsigned(DwarfReg); 63277323Sdim } 64321369Sdim emitSigned(Offset); 65277323Sdim} 66277323Sdim 67321369Sdimvoid DwarfExpression::addFBReg(int Offset) { 68321369Sdim emitOp(dwarf::DW_OP_fbreg); 69321369Sdim emitSigned(Offset); 70321369Sdim} 71321369Sdim 72321369Sdimvoid DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) { 73314564Sdim if (!SizeInBits) 74314564Sdim return; 75314564Sdim 76277323Sdim const unsigned SizeOfByte = 8; 77277323Sdim if (OffsetInBits > 0 || SizeInBits % SizeOfByte) { 78321369Sdim emitOp(dwarf::DW_OP_bit_piece); 79321369Sdim emitUnsigned(SizeInBits); 80321369Sdim emitUnsigned(OffsetInBits); 81277323Sdim } else { 82321369Sdim emitOp(dwarf::DW_OP_piece); 83277323Sdim unsigned ByteSize = SizeInBits / SizeOfByte; 84321369Sdim emitUnsigned(ByteSize); 85277323Sdim } 86314564Sdim this->OffsetInBits += SizeInBits; 87277323Sdim} 88277323Sdim 89321369Sdimvoid DwarfExpression::addShr(unsigned ShiftBy) { 90344779Sdim emitConstu(ShiftBy); 91321369Sdim emitOp(dwarf::DW_OP_shr); 92277323Sdim} 93277323Sdim 94321369Sdimvoid DwarfExpression::addAnd(unsigned Mask) { 95344779Sdim emitConstu(Mask); 96321369Sdim emitOp(dwarf::DW_OP_and); 97277323Sdim} 98277323Sdim 99321369Sdimbool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI, 100314564Sdim unsigned MachineReg, unsigned MaxSize) { 101360784Sdim if (!llvm::Register::isPhysicalRegister(MachineReg)) { 102321369Sdim if (isFrameRegister(TRI, MachineReg)) { 103321369Sdim DwarfRegs.push_back({-1, 0, nullptr}); 104321369Sdim return true; 105321369Sdim } 106288943Sdim return false; 107321369Sdim } 108277323Sdim 109288943Sdim int Reg = TRI.getDwarfRegNum(MachineReg, false); 110288943Sdim 111277323Sdim // If this is a valid register number, emit it. 112277323Sdim if (Reg >= 0) { 113321369Sdim DwarfRegs.push_back({Reg, 0, nullptr}); 114277323Sdim return true; 115277323Sdim } 116277323Sdim 117277323Sdim // Walk up the super-register chain until we find a valid number. 118314564Sdim // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0. 119288943Sdim for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { 120288943Sdim Reg = TRI.getDwarfRegNum(*SR, false); 121277323Sdim if (Reg >= 0) { 122288943Sdim unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); 123288943Sdim unsigned Size = TRI.getSubRegIdxSize(Idx); 124288943Sdim unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); 125321369Sdim DwarfRegs.push_back({Reg, 0, "super-register"}); 126314564Sdim // Use a DW_OP_bit_piece to describe the sub-register. 127314564Sdim setSubRegisterPiece(Size, RegOffset); 128277323Sdim return true; 129277323Sdim } 130277323Sdim } 131277323Sdim 132277323Sdim // Otherwise, attempt to find a covering set of sub-register numbers. 133277323Sdim // For example, Q0 on ARM is a composition of D0+D1. 134314564Sdim unsigned CurPos = 0; 135321369Sdim // The size of the register in bits. 136321369Sdim const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); 137321369Sdim unsigned RegSize = TRI.getRegSizeInBits(*RC); 138277323Sdim // Keep track of the bits in the register we already emitted, so we 139341825Sdim // can avoid emitting redundant aliasing subregs. Because this is 140341825Sdim // just doing a greedy scan of all subregisters, it is possible that 141341825Sdim // this doesn't find a combination of subregisters that fully cover 142341825Sdim // the register (even though one may exist). 143277323Sdim SmallBitVector Coverage(RegSize, false); 144288943Sdim for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { 145288943Sdim unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); 146288943Sdim unsigned Size = TRI.getSubRegIdxSize(Idx); 147288943Sdim unsigned Offset = TRI.getSubRegIdxOffset(Idx); 148288943Sdim Reg = TRI.getDwarfRegNum(*SR, false); 149327952Sdim if (Reg < 0) 150327952Sdim continue; 151277323Sdim 152277323Sdim // Intersection between the bits we already emitted and the bits 153277323Sdim // covered by this subregister. 154326496Sdim SmallBitVector CurSubReg(RegSize, false); 155326496Sdim CurSubReg.set(Offset, Offset + Size); 156277323Sdim 157277323Sdim // If this sub-register has a DWARF number and we haven't covered 158360784Sdim // its range, and its range covers the value, emit a DWARF piece for it. 159360784Sdim if (Offset < MaxSize && CurSubReg.test(Coverage)) { 160321369Sdim // Emit a piece for any gap in the coverage. 161321369Sdim if (Offset > CurPos) 162360784Sdim DwarfRegs.push_back( 163360784Sdim {-1, Offset - CurPos, "no DWARF register encoding"}); 164321369Sdim DwarfRegs.push_back( 165321369Sdim {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"}); 166277323Sdim } 167360784Sdim // Mark it as emitted. 168360784Sdim Coverage.set(Offset, Offset + Size); 169360784Sdim CurPos = Offset + Size; 170277323Sdim } 171341825Sdim // Failed to find any DWARF encoding. 172341825Sdim if (CurPos == 0) 173341825Sdim return false; 174341825Sdim // Found a partial or complete DWARF encoding. 175341825Sdim if (CurPos < RegSize) 176341825Sdim DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"}); 177341825Sdim return true; 178277323Sdim} 179277323Sdim 180321369Sdimvoid DwarfExpression::addStackValue() { 181288943Sdim if (DwarfVersion >= 4) 182321369Sdim emitOp(dwarf::DW_OP_stack_value); 183277323Sdim} 184277323Sdim 185321369Sdimvoid DwarfExpression::addSignedConstant(int64_t Value) { 186353358Sdim assert(isImplicitLocation() || isUnknownLocation()); 187321369Sdim LocationKind = Implicit; 188321369Sdim emitOp(dwarf::DW_OP_consts); 189321369Sdim emitSigned(Value); 190309124Sdim} 191309124Sdim 192321369Sdimvoid DwarfExpression::addUnsignedConstant(uint64_t Value) { 193353358Sdim assert(isImplicitLocation() || isUnknownLocation()); 194321369Sdim LocationKind = Implicit; 195344779Sdim emitConstu(Value); 196277323Sdim} 197277323Sdim 198321369Sdimvoid DwarfExpression::addUnsignedConstant(const APInt &Value) { 199353358Sdim assert(isImplicitLocation() || isUnknownLocation()); 200321369Sdim LocationKind = Implicit; 201321369Sdim 202309124Sdim unsigned Size = Value.getBitWidth(); 203309124Sdim const uint64_t *Data = Value.getRawData(); 204309124Sdim 205309124Sdim // Chop it up into 64-bit pieces, because that's the maximum that 206321369Sdim // addUnsignedConstant takes. 207309124Sdim unsigned Offset = 0; 208309124Sdim while (Offset < Size) { 209321369Sdim addUnsignedConstant(*Data++); 210309124Sdim if (Offset == 0 && Size <= 64) 211309124Sdim break; 212321369Sdim addStackValue(); 213321369Sdim addOpPiece(std::min(Size - Offset, 64u), Offset); 214309124Sdim Offset += 64; 215309124Sdim } 216309124Sdim} 217309124Sdim 218321369Sdimbool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI, 219314564Sdim DIExpressionCursor &ExprCursor, 220277323Sdim unsigned MachineReg, 221314564Sdim unsigned FragmentOffsetInBits) { 222321369Sdim auto Fragment = ExprCursor.getFragmentInfo(); 223321369Sdim if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) { 224321369Sdim LocationKind = Unknown; 225321369Sdim return false; 226321369Sdim } 227288943Sdim 228321369Sdim bool HasComplexExpression = false; 229314564Sdim auto Op = ExprCursor.peek(); 230321369Sdim if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment) 231321369Sdim HasComplexExpression = true; 232321369Sdim 233321369Sdim // If the register can only be described by a complex expression (i.e., 234321369Sdim // multiple subregisters) it doesn't safely compose with another complex 235321369Sdim // expression. For example, it is not possible to apply a DW_OP_deref 236321369Sdim // operation to multiple DW_OP_pieces. 237321369Sdim if (HasComplexExpression && DwarfRegs.size() > 1) { 238321369Sdim DwarfRegs.clear(); 239321369Sdim LocationKind = Unknown; 240321369Sdim return false; 241288943Sdim } 242321369Sdim 243360784Sdim // Handle simple register locations. If we are supposed to emit 244360784Sdim // a call site parameter expression and if that expression is just a register 245360784Sdim // location, emit it with addBReg and offset 0, because we should emit a DWARF 246360784Sdim // expression representing a value, rather than a location. 247360784Sdim if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() || 248360784Sdim isEntryValue())) { 249321369Sdim for (auto &Reg : DwarfRegs) { 250321369Sdim if (Reg.DwarfRegNo >= 0) 251321369Sdim addReg(Reg.DwarfRegNo, Reg.Comment); 252321369Sdim addOpPiece(Reg.Size); 253321369Sdim } 254353358Sdim 255360784Sdim if (isEntryValue()) 256360784Sdim finalizeEntryValue(); 257360784Sdim 258360784Sdim if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4) 259353358Sdim emitOp(dwarf::DW_OP_stack_value); 260353358Sdim 261321369Sdim DwarfRegs.clear(); 262321369Sdim return true; 263288943Sdim } 264321369Sdim 265321369Sdim // Don't emit locations that cannot be expressed without DW_OP_stack_value. 266321369Sdim if (DwarfVersion < 4) 267344779Sdim if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool { 268344779Sdim return Op.getOp() == dwarf::DW_OP_stack_value; 269344779Sdim })) { 270321369Sdim DwarfRegs.clear(); 271321369Sdim LocationKind = Unknown; 272321369Sdim return false; 273321369Sdim } 274321369Sdim 275321369Sdim assert(DwarfRegs.size() == 1); 276321369Sdim auto Reg = DwarfRegs[0]; 277321369Sdim bool FBReg = isFrameRegister(TRI, MachineReg); 278321369Sdim int SignedOffset = 0; 279321369Sdim assert(Reg.Size == 0 && "subregister has same size as superregister"); 280321369Sdim 281321369Sdim // Pattern-match combinations for which more efficient representations exist. 282321369Sdim // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset]. 283321369Sdim if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) { 284360784Sdim uint64_t Offset = Op->getArg(0); 285360784Sdim uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max()); 286360784Sdim if (Offset <= IntMax) { 287360784Sdim SignedOffset = Offset; 288360784Sdim ExprCursor.take(); 289360784Sdim } 290288943Sdim } 291277323Sdim 292321369Sdim // [Reg, DW_OP_constu, Offset, DW_OP_plus] --> [DW_OP_breg, Offset] 293321369Sdim // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset] 294321369Sdim // If Reg is a subregister we need to mask it out before subtracting. 295321369Sdim if (Op && Op->getOp() == dwarf::DW_OP_constu) { 296360784Sdim uint64_t Offset = Op->getArg(0); 297360784Sdim uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max()); 298321369Sdim auto N = ExprCursor.peekNext(); 299360784Sdim if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) { 300360784Sdim SignedOffset = Offset; 301321369Sdim ExprCursor.consume(2); 302360784Sdim } else if (N && N->getOp() == dwarf::DW_OP_minus && 303360784Sdim !SubRegisterSizeInBits && Offset <= IntMax + 1) { 304360784Sdim SignedOffset = -static_cast<int64_t>(Offset); 305360784Sdim ExprCursor.consume(2); 306321369Sdim } 307321369Sdim } 308321369Sdim 309321369Sdim if (FBReg) 310321369Sdim addFBReg(SignedOffset); 311321369Sdim else 312321369Sdim addBReg(Reg.DwarfRegNo, SignedOffset); 313321369Sdim DwarfRegs.clear(); 314321369Sdim return true; 315277323Sdim} 316277323Sdim 317360784Sdimvoid DwarfExpression::beginEntryValueExpression( 318360784Sdim DIExpressionCursor &ExprCursor) { 319353358Sdim auto Op = ExprCursor.take(); 320360784Sdim (void)Op; 321360784Sdim assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value); 322353358Sdim assert(!isMemoryLocation() && 323353358Sdim "We don't support entry values of memory locations yet"); 324360784Sdim assert(!IsEmittingEntryValue && "Already emitting entry value?"); 325360784Sdim assert(Op->getArg(0) == 1 && 326360784Sdim "Can currently only emit entry values covering a single operation"); 327353358Sdim 328360784Sdim emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value)); 329360784Sdim IsEmittingEntryValue = true; 330360784Sdim enableTemporaryBuffer(); 331353358Sdim} 332353358Sdim 333360784Sdimvoid DwarfExpression::finalizeEntryValue() { 334360784Sdim assert(IsEmittingEntryValue && "Entry value not open?"); 335360784Sdim disableTemporaryBuffer(); 336360784Sdim 337360784Sdim // Emit the entry value's size operand. 338360784Sdim unsigned Size = getTemporaryBufferSize(); 339360784Sdim emitUnsigned(Size); 340360784Sdim 341360784Sdim // Emit the entry value's DWARF block operand. 342360784Sdim commitTemporaryBuffer(); 343360784Sdim 344360784Sdim IsEmittingEntryValue = false; 345360784Sdim} 346360784Sdim 347321369Sdim/// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?". 348321369Sdimstatic bool isMemoryLocation(DIExpressionCursor ExprCursor) { 349321369Sdim while (ExprCursor) { 350321369Sdim auto Op = ExprCursor.take(); 351321369Sdim switch (Op->getOp()) { 352321369Sdim case dwarf::DW_OP_deref: 353321369Sdim case dwarf::DW_OP_LLVM_fragment: 354321369Sdim break; 355321369Sdim default: 356321369Sdim return false; 357321369Sdim } 358321369Sdim } 359321369Sdim return true; 360321369Sdim} 361321369Sdim 362321369Sdimvoid DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor, 363314564Sdim unsigned FragmentOffsetInBits) { 364321369Sdim // If we need to mask out a subregister, do it now, unless the next 365321369Sdim // operation would emit an OpPiece anyway. 366321369Sdim auto N = ExprCursor.peek(); 367321369Sdim if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment)) 368321369Sdim maskSubRegister(); 369321369Sdim 370353358Sdim Optional<DIExpression::ExprOperand> PrevConvertOp = None; 371353358Sdim 372314564Sdim while (ExprCursor) { 373314564Sdim auto Op = ExprCursor.take(); 374360784Sdim uint64_t OpNum = Op->getOp(); 375360784Sdim 376360784Sdim if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) { 377360784Sdim emitOp(OpNum); 378360784Sdim continue; 379360784Sdim } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) { 380360784Sdim addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0)); 381360784Sdim continue; 382360784Sdim } 383360784Sdim 384360784Sdim switch (OpNum) { 385314564Sdim case dwarf::DW_OP_LLVM_fragment: { 386314564Sdim unsigned SizeInBits = Op->getArg(1); 387314564Sdim unsigned FragmentOffset = Op->getArg(0); 388314564Sdim // The fragment offset must have already been adjusted by emitting an 389314564Sdim // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base 390314564Sdim // location. 391314564Sdim assert(OffsetInBits >= FragmentOffset && "fragment offset not added?"); 392360784Sdim assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow"); 393314564Sdim 394321369Sdim // If addMachineReg already emitted DW_OP_piece operations to represent 395314564Sdim // a super-register by splicing together sub-registers, subtract the size 396314564Sdim // of the pieces that was already emitted. 397314564Sdim SizeInBits -= OffsetInBits - FragmentOffset; 398314564Sdim 399321369Sdim // If addMachineReg requested a DW_OP_bit_piece to stencil out a 400314564Sdim // sub-register that is smaller than the current fragment's size, use it. 401314564Sdim if (SubRegisterSizeInBits) 402314564Sdim SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits); 403321369Sdim 404321369Sdim // Emit a DW_OP_stack_value for implicit location descriptions. 405353358Sdim if (isImplicitLocation()) 406321369Sdim addStackValue(); 407321369Sdim 408321369Sdim // Emit the DW_OP_piece. 409321369Sdim addOpPiece(SizeInBits, SubRegisterOffsetInBits); 410314564Sdim setSubRegisterPiece(0, 0); 411321369Sdim // Reset the location description kind. 412321369Sdim LocationKind = Unknown; 413321369Sdim return; 414321369Sdim } 415321369Sdim case dwarf::DW_OP_plus_uconst: 416353358Sdim assert(!isRegisterLocation()); 417321369Sdim emitOp(dwarf::DW_OP_plus_uconst); 418321369Sdim emitUnsigned(Op->getArg(0)); 419277323Sdim break; 420277323Sdim case dwarf::DW_OP_plus: 421296417Sdim case dwarf::DW_OP_minus: 422327952Sdim case dwarf::DW_OP_mul: 423341825Sdim case dwarf::DW_OP_div: 424341825Sdim case dwarf::DW_OP_mod: 425341825Sdim case dwarf::DW_OP_or: 426341825Sdim case dwarf::DW_OP_and: 427341825Sdim case dwarf::DW_OP_xor: 428341825Sdim case dwarf::DW_OP_shl: 429341825Sdim case dwarf::DW_OP_shr: 430341825Sdim case dwarf::DW_OP_shra: 431341825Sdim case dwarf::DW_OP_lit0: 432341825Sdim case dwarf::DW_OP_not: 433341825Sdim case dwarf::DW_OP_dup: 434360784Sdim emitOp(OpNum); 435296417Sdim break; 436327952Sdim case dwarf::DW_OP_deref: 437353358Sdim assert(!isRegisterLocation()); 438353358Sdim if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor)) 439321369Sdim // Turning this into a memory location description makes the deref 440321369Sdim // implicit. 441321369Sdim LocationKind = Memory; 442321369Sdim else 443321369Sdim emitOp(dwarf::DW_OP_deref); 444277323Sdim break; 445314564Sdim case dwarf::DW_OP_constu: 446353358Sdim assert(!isRegisterLocation()); 447344779Sdim emitConstu(Op->getArg(0)); 448314564Sdim break; 449353358Sdim case dwarf::DW_OP_LLVM_convert: { 450353358Sdim unsigned BitSize = Op->getArg(0); 451353358Sdim dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1)); 452353358Sdim if (DwarfVersion >= 5) { 453353358Sdim emitOp(dwarf::DW_OP_convert); 454353358Sdim // Reuse the base_type if we already have one in this CU otherwise we 455353358Sdim // create a new one. 456353358Sdim unsigned I = 0, E = CU.ExprRefedBaseTypes.size(); 457353358Sdim for (; I != E; ++I) 458353358Sdim if (CU.ExprRefedBaseTypes[I].BitSize == BitSize && 459353358Sdim CU.ExprRefedBaseTypes[I].Encoding == Encoding) 460353358Sdim break; 461353358Sdim 462353358Sdim if (I == E) 463353358Sdim CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding); 464353358Sdim 465353358Sdim // If targeting a location-list; simply emit the index into the raw 466353358Sdim // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been 467353358Sdim // fitted with means to extract it later. 468353358Sdim // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef 469353358Sdim // (containing the index and a resolve mechanism during emit) into the 470353358Sdim // DIE value list. 471353358Sdim emitBaseTypeRef(I); 472353358Sdim } else { 473353358Sdim if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) { 474353358Sdim if (Encoding == dwarf::DW_ATE_signed) 475353358Sdim emitLegacySExt(PrevConvertOp->getArg(0)); 476353358Sdim else if (Encoding == dwarf::DW_ATE_unsigned) 477353358Sdim emitLegacyZExt(PrevConvertOp->getArg(0)); 478353358Sdim PrevConvertOp = None; 479353358Sdim } else { 480353358Sdim PrevConvertOp = Op; 481353358Sdim } 482353358Sdim } 483353358Sdim break; 484353358Sdim } 485314564Sdim case dwarf::DW_OP_stack_value: 486321369Sdim LocationKind = Implicit; 487314564Sdim break; 488321369Sdim case dwarf::DW_OP_swap: 489353358Sdim assert(!isRegisterLocation()); 490321369Sdim emitOp(dwarf::DW_OP_swap); 491321369Sdim break; 492321369Sdim case dwarf::DW_OP_xderef: 493353358Sdim assert(!isRegisterLocation()); 494321369Sdim emitOp(dwarf::DW_OP_xderef); 495321369Sdim break; 496353358Sdim case dwarf::DW_OP_deref_size: 497353358Sdim emitOp(dwarf::DW_OP_deref_size); 498353358Sdim emitData1(Op->getArg(0)); 499353358Sdim break; 500353358Sdim case dwarf::DW_OP_LLVM_tag_offset: 501353358Sdim TagOffset = Op->getArg(0); 502353358Sdim break; 503360784Sdim case dwarf::DW_OP_regx: 504360784Sdim emitOp(dwarf::DW_OP_regx); 505360784Sdim emitUnsigned(Op->getArg(0)); 506360784Sdim break; 507360784Sdim case dwarf::DW_OP_bregx: 508360784Sdim emitOp(dwarf::DW_OP_bregx); 509360784Sdim emitUnsigned(Op->getArg(0)); 510360784Sdim emitSigned(Op->getArg(1)); 511360784Sdim break; 512277323Sdim default: 513288943Sdim llvm_unreachable("unhandled opcode found in expression"); 514277323Sdim } 515277323Sdim } 516321369Sdim 517360784Sdim if (isImplicitLocation() && !isParameterValue()) 518321369Sdim // Turn this into an implicit location description. 519321369Sdim addStackValue(); 520277323Sdim} 521314564Sdim 522321369Sdim/// add masking operations to stencil out a subregister. 523321369Sdimvoid DwarfExpression::maskSubRegister() { 524321369Sdim assert(SubRegisterSizeInBits && "no subregister was registered"); 525321369Sdim if (SubRegisterOffsetInBits > 0) 526321369Sdim addShr(SubRegisterOffsetInBits); 527321369Sdim uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL; 528321369Sdim addAnd(Mask); 529321369Sdim} 530321369Sdim 531314564Sdimvoid DwarfExpression::finalize() { 532321369Sdim assert(DwarfRegs.size() == 0 && "dwarf registers not emitted"); 533321369Sdim // Emit any outstanding DW_OP_piece operations to mask out subregisters. 534321369Sdim if (SubRegisterSizeInBits == 0) 535321369Sdim return; 536321369Sdim // Don't emit a DW_OP_piece for a subregister at offset 0. 537321369Sdim if (SubRegisterOffsetInBits == 0) 538321369Sdim return; 539321369Sdim addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits); 540314564Sdim} 541314564Sdim 542314564Sdimvoid DwarfExpression::addFragmentOffset(const DIExpression *Expr) { 543314564Sdim if (!Expr || !Expr->isFragment()) 544314564Sdim return; 545314564Sdim 546314564Sdim uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits; 547314564Sdim assert(FragmentOffset >= OffsetInBits && 548314564Sdim "overlapping or duplicate fragments"); 549314564Sdim if (FragmentOffset > OffsetInBits) 550321369Sdim addOpPiece(FragmentOffset - OffsetInBits); 551314564Sdim OffsetInBits = FragmentOffset; 552314564Sdim} 553353358Sdim 554353358Sdimvoid DwarfExpression::emitLegacySExt(unsigned FromBits) { 555353358Sdim // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X 556353358Sdim emitOp(dwarf::DW_OP_dup); 557353358Sdim emitOp(dwarf::DW_OP_constu); 558353358Sdim emitUnsigned(FromBits - 1); 559353358Sdim emitOp(dwarf::DW_OP_shr); 560353358Sdim emitOp(dwarf::DW_OP_lit0); 561353358Sdim emitOp(dwarf::DW_OP_not); 562353358Sdim emitOp(dwarf::DW_OP_mul); 563353358Sdim emitOp(dwarf::DW_OP_constu); 564353358Sdim emitUnsigned(FromBits); 565353358Sdim emitOp(dwarf::DW_OP_shl); 566353358Sdim emitOp(dwarf::DW_OP_or); 567353358Sdim} 568353358Sdim 569353358Sdimvoid DwarfExpression::emitLegacyZExt(unsigned FromBits) { 570353358Sdim // (X & (1 << FromBits - 1)) 571353358Sdim emitOp(dwarf::DW_OP_constu); 572353358Sdim emitUnsigned((1ULL << FromBits) - 1); 573353358Sdim emitOp(dwarf::DW_OP_and); 574353358Sdim} 575360784Sdim 576360784Sdimvoid DwarfExpression::addWasmLocation(unsigned Index, int64_t Offset) { 577360784Sdim assert(LocationKind == Implicit || LocationKind == Unknown); 578360784Sdim LocationKind = Implicit; 579360784Sdim emitOp(dwarf::DW_OP_WASM_location); 580360784Sdim emitUnsigned(Index); 581360784Sdim emitSigned(Offset); 582360784Sdim} 583