| /freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 2074 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Target/R600/ |
| H A D | AMDILCFGStructurizer.cpp | 466 MachineInstr *MI = MBB->getParent() local
475 MachineInstr *MI = local
571 getTrueBranch(MachineInstr *MI) argument
575 setTrueBranch(MachineInstr *MI, MachineBasicBlock *MBB) argument
581 getFalseBranch(MachineBasicBlock *MBB, MachineInstr *MI) argument
591 isCondBranch(MachineInstr *MI) argument
602 isUncondBranch(MachineInstr *MI) argument
628 MachineInstr *MI = &*It; local
639 MachineInstr *MI = &*It; local
663 MachineInstr *MI = &(*It); local
671 MachineInstr *MI = getReturnInstr(MBB); local
695 MachineInstr *MI = Func->CloneMachineInstr(It); local
1604 MachineInstr *MI = getLoopendBlockBranchInstr(ContingMBB); local
1787 MachineInstr *MI = getReturnInstr(MBB); local
[all...] |
| H A D | R600ISelLowering.cpp | 127 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2528 bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, argument
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| H A D | X86InstrInfo.cpp | 1453 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument
1502 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, argument
1574 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
1582 isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
1595 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
1604 isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
1636 isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const argument
1808 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); local
1818 hasLiveCondCodeDef(MachineInstr *MI) argument
1831 getTruncatedShiftCount(MachineInstr *MI, unsigned ShiftAmtOperandIdx) argument
1850 classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned Opc, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const argument
1930 MachineInstr *MI = MBBI; local
2047 MachineInstr *MI = MBBI; local
2345 commuteInstruction(MachineInstr *MI, bool NewMI) const argument
3035 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
3215 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
3253 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
3286 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
3402 isDefConvertible(MachineInstr *MI) argument
3545 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); local
3744 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument
3871 FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, const SmallVectorImpl<MachineOperand> &MOs, MachineInstr *MI, const TargetInstrInfo &TII) argument
3899 FuseInst(MachineFunction &MF, unsigned Opcode, unsigned OpNo, const SmallVectorImpl<MachineOperand> &MOs, MachineInstr *MI, const TargetInstrInfo &TII) argument
3924 MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, const SmallVectorImpl<MachineOperand> &MOs, MachineInstr *MI) argument
3939 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned i, const SmallVectorImpl<MachineOperand> &MOs, unsigned Size, unsigned Align) const argument
4040 dbgs() << "We failed to fuse operand " << i << " in " << *MI; local
4089 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
4159 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const argument
4176 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
4201 foldPatchpoint(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex, const TargetInstrInfo &TII) argument
4262 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument
4312 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const argument
4456 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument
4511 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
5207 setExecutionDomain(MachineInstr *MI, unsigned Domain) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1323 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1444 MemIntrinsic *MI = cast<MemIntrinsic>(II); local
1481 Instruction *InstCombiner::visitAllocSite(Instruction &MI) { argument
|
| /freebsd-10.1-release/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | CodeGenPrepare.cpp | 899 AddressingModeMatcher(SmallVectorImpl<Instruction*> &AMI, const TargetLowering &T, Type *AT, Instruction *MI, ExtAddrMode &AM) argument
|
| H A D | ScalarReplAggregates.cpp | 2157 SROA::RewriteMemIntrinUserOfAlloca(MemIntrinsic *MI, Instruction *Inst, argument
[all...] |
| H A D | GVN.cpp | 532 static AvailableValueInBlock getMI(BasicBlock *BB, MemIntrinsic *MI, argument
1060 AnalyzeLoadFromClobberingMemInst(Type *LoadTy, Value *LoadPtr, MemIntrinsic *MI, const DataLayout &TD) argument
|
| /freebsd-10.1-release/contrib/llvm/tools/clang/lib/Lex/ |
| H A D | PPDirectives.cpp | 56 MacroInfo *MI = AllocateMacroInfo(); local
70 MacroInfo *MI = &MIChain->MI; local
78 AllocateDefMacroDirective(MacroInfo *MI, SourceLocation Loc, bool isImported) argument
102 ReleaseMacroInfo(MacroInfo *MI) argument
1783 ReadMacroDefinitionArgList(MacroInfo *MI, Token &Tok) argument
1894 MacroInfo *MI = AllocateMacroInfo(MacroNameTok.getLocation()); local
2146 const MacroInfo *MI = MD ? MD->getMacroInfo() : 0; local
2198 MacroInfo *MI = MD ? MD->getMacroInfo() : 0; local
[all...] |
| /freebsd-10.1-release/contrib/llvm/utils/TableGen/ |
| H A D | AsmMatcherEmitter.cpp | 588 MatchableInfo* MI; member in struct:__anon3826::OperandMatchEntry
|
| /freebsd-10.1-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfDebug.cpp | 1335 static bool isDbgValueInDefinedReg(const MachineInstr *MI) { argument
1344 getDebugLocEntry(AsmPrinter *Asm, const MCSymbol *FLabel, const MCSymbol *SLabel, const MachineInstr *MI) argument
1477 getLabelBeforeInsn(const MachineInstr *MI) argument
1484 getLabelAfterInsn(const MachineInstr *MI) argument
1489 beginInstruction(const MachineInstr *MI) argument
1531 endInstruction(const MachineInstr *MI) argument
1657 const MachineInstr *MI = II; local
1785 const MachineInstr *MI = History[i]; local
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 240 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { argument
254 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { argument
276 MachineInstr *MI = &*MIB; local
2979 tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, const LoadInst *LI) argument
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 454 PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const argument
502 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument
920 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
968 isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
1111 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const argument
1159 isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const argument
1285 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); local
1306 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF); local
1524 isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const argument
1619 getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) argument
1644 commuteInstruction(MachineInstr *MI, bool NewMI) const argument
1704 analyzeSelect(const MachineInstr *MI, SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const argument
1725 optimizeSelect(MachineInstr *MI, bool PreferFalse) const argument
1969 rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) argument
2114 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
2148 isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, int CmpMask, bool CommonUse) argument
2232 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); local
2578 getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, const MachineInstr *MI) argument
3233 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument
3257 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
3794 getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost) const argument
3899 verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const argument
4005 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument
4034 setExecutionDomain(MachineInstr *MI, unsigned Domain) const argument
4240 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
4302 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 415 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, argument
536 tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const void *Decoder) argument
564 AddThumb1SBit(MCInst &MI, bool InITBlock) argument
683 getInstruction(MCInst &MI, uint64_t &Size, const MemoryObject &Region, uint64_t Address, raw_ostream &os, raw_ostream &cs) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2845 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument
2908 expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const argument
2968 expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode, unsigned CondCode) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2245 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI, argument
2256 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI, argument
2265 static unsigned forceReg(MachineInstr *MI, MachineOperan argument
2282 emitSelect(MachineInstr *MI, MachineBasicBlock *MBB) const argument
2328 emitCondStore(MachineInstr *MI, MachineBasicBlock *MBB, unsigned StoreOpcode, unsigned STOCOpcode, bool Invert) const argument
2394 emitAtomicLoadBinary(MachineInstr *MI, MachineBasicBlock *MBB, unsigned BinOpcode, unsigned BitSize, bool Invert) const argument
2517 emitAtomicLoadMinMax(MachineInstr *MI, MachineBasicBlock *MBB, unsigned CompareOpcode, unsigned KeepOldMask, unsigned BitSize) const argument
2631 emitAtomicCmpSwapW(MachineInstr *MI, MachineBasicBlock *MBB) const argument
2746 emitExt128(MachineInstr *MI, MachineBasicBlock *MBB, bool ClearEven, unsigned SubReg) const argument
2777 emitMemMemWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const argument
2946 emitStringWrapper(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode) const argument
3005 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Transforms/Instrumentation/ |
| H A D | AddressSanitizer.cpp | 622 bool AddressSanitizer::instrumentMemIntrinsic(MemIntrinsic *MI) { argument
|
| /freebsd-10.1-release/contrib/llvm/tools/clang/include/clang/Lex/ |
| H A D | Preprocessor.h | 391 MacroInfo MI; member in struct:clang::Preprocessor::MacroInfoChain
405 MacroInfo MI; member in struct:clang::Preprocessor::DeserializedMacroInfoChain
561 DefMacroDirective *appendDefMacroDirective(IdentifierInfo *II, MacroInfo *MI, argument
568 DefMacroDirective *appendDefMacroDirective(IdentifierInfo *II, MacroInfo *MI){ argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/tools/clang/lib/AST/ |
| H A D | VTableBuilder.cpp | 1702 const MethodInfo &MI = I->second; local
2565 const MethodInfo &MI = I->second; local
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
| H A D | MachineScheduler.cpp | 458 void ScheduleDAGMI::moveInstruction(MachineInstr *MI, argument
877 MachineInstr *MI = SU->getInstr(); local
2390 const MachineInstr *MI = SU->getInstr(); local
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 432 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, argument
516 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI, argument
608 emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const argument
688 EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const argument
786 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 762 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, argument
787 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, argument
875 emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, bool Nand) const argument
960 emitAtomicBinaryPartword(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, bool Nand) const argument
1118 emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const argument
1199 emitAtomicCmpSwapPartword(MachineInstr *MI, MachineBasicBlock *BB, unsigned Size) const argument
[all...] |
| /freebsd-10.1-release/contrib/llvm/tools/clang/lib/CodeGen/ |
| H A D | CGDebugInfo.cpp | 935 llvm::DenseMap<const Decl *, llvm::WeakVH>::iterator MI = local
1125 llvm::DenseMap<const FunctionDecl *, llvm::WeakVH>::iterator MI = local
1143 llvm::DenseMap<const FunctionDecl *, llvm::WeakVH>::iterator MI = local
2351 MI = SPCache.find(FD->getCanonicalDecl()); local
2373 MI = SPCache.find(NextFD->getCanonicalDecl()); local
[all...] |