Lines Matching defs:MI
1453 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1456 switch (MI.getOpcode()) {
1471 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1474 SrcReg = MI.getOperand(1).getReg();
1475 DstReg = MI.getOperand(0).getReg();
1476 switch (MI.getOpcode()) {
1502 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1504 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1505 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1506 MI->getOperand(Op+1).getImm() == 1 &&
1507 MI->getOperand(Op+2).getReg() == 0 &&
1508 MI->getOperand(Op+3).getImm() == 0) {
1509 FrameIndex = MI->getOperand(Op).getIndex();
1574 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1576 if (isFrameLoadOpcode(MI->getOpcode()))
1577 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1578 return MI->getOperand(0).getReg();
1582 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1584 if (isFrameLoadOpcode(MI->getOpcode())) {
1586 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1590 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1595 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1597 if (isFrameStoreOpcode(MI->getOpcode()))
1598 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1599 isFrameOperand(MI, 0, FrameIndex))
1600 return MI->getOperand(X86::AddrNumOperands).getReg();
1604 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1606 if (isFrameStoreOpcode(MI->getOpcode())) {
1608 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1612 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1636 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1638 switch (MI->getOpcode()) {
1671 if (MI->getOperand(1).isReg() &&
1672 MI->getOperand(2).isImm() &&
1673 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1674 MI->isInvariantLoad(AA)) {
1675 unsigned BaseReg = MI->getOperand(1).getReg();
1679 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1681 const MachineFunction &MF = *MI->getParent()->getParent();
1690 if (MI->getOperand(2).isImm() &&
1691 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1692 !MI->getOperand(4).isReg()) {
1694 if (!MI->getOperand(1).isReg())
1696 unsigned BaseReg = MI->getOperand(1).getReg();
1700 const MachineFunction &MF = *MI->getParent()->getParent();
1808 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1809 MBB.insert(I, MI);
1816 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1818 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1819 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1820 MachineOperand &MO = MI->getOperand(i);
1831 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1834 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1835 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1850 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1854 MachineFunction &MF = *MI->getParent()->getParent();
1879 // another we need to add 64-bit registers to the final MI.
1886 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1894 isKill = MI->killsRegister(SrcReg);
1907 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1930 MachineInstr *MI = MBBI;
1931 unsigned Dest = MI->getOperand(0).getReg();
1932 unsigned Src = MI->getOperand(1).getReg();
1933 bool isDead = MI->getOperand(0).isDead();
1934 bool isKill = MI->getOperand(1).isKill();
1954 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1956 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1960 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1965 unsigned ShAmt = MI->getOperand(2).getImm();
1982 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1986 unsigned Src2 = MI->getOperand(2).getReg();
1987 bool isKill2 = MI->getOperand(2).isKill();
2001 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2003 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2009 LV->replaceKillInstruction(Src2, MI, InsMI2);
2016 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2025 LV->replaceKillInstruction(Src, MI, InsMI);
2027 LV->replaceKillInstruction(Dest, MI, ExtMI);
2047 MachineInstr *MI = MBBI;
2052 if (hasLiveCondCodeDef(MI))
2055 MachineFunction &MF = *MI->getParent()->getParent();
2057 const MachineOperand &Dest = MI->getOperand(0);
2058 const MachineOperand &Src = MI->getOperand(1);
2067 unsigned MIOpc = MI->getOpcode();
2070 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2073 unsigned B = MI->getOperand(1).getReg();
2074 unsigned C = MI->getOperand(2).getReg();
2076 unsigned M = MI->getOperand(3).getImm();
2077 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2082 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2085 unsigned B = MI->getOperand(1).getReg();
2086 unsigned C = MI->getOperand(2).getReg();
2088 unsigned M = MI->getOperand(3).getImm();
2093 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2098 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2099 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2108 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2114 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2115 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2124 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2128 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2140 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2141 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2146 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2158 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2164 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2168 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2181 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2182 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2188 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2195 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2199 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2213 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2214 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2221 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2231 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2235 const MachineOperand &Src2 = MI->getOperand(2);
2239 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2243 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2257 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2264 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2265 unsigned Src2 = MI->getOperand(2).getReg();
2266 bool isKill2 = MI->getOperand(2).isKill();
2267 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2272 bool isUndef = MI->getOperand(1).isUndef();
2273 bool isUndef2 = MI->getOperand(2).isUndef();
2278 LV->replaceKillInstruction(Src2, MI, NewMI);
2285 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2286 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2288 MI->getOperand(2).getImm());
2294 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2300 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2304 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2310 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2319 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2320 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2322 MI->getOperand(2).getImm());
2332 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2334 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2345 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2346 switch (MI->getOpcode()) {
2355 switch (MI->getOpcode()) {
2364 unsigned Amt = MI->getOperand(3).getImm();
2366 MachineFunction &MF = *MI->getParent()->getParent();
2367 MI = MF.CloneMachineInstr(MI);
2370 MI->setDesc(get(Opc));
2371 MI->getOperand(3).setImm(Size-Amt);
2372 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2391 switch (MI->getOpcode()) {
2443 MachineFunction &MF = *MI->getParent()->getParent();
2444 MI = MF.CloneMachineInstr(MI);
2447 MI->setDesc(get(Opc));
2451 return TargetInstrInfo::commuteInstruction(MI, NewMI);
2601 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2603 /// set by MI(b,a).
2696 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2697 if (!MI->isTerminator()) return false;
2700 if (MI->isBranch() && !MI->isBarrier())
2702 if (!MI->isPredicable())
2704 return !isPredicated(MI);
3036 MachineBasicBlock::iterator MI, DebugLoc DL,
3073 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3083 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3084 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3088 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3089 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3095 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3097 BuildMI(MBB, MI, DL, get(X86::POPF64));
3101 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3103 BuildMI(MBB, MI, DL, get(X86::POPF32));
3216 MachineBasicBlock::iterator MI,
3227 DebugLoc DL = MBB.findDebugLoc(MI);
3228 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3254 MachineBasicBlock::iterator MI,
3263 DebugLoc DL = MBB.findDebugLoc(MI);
3264 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3286 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3288 switch (MI->getOpcode()) {
3297 SrcReg = MI->getOperand(0).getReg();
3300 CmpValue = MI->getOperand(1).getImm();
3307 SrcReg = MI->getOperand(1).getReg();
3316 SrcReg = MI->getOperand(1).getReg();
3317 SrcReg2 = MI->getOperand(2).getReg();
3328 SrcReg = MI->getOperand(1).getReg();
3331 CmpValue = MI->getOperand(2).getImm();
3337 SrcReg = MI->getOperand(0).getReg();
3338 SrcReg2 = MI->getOperand(1).getReg();
3346 SrcReg = MI->getOperand(0).getReg();
3347 if (MI->getOperand(1).getReg() != SrcReg) return false;
3402 inline static bool isDefConvertible(MachineInstr *MI) {
3403 switch (MI->getOpcode()) {
3410 return getTruncatedShiftCount(MI, 2) != 0;
3415 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3422 return getTruncatedShiftCount(MI, 3) != 0;
3545 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3546 if (!MI) return false;
3549 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3551 // If we are comparing against zero, check whether we can use MI to update
3552 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3554 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3555 !isDefConvertible(MI)))
3570 RE = CmpInstr->getParent() == MI->getParent() ?
3571 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3697 // The instruction to be updated is either Sub or MI.
3698 Sub = IsCmpZero ? MI : Sub;
3744 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3750 if (MI->mayLoad()) {
3762 // We try to commute MI if possible.
3763 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3765 // Collect information about virtual register operands of MI.
3768 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3769 MachineOperand &MO = MI->getOperand(i);
3787 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3794 // MI was changed but it didn't help, commute it back!
3795 commuteInstruction(MI, false);
3799 // Check whether we can commute MI and enable folding.
3800 if (MI->isCommutable()) {
3801 MachineInstr *NewMI = commuteInstruction(MI, false);
3804 if (NewMI != MI) {
3836 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3838 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3839 switch (MI->getOpcode()) {
3862 MI->setDesc(get(X86::TEST8ri));
3873 MachineInstr *MI,
3878 MI->getDebugLoc(), true);
3887 unsigned NumOps = MI->getDesc().getNumOperands()-2;
3889 MachineOperand &MO = MI->getOperand(i+2);
3892 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3893 MachineOperand &MO = MI->getOperand(i);
3902 MachineInstr *MI, const TargetInstrInfo &TII) {
3905 MI->getDebugLoc(), true);
3908 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3909 MachineOperand &MO = MI->getOperand(i);
3926 MachineInstr *MI) {
3927 MachineFunction &MF = *MI->getParent()->getParent();
3928 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3940 MachineInstr *MI, unsigned i,
3950 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
3954 unsigned NumOps = MI->getDesc().getNumOperands();
3956 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3960 if (MI->getOpcode() == X86::ADD32ri &&
3961 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3969 MI->getOperand(0).isReg() &&
3970 MI->getOperand(1).isReg() &&
3971 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
3975 if (MI->getOpcode() == X86::MOV32r0) {
3976 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
3994 OpcodeTablePtr->find(MI->getOpcode());
4002 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4011 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4019 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4021 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4039 if (PrintFailedFusing && !MI->isCopy())
4040 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4089 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4091 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4094 // If MI is marked as reading Reg, the partial register update is wanted.
4095 const MachineOperand &MO = MI->getOperand(0);
4098 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4101 if (MI->readsRegister(Reg, TRI))
4159 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4161 if (!hasUndefRegUpdate(MI->getOpcode()))
4167 const MachineOperand &MO = MI->getOperand(OpNum);
4176 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4178 unsigned Reg = MI->getOperand(OpNum).getReg();
4179 // If MI kills this register, the false dependence is already broken.
4180 if (MI->killsRegister(Reg, TRI))
4187 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4193 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4198 MI->addRegisterKilled(Reg, TRI, true);
4202 MachineInstr *MI,
4207 switch (MI->getOpcode()) {
4213 PatchPointOpers opers(MI);
4230 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true);
4235 MIB.addOperand(MI->getOperand(i));
4237 for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) {
4238 MachineOperand &MO = MI->getOperand(i);
4262 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4266 if (MI->getOpcode() == TargetOpcode::STACKMAP
4267 || MI->getOpcode() == TargetOpcode::PATCHPOINT) {
4268 return foldPatchpoint(MF, MI, Ops, FrameIndex, *this);
4277 hasPartialRegUpdate(MI->getOpcode()))
4290 switch (MI->getOpcode()) {
4302 MI->setDesc(get(NewOpc));
4303 MI->getOperand(1).ChangeToImmediate(0);
4309 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
4313 MachineInstr *MI,
4320 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4329 hasPartialRegUpdate(MI->getOpcode()))
4357 switch (MI->getOpcode()) {
4365 MI->setDesc(get(NewOpc));
4366 MI->getOperand(1).ChangeToImmediate(0);
4372 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4400 // 2. It may not be live at MI.
4452 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4456 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4462 switch (MI->getOpcode()) {
4472 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4482 unsigned Opc = MI->getOpcode();
4483 unsigned NumOps = MI->getDesc().getNumOperands();
4485 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4508 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4511 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4515 MemOp2RegOpTable.find(MI->getOpcode());
4531 if (!MI->hasOneMemOperand() &&
4542 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4543 MachineOperand &Op = MI->getOperand(i);
4558 MF.extractLoadMemRefs(MI->memoperands_begin(),
4559 MI->memoperands_end());
4572 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4628 MF.extractStoreMemRefs(MI->memoperands_begin(),
4629 MI->memoperands_end());
5196 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5197 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5200 if (domain && lookup(MI->getOpcode(), domain))
5202 else if (domain && lookupAVX2(MI->getOpcode(), domain))
5207 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5209 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5211 const uint16_t *table = lookup(MI->getOpcode(), dom);
5215 table = lookupAVX2(MI->getOpcode(), dom);
5218 MI->setDesc(get(table[Domain-1]));