Lines Matching defs:MI
130 MachineInstr *MI = MBBI;
131 MachineFunction &MF = *MI->getParent()->getParent();
132 uint64_t TSFlags = MI->getDesc().TSFlags;
145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
152 const MCInstrDesc &MCID = MI->getDesc();
154 bool isLoad = !MI->mayStore();
155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156 const MachineOperand &Base = MI->getOperand(2);
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
173 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
223 MemMI = BuildMI(MF, MI->getDebugLoc(),
224 get(MemOpc), MI->getOperand(0).getReg())
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc)).addReg(MI->getOperand(1).getReg())
238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = MI->getOperand(i);
251 // Look at the two new MI's in reverse order.
256 if (VI.removeKill(MI))
437 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
438 if (MI->isBundle()) {
439 MachineBasicBlock::const_instr_iterator I = MI;
440 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
449 int PIdx = MI->findFirstPredOperandIdx();
450 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
454 PredicateInstruction(MachineInstr *MI,
456 unsigned Opc = MI->getOpcode();
458 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
459 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
465 int PIdx = MI->findFirstPredOperandIdx();
467 MachineOperand &PMO = MI->getOperand(PIdx);
469 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
502 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
506 const MachineOperand &MO = MI->getOperand(i);
520 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
521 if (!MI->isPredicable())
525 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
529 return isV8EligibleForIT(MI);
531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
550 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
551 const MachineBasicBlock &MBB = *MI->getParent();
555 const MCInstrDesc &MCID = MI->getDesc();
560 if (MI->getOpcode() == ARM::INLINEASM)
561 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
562 if (MI->isLabel())
564 unsigned Opc = MI->getOpcode();
573 return getInstBundleLength(MI);
585 return MI->getOperand(2).getImm();
611 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
639 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
641 MachineBasicBlock::const_instr_iterator I = MI;
642 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
920 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
922 switch (MI->getOpcode()) {
926 if (MI->getOperand(1).isFI() &&
927 MI->getOperand(2).isReg() &&
928 MI->getOperand(3).isImm() &&
929 MI->getOperand(2).getReg() == 0 &&
930 MI->getOperand(3).getImm() == 0) {
931 FrameIndex = MI->getOperand(1).getIndex();
932 return MI->getOperand(0).getReg();
940 if (MI->getOperand(1).isFI() &&
941 MI->getOperand(2).isImm() &&
942 MI->getOperand(2).getImm() == 0) {
943 FrameIndex = MI->getOperand(1).getIndex();
944 return MI->getOperand(0).getReg();
950 if (MI->getOperand(0).isFI() &&
951 MI->getOperand(2).getSubReg() == 0) {
952 FrameIndex = MI->getOperand(0).getIndex();
953 return MI->getOperand(2).getReg();
957 if (MI->getOperand(1).isFI() &&
958 MI->getOperand(0).getSubReg() == 0) {
959 FrameIndex = MI->getOperand(1).getIndex();
960 return MI->getOperand(0).getReg();
968 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
971 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1111 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1113 switch (MI->getOpcode()) {
1117 if (MI->getOperand(1).isFI() &&
1118 MI->getOperand(2).isReg() &&
1119 MI->getOperand(3).isImm() &&
1120 MI->getOperand(2).getReg() == 0 &&
1121 MI->getOperand(3).getImm() == 0) {
1122 FrameIndex = MI->getOperand(1).getIndex();
1123 return MI->getOperand(0).getReg();
1131 if (MI->getOperand(1).isFI() &&
1132 MI->getOperand(2).isImm() &&
1133 MI->getOperand(2).getImm() == 0) {
1134 FrameIndex = MI->getOperand(1).getIndex();
1135 return MI->getOperand(0).getReg();
1141 if (MI->getOperand(1).isFI() &&
1142 MI->getOperand(0).getSubReg() == 0) {
1143 FrameIndex = MI->getOperand(1).getIndex();
1144 return MI->getOperand(0).getReg();
1148 if (MI->getOperand(1).isFI() &&
1149 MI->getOperand(0).getSubReg() == 0) {
1150 FrameIndex = MI->getOperand(1).getIndex();
1151 return MI->getOperand(0).getReg();
1159 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1162 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1165 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1170 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1175 unsigned DstRegS = MI->getOperand(0).getReg();
1176 unsigned SrcRegS = MI->getOperand(1).getReg();
1191 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1195 if (MI->getOperand(0).isDead())
1199 DEBUG(dbgs() << "widening: " << *MI);
1200 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1204 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1206 MI->RemoveOperand(ImpDefIdx);
1209 MI->setDesc(get(ARM::VMOVD));
1210 MI->getOperand(0).setReg(DstRegD);
1211 MI->getOperand(1).setReg(SrcRegD);
1218 MI->getOperand(1).setIsUndef();
1223 if (MI->getOperand(1).isKill()) {
1224 MI->getOperand(1).setIsKill(false);
1225 MI->addRegisterKilled(SrcRegS, TRI, true);
1228 DEBUG(dbgs() << "replaced by: " << *MI);
1285 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1286 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1287 MBB.insert(I, MI);
1306 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1317 return MI;
1524 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1533 if (MI->isDebugValue())
1537 if (MI->isTerminator() || MI->isLabel())
1546 MachineBasicBlock::const_iterator I = MI;
1561 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1619 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1620 int PIdx = MI->findFirstPredOperandIdx();
1626 PredReg = MI->getOperand(PIdx+1).getReg();
1627 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1644 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1645 switch (MI->getOpcode()) {
1650 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1654 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1655 if (!MI)
1658 MI->getOperand(MI->findFirstPredOperandIdx())
1660 return MI;
1663 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1675 MachineInstr *MI = MRI.getVRegDef(Reg);
1676 if (!MI)
1678 // MI is folded into the MOVCC by predicating it.
1679 if (!MI->isPredicable())
1681 // Check if MI has any non-dead defs or physreg uses. This also detects
1683 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1684 const MachineOperand &MO = MI->getOperand(i);
1690 // MI can't have any tied operands, that would conflict with predication.
1699 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1701 return MI;
1704 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1708 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1718 Cond.push_back(MI->getOperand(3));
1719 Cond.push_back(MI->getOperand(4));
1725 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1727 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1729 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1730 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1733 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1738 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1739 unsigned DestReg = MI->getOperand(0).getReg();
1746 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1755 unsigned CondCode = MI->getOperand(3).getImm();
1760 NewMI.addOperand(MI->getOperand(4));
1774 // The caller will erase MI, but not DefMI.
1861 MachineInstr *MI,
1871 bool IsPop = isPopOpcode(MI->getOpcode());
1872 bool IsPush = isPushOpcode(MI->getOpcode());
1876 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1877 MI->getOpcode() == ARM::VLDMDIA_UPD;
1878 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
1879 MI->getOpcode() == ARM::tPOP ||
1880 MI->getOpcode() == ARM::tPOP_RET;
1882 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
1883 MI->getOperand(1).getReg() == ARM::SP)) &&
1897 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
1911 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1912 RegList.push_back(MI->getOperand(i));
1914 MachineBasicBlock *MBB = MI->getParent();
1936 MBB->computeRegisterLiveness(TRI, CurReg, MI) !=
1958 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1959 MI->RemoveOperand(i);
1962 MachineInstrBuilder MIB(MF, &*MI);
1969 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1972 unsigned Opcode = MI.getOpcode();
1973 const MCInstrDesc &Desc = MI.getDesc();
1982 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1985 MI.setDesc(TII.get(ARM::MOVr));
1986 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1987 MI.RemoveOperand(FrameRegIdx+1);
1993 MI.setDesc(TII.get(ARM::SUBri));
1999 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2000 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2016 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2025 InstrOffs = MI.getOperand(ImmIdx).getImm();
2031 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2032 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2039 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2040 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2051 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2052 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2072 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2077 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2114 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2116 switch (MI->getOpcode()) {
2120 SrcReg = MI->getOperand(0).getReg();
2123 CmpValue = MI->getOperand(1).getImm();
2127 SrcReg = MI->getOperand(0).getReg();
2128 SrcReg2 = MI->getOperand(1).getReg();
2134 SrcReg = MI->getOperand(0).getReg();
2136 CmpMask = MI->getOperand(1).getImm();
2147 /// When successful, MI will hold the found instruction.
2148 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2150 switch (MI->getOpcode()) {
2153 if (CmpMask != MI->getOperand(2).getImm())
2155 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2160 const MachineInstr &Copy = *MI;
2162 llvm::next(MachineBasicBlock::iterator(MI)));
2163 if (AND == MI->getParent()->end()) return false;
2164 MI = AND;
2165 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2173 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2175 /// set by MI(b,a).
2232 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2233 if (!MI) return false;
2237 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2238 MI = 0;
2246 MI = PotentialAND;
2249 if (!MI) return false;
2254 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2261 // One is MI, the other is a SUB instruction.
2266 // MI is not a candidate for CMPrr.
2267 MI = NULL;
2268 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2274 MI = NULL;
2304 if (!MI && !Sub)
2307 // The single candidate is called MI.
2308 if (!MI) MI = Sub;
2311 if (isPredicated(MI))
2314 switch (MI->getOpcode()) {
2350 // When checking against MI: if it's a conditional code requires
2445 MI->getOperand(5).setReg(ARM::CPSR);
2446 MI->getOperand(5).setIsDef(true);
2447 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2579 const MachineInstr *MI) {
2580 switch (MI->getOpcode()) {
2582 const MCInstrDesc &Desc = MI->getDesc();
2592 unsigned ShOpVal = MI->getOperand(3).getImm();
2605 if (!MI->getOperand(2).getReg())
2608 unsigned ShOpVal = MI->getOperand(3).getImm();
2621 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2625 unsigned Rt = MI->getOperand(0).getReg();
2626 unsigned Rm = MI->getOperand(3).getReg();
2632 unsigned Rt = MI->getOperand(0).getReg();
2633 unsigned Rm = MI->getOperand(3).getReg();
2636 unsigned ShOpVal = MI->getOperand(4).getImm();
2649 unsigned ShOpVal = MI->getOperand(4).getImm();
2662 unsigned Rt = MI->getOperand(0).getReg();
2663 unsigned Rm = MI->getOperand(3).getReg();
2668 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2675 unsigned Rt = MI->getOperand(0).getReg();
2676 unsigned Rm = MI->getOperand(3).getReg();
2695 unsigned Rm = MI->getOperand(3).getReg();
2698 unsigned Rt = MI->getOperand(0).getReg();
2701 unsigned ShOpVal = MI->getOperand(4).getImm();
2713 unsigned Rt = MI->getOperand(0).getReg();
2714 unsigned Rn = MI->getOperand(2).getReg();
2715 unsigned Rm = MI->getOperand(3).getReg();
2717 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2722 unsigned Rm = MI->getOperand(3).getReg();
2724 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2737 unsigned Rt = MI->getOperand(0).getReg();
2738 unsigned Rn = MI->getOperand(3).getReg();
2739 unsigned Rm = MI->getOperand(4).getReg();
2741 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2746 unsigned Rt = MI->getOperand(0).getReg();
2747 unsigned Rn = MI->getOperand(3).getReg();
2752 unsigned Rm = MI->getOperand(4).getReg();
2754 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2782 unsigned Rt = MI->getOperand(0).getReg();
2783 unsigned Rn = MI->getOperand(2).getReg();
2810 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2821 // because we can't ensure that it is aware of other MI forms. Doing this will
2823 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2825 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2826 E = MI->memoperands_end(); I != E; ++I) {
2834 const MachineInstr *MI) const {
2838 const MCInstrDesc &Desc = MI->getDesc();
2843 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2848 unsigned Opc = MI->getOpcode();
2878 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2914 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2964 !MI->hasOneMemOperand() ||
2965 (*MI->memoperands_begin())->getAlignment() < 8)
3234 const MachineInstr *MI, unsigned Reg,
3238 MachineBasicBlock::const_iterator I = MI; ++I;
3258 const MachineInstr *MI, unsigned Reg,
3262 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3264 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3776 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3777 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3778 MI->isRegSequence() || MI->isImplicitDef())
3781 if (MI->isBundle())
3784 const MCInstrDesc &MCID = MI->getDesc();
3795 const MachineInstr *MI,
3797 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3798 MI->isRegSequence() || MI->isImplicitDef())
3803 if (MI->isBundle()) {
3805 MachineBasicBlock::const_instr_iterator I = MI;
3806 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3814 const MCInstrDesc &MCID = MI->getDesc();
3823 return MI->mayLoad() ? 3 : 1;
3829 return getNumMicroOps(ItinData, MI);
3835 unsigned DefAlign = MI->hasOneMemOperand()
3836 ? (*MI->memoperands_begin())->getAlignment() : 0;
3837 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3899 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3901 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3944 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3947 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3952 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3953 (MI->getOpcode() == ARM::VMOVRS ||
3954 MI->getOpcode() == ARM::VMOVSR ||
3955 MI->getOpcode() == ARM::VMOVS))
3959 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4006 MachineInstr *MI,
4011 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4020 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4034 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4037 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4039 switch (MI->getOpcode()) {
4048 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4051 DstReg = MI->getOperand(0).getReg();
4052 SrcReg = MI->getOperand(1).getReg();
4054 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4055 MI->RemoveOperand(i-1);
4058 MI->setDesc(get(ARM::VORRd));
4066 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4069 DstReg = MI->getOperand(0).getReg();
4070 SrcReg = MI->getOperand(1).getReg();
4072 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4073 MI->RemoveOperand(i-1);
4080 MI->setDesc(get(ARM::VGETLNi32));
4092 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4095 DstReg = MI->getOperand(0).getReg();
4096 SrcReg = MI->getOperand(1).getReg();
4101 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4104 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4105 MI->RemoveOperand(i-1);
4109 MI->setDesc(get(ARM::VSETLNi32));
4111 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4128 DstReg = MI->getOperand(0).getReg();
4129 SrcReg = MI->getOperand(1).getReg();
4136 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4139 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4140 MI->RemoveOperand(i-1);
4145 MI->setDesc(get(ARM::VDUPLN32d));
4147 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4173 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4180 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4184 CurUndef = !MI->readsRegister(CurReg, TRI);
4193 MI->setDesc(get(ARM::VEXTd32));
4199 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4203 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4240 getPartialRegUpdateClearance(const MachineInstr *MI,
4249 const MachineOperand &MO = MI->getOperand(OpNum);
4255 switch(MI->getOpcode()) {
4265 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4278 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4284 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4287 // Physical register: MI must define the full D-reg.
4290 if (!DReg || !MI->definesRegister(DReg, TRI))
4294 // MI has an unwanted D-register dependency.
4302 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4305 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4308 const MachineOperand &MO = MI->getOperand(OpNum);
4314 // If MI defines an S-reg, find the corresponding D super-register.
4321 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4329 // Insert the dependency-breaking FCONSTD before MI.
4331 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4333 MI->addRegisterKilled(DReg, TRI, true);
4340 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4341 if (MI->getNumOperands() < 4)
4343 unsigned ShOpVal = MI->getOperand(3).getImm();