Target/Sparc/SparcISelLowering.cpp

2845 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2847   switch (MI->getOpcode()) {
2853     return expandSelectCC(MI, BB, SP::BCOND);
2858     return expandSelectCC(MI, BB, SP::FBCOND);
2861     return expandAtomicRMW(MI, BB, SP::ADDrr);
2863     return expandAtomicRMW(MI, BB, SP::ADDXrr);
2865     return expandAtomicRMW(MI, BB, SP::SUBrr);
2867     return expandAtomicRMW(MI, BB, SP::SUBXrr);
2869     return expandAtomicRMW(MI, BB, SP::ANDrr);
2871     return expandAtomicRMW(MI, BB, SP::ANDXrr);
2873     return expandAtomicRMW(MI, BB, SP::ORrr);
2875     return expandAtomicRMW(MI, BB, SP::ORXrr);
2877     return expandAtomicRMW(MI, BB, SP::XORrr);
2879     return expandAtomicRMW(MI, BB, SP::XORXrr);
2881     return expandAtomicRMW(MI, BB, SP::ANDrr);
2883     return expandAtomicRMW(MI, BB, SP::ANDXrr);
2886     return expandAtomicRMW(MI, BB, 0);
2889     return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2891     return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2893     return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2895     return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2897     return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2899     return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2901     return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2903     return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2908 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
2912   DebugLoc dl = MI->getDebugLoc();
2913   unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2937                   llvm::next(MachineBasicBlock::iterator(MI)),
2959   BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2960     .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2961     .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2963   MI->eraseFromParent();   // The pseudo instruction is gone now.
2968 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
2974   DebugLoc DL = MI->getDebugLoc();
2976   // MI is an atomic read-modify-write instruction of the form:
2981   unsigned DestReg = MI->getOperand(0).getReg();
2982   unsigned AddrReg = MI->getOperand(1).getReg();
2983   unsigned Rs2Reg  = MI->getOperand(2).getReg();
2985   // SelectionDAG has already inserted memory barriers before and after MI, so
3002   BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
3005   // Split the basic block MBB before MI and insert the loop block in the hole.
3015   // Move MI and following instructions to DoneMBB.
3016   DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3044   if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3045       MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3053     .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3058   MI->eraseFromParent();