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296373 |
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04-Mar-2016 |
marius |
- Copy stable/10@296371 to releng/10.3 in preparation for 10.3-RC1 builds. - Update newvers.sh to reflect RC1. - Update __FreeBSD_version to reflect 10.3. - Update default pkg(8) configuration to use the quarterly branch.
Approved by: re (implicit) |
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283884 |
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01-Jun-2015 |
jhb |
MFC 282641,282658: - Move hwpmc(4) debugging code under a new HWPMC_DEBUG option instead of the broader DEBUG option. - Convert hwpmc(4) debug printfs over to KTR.
Sponsored by: Norse Corp, Inc.
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280455 |
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24-Mar-2015 |
rrs |
MFC of r277177 and r279894 with the fixes for the PMC for Haswell.
Sponsored by: Netflix Inc.
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267602 |
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18-Jun-2014 |
kib |
MFC r267062: Disable existing uncore hwpmc code for Nehalem and Westmere EX.
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266911 |
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31-May-2014 |
hiren |
MFC r263446
Update hwpmc to support core events for Atom Silvermont microarchitecture. (Model 0x4D as per Intel document 330061-001 01/2014)
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256281 |
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10-Oct-2013 |
gjb |
Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.
Approved by: re (implicit) Sponsored by: The FreeBSD Foundation
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250101 |
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30-Apr-2013 |
davide |
Complete r250097: Do not change the initialization order in pmc_intel_initialize().
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250097 |
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30-Apr-2013 |
davide |
When hwpmc(4) module is unloaded it reports a double leakage. This happens at least if FreeBSD is ran under VirtualBox. In order to avoid the leakage, properly deallocate structures in case CPU claims that hw performance monitoring counters are not supported.
Reported by: hiren
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249069 |
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03-Apr-2013 |
sbruno |
Trailing whitespace cleanup along with 80 column enforcemnt.
Submitted by: hiren.panchasara@gmail.com Reviewed by: sbruno@freebsd.org Obtained from: Yahoo! Inc. MFC after: 2 weeks
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248842 |
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28-Mar-2013 |
sbruno |
Update hwpmc to support Haswell class processors. 0x3C: /* Per Intel document 325462-045US 01/2013. */
Add manpage to document all the goodness that is available in this processor model.
Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
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246166 |
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31-Jan-2013 |
sbruno |
Update hwpmc to support the Xeon class of Ivybridge processors. case 0x3E: /* Per Intel document 325462-045US 01/2013. */
Add manpage to document all the goodness that is available in this processor model.
No support for uncore events at this time.
Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks
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241738 |
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19-Oct-2012 |
sbruno |
Update hwpmc to support the Xeon class of Sandybridge processors. (Model 0x2D /* Per Intel document 253669-044US 08/2012. */)
Add manpage to document all the goodness that is available in this processor model.
No support for uncore events at this time.
Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ fabient@ Obtained from: Yahoo! Inc. MFC after: 2 weeks
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240164 |
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06-Sep-2012 |
fabient |
Add Intel Ivy Bridge support to hwpmc(9). Update offcore RSP token for Sandy Bridge. Note: No uncore support.
Will works on Family 6 Model 3a.
MFC after: 1 month Tested by: bapt, grehan
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237196 |
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17-Jun-2012 |
davide |
Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D). Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a panic of the machine.
Approved by: gnn (mentor) MFC after: 3 days
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235229 |
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10-May-2012 |
fabient |
Remove out of date KASSERT that fire with soft PMC.
MFC after: 1 week
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233628 |
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28-Mar-2012 |
fabient |
Add software PMC support.
New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8).
Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions.
Sponsored by: NETASQ MFC after: 1 month
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233569 |
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27-Mar-2012 |
gonzo |
Fix crash on VirtualBox (and probably on some real hardware):
- Do not cover error returned by pmc_core_initialize with the result of pmc_uncore_initialize, fail right away. - Give a user something to report instead failing silently
Reported by: Alexandr Kovalenko <never@nevermind.kiev.ua>
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232366 |
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01-Mar-2012 |
davide |
- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture
Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks
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206089 |
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02-Apr-2010 |
fabient |
- Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token.
Sponsored by: NETASQ
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200669 |
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18-Dec-2009 |
jkoshy |
Recognize Intel CPUs with Family 0x6, Models 0x1E and 0x1F.
Submitted by: Marc Unangst <mju at panasas dot com>
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187761 |
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27-Jan-2009 |
jeff |
- Add support for nehalem/corei7 cpus. This supports all of the core counters defined in the reference manual. It does not support the 'uncore' events.
Reviewed by: jkoshy Sponsored by: Nokia
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185585 |
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03-Dec-2008 |
jkoshy |
Fixes for Core2 Extreme support.
Submitted by: "Artem Belevich" <artemb at gmail dot com>
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185363 |
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27-Nov-2008 |
jkoshy |
- Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and model 0x1C (Atom).
In these CPUs, the actual numbers, kinds and widths of PMCs present need to queried at run time. Support for specific "architectural" events also needs to be queried at run time.
Model 0xE CPUs support programmable PMCs, subsequent CPUs additionally support "fixed-function" counters.
- Use event names that are close to vendor documentation, taking in account that: - events with identical semantics on two or more CPUs in this family can have differing names in vendor documentation, - identical vendor event names may map to differing events across CPUs, - each type of CPU supports a different subset of measurable events.
Fixed-function and programmable counters both use the same vendor names for events. The use of a class name prefix ("iaf-" or "iap-" respectively) permits these to be distinguished.
- In libpmc, refactor pmc_name_of_event() into a public interface and an internal helper function, for use by log handling code.
- Minor code tweaks: staticize a global, freshen a few comments.
Tested by: gnn
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185341 |
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26-Nov-2008 |
jkim |
Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by: jhb, peter (early amd64 version)
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184993 |
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15-Nov-2008 |
jkoshy |
Fix assertions.
Reported by: keramida
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184802 |
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09-Nov-2008 |
jkoshy |
- Separate PMC class dependent code from other kinds of machine dependencies. A 'struct pmc_classdep' structure describes operations on PMCs; 'struct pmc_mdep' contains one or more 'struct pmc_classdep' structures depending on the CPU in question.
Inside PMC class dependent code, row indices are relative to the PMCs supported by the PMC class; MI code in "hwpmc_mod.c" translates global row indices before invoking class dependent operations.
- Augment the OP_GETCPUINFO request with the number of PMCs present in a PMC class.
- Move code common to Intel CPUs to file "hwpmc_intel.c".
- Move TSC handling to file "hwpmc_tsc.c".
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