hwpmc_intel.c revision 185341
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 185341 2008-11-26 19:25:13Z jkim $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44static int 45intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46{ 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59} 60 61static int 62intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63{ 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74} 75 76struct pmc_mdep * 77pmc_intel_initialize(void) 78{ 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 91 switch (cpu_id & 0xF00) { 92#if defined(__i386__) 93 case 0x500: /* Pentium family processors */ 94 cputype = PMC_CPU_INTEL_P5; 95 break; 96 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 97 switch ((cpu_id & 0xF0) >> 4) { /* model number field */ 98 case 0x1: 99 cputype = PMC_CPU_INTEL_P6; 100 break; 101 case 0x3: case 0x5: 102 cputype = PMC_CPU_INTEL_PII; 103 break; 104 case 0x6: 105 cputype = PMC_CPU_INTEL_CL; 106 break; 107 case 0x7: case 0x8: case 0xA: case 0xB: 108 cputype = PMC_CPU_INTEL_PIII; 109 break; 110 case 0x9: case 0xD: 111 cputype = PMC_CPU_INTEL_PM; 112 break; 113 } 114 break; 115#endif 116#if defined(__i386__) || defined(__amd64__) 117 case 0xF00: /* P4 */ 118 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 119 if (model >= 0 && model <= 6) /* known models */ 120 cputype = PMC_CPU_INTEL_PIV; 121 break; 122 } 123#endif 124 125 if ((int) cputype == -1) { 126 printf("pmc: Unknown Intel CPU.\n"); 127 return (NULL); 128 } 129 130 pmc_mdep = malloc(sizeof(struct pmc_mdep) + nclasses * 131 sizeof(struct pmc_classdep), M_PMC, M_WAITOK|M_ZERO); 132 133 pmc_mdep->pmd_cputype = cputype; 134 pmc_mdep->pmd_nclass = nclasses; 135 136 pmc_mdep->pmd_switch_in = intel_switch_in; 137 pmc_mdep->pmd_switch_out = intel_switch_out; 138 139 ncpus = pmc_cpu_max(); 140 141 error = pmc_tsc_initialize(pmc_mdep, ncpus); 142 if (error) 143 goto error; 144 145 switch (cputype) { 146#if defined(__i386__) || defined(__amd64__) 147 148 /* 149 * Intel Pentium 4 Processors, and P4/EMT64 processors. 150 */ 151 152 case PMC_CPU_INTEL_PIV: 153 error = pmc_p4_initialize(pmc_mdep, ncpus); 154 155 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P4_NPMCS, 156 ("[intel,%d] incorrect npmc count %d", __LINE__, 157 pmc_mdep->pmd_npmc)); 158 break; 159#endif 160 161#if defined(__i386__) 162 /* 163 * P6 Family Processors 164 */ 165 166 case PMC_CPU_INTEL_P6: 167 case PMC_CPU_INTEL_CL: 168 case PMC_CPU_INTEL_PII: 169 case PMC_CPU_INTEL_PIII: 170 case PMC_CPU_INTEL_PM: 171 error = pmc_p6_initialize(pmc_mdep, ncpus); 172 173 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + P6_NPMCS, 174 ("[intel,%d] incorrect npmc count %d", __LINE__, 175 pmc_mdep->pmd_npmc)); 176 break; 177 178 /* 179 * Intel Pentium PMCs. 180 */ 181 182 case PMC_CPU_INTEL_P5: 183 error = pmc_p5_initialize(pmc_mdep, ncpus); 184 185 KASSERT(pmc_mdep->pmd_npmc == TSC_NPMCS + PENTIUM_NPMCS, 186 ("[intel,%d] incorrect npmc count %d", __LINE__, 187 md->pmd_npmc)); 188 break; 189#endif 190 191 default: 192 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 193 } 194 195 196 error: 197 if (error) { 198 free(pmc_mdep, M_PMC); 199 pmc_mdep = NULL; 200 } 201 202 return (pmc_mdep); 203} 204 205void 206pmc_intel_finalize(struct pmc_mdep *md) 207{ 208 pmc_tsc_finalize(md); 209 210 switch (md->pmd_cputype) { 211#if defined(__i386__) || defined(__amd64__) 212 case PMC_CPU_INTEL_PIV: 213 pmc_p4_finalize(md); 214 break; 215#endif 216#if defined(__i386__) 217 case PMC_CPU_INTEL_P6: 218 case PMC_CPU_INTEL_CL: 219 case PMC_CPU_INTEL_PII: 220 case PMC_CPU_INTEL_PIII: 221 case PMC_CPU_INTEL_PM: 222 pmc_p6_finalize(md); 223 break; 224 case PMC_CPU_INTEL_P5: 225 pmc_p5_finalize(md); 226 break; 227#endif 228 default: 229 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 230 } 231} 232