hwpmc_intel.c revision 248842
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Common code for handling Intel CPUs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_intel.c 248842 2013-03-28 19:15:54Z sbruno $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44static int 45intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46{ 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59} 60 61static int 62intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63{ 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74} 75 76struct pmc_mdep * 77pmc_intel_initialize(void) 78{ 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 91 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 92 93 switch (cpu_id & 0xF00) { 94#if defined(__i386__) 95 case 0x500: /* Pentium family processors */ 96 cputype = PMC_CPU_INTEL_P5; 97 break; 98#endif 99 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 100 switch (model) { 101#if defined(__i386__) 102 case 0x1: 103 cputype = PMC_CPU_INTEL_P6; 104 break; 105 case 0x3: case 0x5: 106 cputype = PMC_CPU_INTEL_PII; 107 break; 108 case 0x6: case 0x16: 109 cputype = PMC_CPU_INTEL_CL; 110 break; 111 case 0x7: case 0x8: case 0xA: case 0xB: 112 cputype = PMC_CPU_INTEL_PIII; 113 break; 114 case 0x9: case 0xD: 115 cputype = PMC_CPU_INTEL_PM; 116 break; 117#endif 118 case 0xE: 119 cputype = PMC_CPU_INTEL_CORE; 120 break; 121 case 0xF: 122 cputype = PMC_CPU_INTEL_CORE2; 123 nclasses = 3; 124 break; 125 case 0x17: 126 cputype = PMC_CPU_INTEL_CORE2EXTREME; 127 nclasses = 3; 128 break; 129 case 0x1C: /* Per Intel document 320047-002. */ 130 cputype = PMC_CPU_INTEL_ATOM; 131 nclasses = 3; 132 break; 133 case 0x1A: 134 case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ 135 case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ 136 case 0x2E: 137 cputype = PMC_CPU_INTEL_COREI7; 138 nclasses = 5; 139 break; 140 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 141 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 142 cputype = PMC_CPU_INTEL_WESTMERE; 143 nclasses = 5; 144 break; 145 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 146 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 147 nclasses = 5; 148 break; 149 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 150 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 151 nclasses = 3; 152 break; 153 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 154 cputype = PMC_CPU_INTEL_IVYBRIDGE; 155 nclasses = 3; 156 break; 157 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 158 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 159 nclasses = 3; 160 break; 161 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 162 cputype = PMC_CPU_INTEL_HASWELL; 163 nclasses = 5; 164 break; 165 } 166 break; 167#if defined(__i386__) || defined(__amd64__) 168 case 0xF00: /* P4 */ 169 if (model >= 0 && model <= 6) /* known models */ 170 cputype = PMC_CPU_INTEL_PIV; 171 break; 172 } 173#endif 174 175 if ((int) cputype == -1) { 176 printf("pmc: Unknown Intel CPU.\n"); 177 return (NULL); 178 } 179 180 /* Allocate base class and initialize machine dependent struct */ 181 pmc_mdep = pmc_mdep_alloc(nclasses); 182 183 pmc_mdep->pmd_cputype = cputype; 184 pmc_mdep->pmd_switch_in = intel_switch_in; 185 pmc_mdep->pmd_switch_out = intel_switch_out; 186 187 ncpus = pmc_cpu_max(); 188 189 error = pmc_tsc_initialize(pmc_mdep, ncpus); 190 if (error) 191 goto error; 192 193 switch (cputype) { 194#if defined(__i386__) || defined(__amd64__) 195 /* 196 * Intel Core, Core 2 and Atom processors. 197 */ 198 case PMC_CPU_INTEL_ATOM: 199 case PMC_CPU_INTEL_CORE: 200 case PMC_CPU_INTEL_CORE2: 201 case PMC_CPU_INTEL_CORE2EXTREME: 202 case PMC_CPU_INTEL_COREI7: 203 case PMC_CPU_INTEL_IVYBRIDGE: 204 case PMC_CPU_INTEL_SANDYBRIDGE: 205 case PMC_CPU_INTEL_WESTMERE: 206 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 207 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 208 case PMC_CPU_INTEL_HASWELL: 209 error = pmc_core_initialize(pmc_mdep, ncpus); 210 break; 211 212 /* 213 * Intel Pentium 4 Processors, and P4/EMT64 processors. 214 */ 215 216 case PMC_CPU_INTEL_PIV: 217 error = pmc_p4_initialize(pmc_mdep, ncpus); 218 break; 219#endif 220 221#if defined(__i386__) 222 /* 223 * P6 Family Processors 224 */ 225 226 case PMC_CPU_INTEL_P6: 227 case PMC_CPU_INTEL_CL: 228 case PMC_CPU_INTEL_PII: 229 case PMC_CPU_INTEL_PIII: 230 case PMC_CPU_INTEL_PM: 231 error = pmc_p6_initialize(pmc_mdep, ncpus); 232 break; 233 234 /* 235 * Intel Pentium PMCs. 236 */ 237 238 case PMC_CPU_INTEL_P5: 239 error = pmc_p5_initialize(pmc_mdep, ncpus); 240 break; 241#endif 242 243 default: 244 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 245 } 246 247 if (error) 248 goto error; 249 250 /* 251 * Init the uncore class. 252 */ 253#if defined(__i386__) || defined(__amd64__) 254 switch (cputype) { 255 /* 256 * Intel Corei7 and Westmere processors. 257 */ 258 case PMC_CPU_INTEL_COREI7: 259 case PMC_CPU_INTEL_HASWELL: 260 case PMC_CPU_INTEL_SANDYBRIDGE: 261 case PMC_CPU_INTEL_WESTMERE: 262 error = pmc_uncore_initialize(pmc_mdep, ncpus); 263 break; 264 default: 265 break; 266 } 267#endif 268 269 error: 270 if (error) { 271 free(pmc_mdep, M_PMC); 272 pmc_mdep = NULL; 273 } 274 275 return (pmc_mdep); 276} 277 278void 279pmc_intel_finalize(struct pmc_mdep *md) 280{ 281 pmc_tsc_finalize(md); 282 283 switch (md->pmd_cputype) { 284#if defined(__i386__) || defined(__amd64__) 285 case PMC_CPU_INTEL_ATOM: 286 case PMC_CPU_INTEL_CORE: 287 case PMC_CPU_INTEL_CORE2: 288 case PMC_CPU_INTEL_CORE2EXTREME: 289 case PMC_CPU_INTEL_COREI7: 290 case PMC_CPU_INTEL_HASWELL: 291 case PMC_CPU_INTEL_IVYBRIDGE: 292 case PMC_CPU_INTEL_SANDYBRIDGE: 293 case PMC_CPU_INTEL_WESTMERE: 294 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 295 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 296 pmc_core_finalize(md); 297 break; 298 299 case PMC_CPU_INTEL_PIV: 300 pmc_p4_finalize(md); 301 break; 302#endif 303#if defined(__i386__) 304 case PMC_CPU_INTEL_P6: 305 case PMC_CPU_INTEL_CL: 306 case PMC_CPU_INTEL_PII: 307 case PMC_CPU_INTEL_PIII: 308 case PMC_CPU_INTEL_PM: 309 pmc_p6_finalize(md); 310 break; 311 case PMC_CPU_INTEL_P5: 312 pmc_p5_finalize(md); 313 break; 314#endif 315 default: 316 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 317 } 318 319 /* 320 * Uncore. 321 */ 322#if defined(__i386__) || defined(__amd64__) 323 switch (md->pmd_cputype) { 324 case PMC_CPU_INTEL_COREI7: 325 case PMC_CPU_INTEL_HASWELL: 326 case PMC_CPU_INTEL_SANDYBRIDGE: 327 case PMC_CPU_INTEL_WESTMERE: 328 pmc_uncore_finalize(md); 329 break; 330 default: 331 break; 332 } 333#endif 334} 335