| /linux-master/drivers/staging/fbtft/ |
| H A D | fb_upd161704.c | 31 write_reg(par, 0x0003, 0x0001); /* Soft reset */
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */
47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */
49 write_reg(pa
[all...] |
| H A D | fb_tinylcd.c | 24 write_reg(par, 0xB0, 0x80);
25 write_reg(par, 0xC0, 0x0A, 0x0A);
26 write_reg(par, 0xC1, 0x45, 0x07);
27 write_reg(par, 0xC2, 0x33);
28 write_reg(par, 0xC5, 0x00, 0x42, 0x80);
29 write_reg(par, 0xB1, 0xD0, 0x11);
30 write_reg(par, 0xB4, 0x02);
31 write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
32 write_reg(par, 0xB7, 0x07);
33 write_reg(pa
[all...] |
| H A D | fb_ili9320.c | 26 write_reg(par, 0x0000);
49 write_reg(par, 0x00E5, 0x8000);
52 write_reg(par, 0x0000, 0x0001);
55 write_reg(par, 0x0001, 0x0100);
58 write_reg(par, 0x0002, 0x0700);
61 write_reg(par, 0x0004, 0x0000);
64 write_reg(par, 0x0008, 0x0202);
67 write_reg(par, 0x0009, 0x0000);
70 write_reg(par, 0x000A, 0x0000);
73 write_reg(pa
[all...] |
| H A D | fb_bd663474.c | 31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */
35 write_reg(par, 0x100, 0x0000); /* power supply setup */
36 write_reg(par, 0x101, 0x0000);
37 write_reg(par, 0x102, 0x3110);
38 write_reg(par, 0x103, 0xe200);
39 write_reg(par, 0x110, 0x009d);
40 write_reg(par, 0x111, 0x0022);
41 write_reg(par, 0x100, 0x0120);
44 write_reg(par, 0x100, 0x3120);
47 write_reg(pa
[all...] |
| H A D | fb_ili9325.c | 96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */
101 write_reg(par, 0x0004, 0x0000); /* Resize register */
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */
104 write_reg(par, 0x000A, 0x0000); /* FMARK function */
105 write_reg(pa
[all...] |
| H A D | fb_s6d1121.c | 33 write_reg(par, 0x0011, 0x2004);
34 write_reg(par, 0x0013, 0xCC00);
35 write_reg(par, 0x0015, 0x2600);
36 write_reg(par, 0x0014, 0x252A);
37 write_reg(par, 0x0012, 0x0033);
38 write_reg(par, 0x0013, 0xCC04);
39 write_reg(par, 0x0013, 0xCC06);
40 write_reg(par, 0x0013, 0xCC4F);
41 write_reg(par, 0x0013, 0x674F);
42 write_reg(pa
[all...] |
| H A D | fb_ssd1289.c | 30 write_reg(par, 0x00, 0x0001);
31 write_reg(par, 0x03, 0xA8A4);
32 write_reg(par, 0x0C, 0x0000);
33 write_reg(par, 0x0D, 0x080C);
34 write_reg(par, 0x0E, 0x2B00);
35 write_reg(par, 0x1E, 0x00B7);
36 write_reg(par, 0x01,
38 write_reg(par, 0x02, 0x0600);
39 write_reg(par, 0x10, 0x0000);
40 write_reg(pa
[all...] |
| H A D | fb_hx8347d.c | 28 write_reg(par, 0xEA, 0x00);
29 write_reg(par, 0xEB, 0x20);
30 write_reg(par, 0xEC, 0x0C);
31 write_reg(par, 0xED, 0xC4);
32 write_reg(par, 0xE8, 0x40);
33 write_reg(par, 0xE9, 0x38);
34 write_reg(par, 0xF1, 0x01);
35 write_reg(par, 0xF2, 0x10);
36 write_reg(par, 0x27, 0xA3);
39 write_reg(pa
[all...] |
| H A D | fb_seps525.c | 103 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03);
106 write_reg(par, SEPS525_REDUCE_CURRENT, 0x00);
109 write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00);
111 write_reg(par, SEPS525_OSC_CTL, 0x01);
113 write_reg(par, SEPS525_CLOCK_DIV, 0x90);
115 write_reg(par, SEPS525_IREF, 0x01);
118 write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04);
119 write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05);
120 write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05);
123 write_reg(pa
[all...] |
| H A D | fb_ssd1305.c | 22 * write_reg() caveat:
25 * write_reg(par, val1, val2);
28 * write_reg(par, val1);
29 * write_reg(par, val2);
47 write_reg(par, 0xAE);
50 write_reg(par, 0xD5);
51 write_reg(par, 0x80);
54 write_reg(par, 0xA8);
56 write_reg(par, 0x3F);
58 write_reg(pa
[all...] |
| H A D | fb_ra8875.c | 55 write_reg(par, 0x88, 0x0A);
56 write_reg(par, 0x89, 0x02);
59 write_reg(par, 0x10, 0x0C);
61 write_reg(par, 0x04, 0x03);
64 write_reg(par, 0x14, 0x27);
65 write_reg(par, 0x15, 0x00);
66 write_reg(par, 0x16, 0x05);
67 write_reg(par, 0x17, 0x04);
68 write_reg(par, 0x18, 0x03);
70 write_reg(pa
[all...] |
| H A D | fb_ili9341.c | 34 write_reg(par, MIPI_DCS_SOFT_RESET);
36 write_reg(par, MIPI_DCS_SET_DISPLAY_OFF);
38 write_reg(par, 0xCF, 0x00, 0x83, 0x30);
39 write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81);
40 write_reg(par, 0xE8, 0x85, 0x01, 0x79);
41 write_reg(par, 0xCB, 0x39, 0X2C, 0x00, 0x34, 0x02);
42 write_reg(par, 0xF7, 0x20);
43 write_reg(par, 0xEA, 0x00, 0x00);
45 write_reg(par, 0xC0, 0x26);
46 write_reg(pa
[all...] |
| H A D | fb_ssd1306.c | 21 * write_reg() caveat:
24 * write_reg(par, val1, val2);
27 * write_reg(par, val1);
28 * write_reg(par, val2);
46 write_reg(par, 0xAE);
49 write_reg(par, 0xD5);
50 write_reg(par, 0x80);
53 write_reg(par, 0xA8);
55 write_reg(par, 0x3F);
57 write_reg(pa
[all...] |
| H A D | fb_hx8353d.c | 26 write_reg(par, 0xB9, 0xFF, 0x83, 0x53);
29 write_reg(par, 0xB0, 0x3C, 0x01);
32 write_reg(par, 0xB6, 0x94, 0x6C, 0x50);
35 write_reg(par, 0xB1, 0x00, 0x01, 0x1B, 0x03, 0x01, 0x08, 0x77, 0x89);
38 write_reg(par, 0x3A, 0x05);
41 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0xC0);
44 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
48 write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
51 write_reg(par, MIPI_DCS_WRITE_LUT,
67 write_reg(pa
[all...] |
| H A D | fb_ili9340.c | 25 write_reg(par, 0xEF, 0x03, 0x80, 0x02);
26 write_reg(par, 0xCF, 0x00, 0XC1, 0X30);
27 write_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81);
28 write_reg(par, 0xE8, 0x85, 0x00, 0x78);
29 write_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02);
30 write_reg(par, 0xF7, 0x20);
31 write_reg(par, 0xEA, 0x00, 0x00);
34 write_reg(par, 0xC0, 0x23);
37 write_reg(par, 0xC1, 0x10);
40 write_reg(pa
[all...] |
| H A D | fb_uc1701.c | 68 write_reg(par, LCD_RESET_CMD);
72 write_reg(par, LCD_START_LINE);
75 write_reg(par, LCD_BOTTOMVIEW | 1);
78 write_reg(par, LCD_SCAN_DIR | 0x00);
81 write_reg(par, LCD_ALL_PIXEL | 0);
84 write_reg(par, LCD_DISPLAY_INVERT | 0);
87 write_reg(par, LCD_BIAS | 0);
90 write_reg(par, LCD_POWER_CONTROL | 0x07);
93 write_reg(par, LCD_VOLTAGE | 0x07);
96 write_reg(pa
[all...] |
| H A D | fb_hx8357d.c | 30 write_reg(par, MIPI_DCS_SOFT_RESET);
34 write_reg(par, HX8357D_SETC, 0xFF, 0x83, 0x57);
38 write_reg(par, HX8357_SETRGB, 0x00, 0x00, 0x06, 0x06);
41 write_reg(par, HX8357D_SETCOM, 0x25);
44 write_reg(par, HX8357_SETOSC, 0x68);
47 write_reg(par, HX8357_SETPANEL, 0x05);
49 write_reg(par, HX8357_SETPWR1,
57 write_reg(par, HX8357D_SETSTBA,
65 write_reg(par, HX8357D_SETCYC,
74 write_reg(pa
[all...] |
| H A D | fb_ssd1351.c | 38 write_reg(par, 0xfd, 0x12); /* Command Lock */
39 write_reg(par, 0xfd, 0xb1); /* Command Lock */
40 write_reg(par, 0xae); /* Display Off */
41 write_reg(par, 0xb3, 0xf1); /* Front Clock Div */
42 write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */
43 write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */
44 write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */
45 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */
46 write_reg(par, 0xa2, 0x00); /* Set Display Offset */
47 write_reg(pa
[all...] |
| H A D | fb_hx8340bn.c | 45 write_reg(par, 0xC1, 0xFF, 0x83, 0x40);
53 write_reg(par, 0x11);
57 write_reg(par, 0xCA, 0x70, 0x00, 0xD9);
65 write_reg(par, 0xB0, 0x01, 0x11);
68 write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06);
78 write_reg(par, 0xB5, 0x35, 0x20, 0x45);
87 write_reg(par, 0xB4, 0x33, 0x25, 0x4C);
96 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
103 write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
111 write_reg(pa
[all...] |
| H A D | fb_tls8204.c | 38 write_reg(par, 0x21); /* 5:1 1
46 write_reg(par, 0x10 | (bs & 0x7));
55 write_reg(par, 0x04 | (64 >> 6));
56 write_reg(par, 0x40 | (64 & 0x3F));
59 write_reg(par, 0x20);
62 write_reg(par, 0x08 | 4);
75 write_reg(par, 0x80); /* 7:1 1
80 write_reg(par, 0x40); /* 7:0 0
98 write_reg(par, 0x80 | 0);
99 write_reg(pa
[all...] |
| H A D | fb_ssd1325.c | 23 * write_reg() caveat:
26 * write_reg(par, val1, val2);
29 * write_reg(par, val1);
30 * write_reg(par, val2);
38 write_reg(par, 0xb3);
39 write_reg(par, 0xf0);
40 write_reg(par, 0xae);
41 write_reg(par, 0xa1);
42 write_reg(par, 0x00);
43 write_reg(pa
[all...] |
| H A D | fb_ili9163.c | 79 write_reg(par, MIPI_DCS_SOFT_RESET); /* software reset */
81 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); /* exit sleep */
83 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
85 write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x02);
87 write_reg(par, CMD_GAMRSEL, 0x01); /* Enable Gamma adj */
89 write_reg(par, MIPI_DCS_ENTER_NORMAL_MODE);
90 write_reg(par, CMD_DFUNCTR, 0xff, 0x06);
92 write_reg(par, CMD_FRMCTR1, 0x08, 0x02);
93 write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */
95 write_reg(pa
[all...] |
| H A D | fb_ssd1331.c | 29 write_reg(par, 0xae); /* Display Off */
33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2));
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2));
37 write_reg(par, 0x72); /* RGB colour */
38 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */
39 write_reg(par, 0xa2, 0x00); /* Set Display Offset */
40 write_reg(par, 0xa4); /* NORMALDISPLAY */
41 write_reg(par, 0xa8, 0x3f); /* Set multiplex */
42 write_reg(par, 0xad, 0x8e); /* Set master */
43 /* write_reg(pa
[all...] |
| H A D | fb_sh1106.c | 38 write_reg(par, 0xAE);
41 write_reg(par, 0xD5, 0x80);
44 write_reg(par, 0xA8, par->info->var.yres - 1);
47 write_reg(par, 0xD3, 0x00);
50 write_reg(par, 0x40 | 0x0);
54 write_reg(par, 0xA0 | 0x1);
58 write_reg(par, 0xC8);
63 write_reg(par, 0xDA, 0x12);
66 write_reg(par, 0xDA, 0x12);
69 write_reg(pa
[all...] |
| /linux-master/arch/sh/boards/mach-kfr2r09/ |
| H A D | lcd_wqvga.c | 65 static void write_reg(void *sohandle, function
82 write_reg(sohandle, so, 1, data[i]);
91 write_reg(sohandle, so, 0, 0xb0);
92 write_reg(sohandle, so, 1, 0x00);
95 write_reg(sohandle, so, 0, 0xb1);
96 write_reg(sohandle, so, 1, 0x00);
99 write_reg(sohandle, so, 0, 0xbf);
117 write_reg(sohandle, so, 0, 0x2c);
130 write_reg(sohandle, so, 1, 0x00);
137 write_reg(sohandl
[all...] |