staging/fbtft/fb_ili9325.c

96 	write_reg(par, 0x00E3, 0x3008); /* Set internal timing */
97 	write_reg(par, 0x00E7, 0x0012); /* Set internal timing */
98 	write_reg(par, 0x00EF, 0x1231); /* Set internal timing */
99 	write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */
100 	write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */
101 	write_reg(par, 0x0004, 0x0000); /* Resize register */
102 	write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */
103 	write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */
104 	write_reg(par, 0x000A, 0x0000); /* FMARK function */
105 	write_reg(par, 0x000C, 0x0000); /* RGB interface setting */
106 	write_reg(par, 0x000D, 0x0000); /* Frame marker Position */
107 	write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */
110 	write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
111 	write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */
112 	write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */
113 	write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */
115 	write_reg(par, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */
117 	write_reg(par, 0x0011, 0x220 | vc); /* DC1[2:0], DC0[2:0], VC[2:0] */
119 	write_reg(par, 0x0012, vrh); /* Internal reference voltage= Vci; */
121 	write_reg(par, 0x0013, vdv << 8); /* Set VDV[4:0] for VCOM amplitude */
122 	write_reg(par, 0x0029, vcm); /* Set VCM[5:0] for VCOMH */
123 	write_reg(par, 0x002B, 0x000C); /* Set Frame Rate */
125 	write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */
126 	write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */
129 	write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */
130 	write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */
131 	write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */
132 	write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */
133 	write_reg(par, 0x0060, 0xA700); /* Gate Scan Line */
134 	write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */
135 	write_reg(par, 0x006A, 0x0000); /* set scrolling line */
138 	write_reg(par, 0x0080, 0x0000);
139 	write_reg(par, 0x0081, 0x0000);
140 	write_reg(par, 0x0082, 0x0000);
141 	write_reg(par, 0x0083, 0x0000);
142 	write_reg(par, 0x0084, 0x0000);
143 	write_reg(par, 0x0085, 0x0000);
146 	write_reg(par, 0x0090, 0x0010);
147 	write_reg(par, 0x0092, 0x0600);
148 	write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */
159 		write_reg(par, 0x0020, xs);
160 		write_reg(par, 0x0021, ys);
163 		write_reg(par, 0x0020, WIDTH - 1 - xs);
164 		write_reg(par, 0x0021, HEIGHT - 1 - ys);
167 		write_reg(par, 0x0020, WIDTH - 1 - ys);
168 		write_reg(par, 0x0021, xs);
171 		write_reg(par, 0x0020, ys);
172 		write_reg(par, 0x0021, HEIGHT - 1 - xs);
175 	write_reg(par, 0x0022); /* Write Data to GRAM */
183 		write_reg(par, 0x03, 0x0030 | (par->bgr << 12));
186 		write_reg(par, 0x03, 0x0000 | (par->bgr << 12));
189 		write_reg(par, 0x03, 0x0028 | (par->bgr << 12));
192 		write_reg(par, 0x03, 0x0018 | (par->bgr << 12));
218 	write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4));
219 	write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6));
220 	write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8));
221 	write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2));
222 	write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0));
224 	write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4));
225 	write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6));
226 	write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8));
227 	write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2));
228 	write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0));