Lines Matching refs:write_reg
29 write_reg(par, 0xae); /* Display Off */
33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2));
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2));
37 write_reg(par, 0x72); /* RGB colour */
38 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */
39 write_reg(par, 0xa2, 0x00); /* Set Display Offset */
40 write_reg(par, 0xa4); /* NORMALDISPLAY */
41 write_reg(par, 0xa8, 0x3f); /* Set multiplex */
42 write_reg(par, 0xad, 0x8e); /* Set master */
43 /* write_reg(par, 0xb0, 0x0b); Set power mode */
44 write_reg(par, 0xb1, 0x31); /* Precharge */
45 write_reg(par, 0xb3, 0xf0); /* Clock div */
46 write_reg(par, 0x8a, 0x64); /* Precharge A */
47 write_reg(par, 0x8b, 0x78); /* Precharge B */
48 write_reg(par, 0x8c, 0x64); /* Precharge C */
49 write_reg(par, 0xbb, 0x3a); /* Precharge level */
50 write_reg(par, 0xbe, 0x3e); /* vcomh */
51 write_reg(par, 0x87, 0x06); /* Master current */
52 write_reg(par, 0x81, 0x91); /* Contrast A */
53 write_reg(par, 0x82, 0x50); /* Contrast B */
54 write_reg(par, 0x83, 0x7d); /* Contrast C */
55 write_reg(par, 0xaf); /* Set Sleep Mode Display On */
62 write_reg(par, 0x15, xs, xe);
63 write_reg(par, 0x75, ys, ye);
153 write_reg(par, 0xB8,
173 write_reg(par, 0xAE);
175 write_reg(par, 0xAF);